1/* 2 * Google Gru (and derivatives) board device tree source 3 * 4 * Copyright 2016-2017 Google, Inc 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/input/input.h> 46#include "rk3399.dtsi" 47#include "rk3399-op1-opp.dtsi" 48 49/ { 50 chosen { 51 stdout-path = "serial2:115200n8"; 52 }; 53 54 /* 55 * Power Tree 56 * 57 * In general an attempt is made to include all rails called out by 58 * the schematic as long as those rails interact in some way with 59 * the AP. AKA: 60 * - Rails that only connect to the EC (or devices that the EC talks to) 61 * are not included. 62 * - Rails _are_ included if the rails go to the AP even if the AP 63 * doesn't currently care about them / they are always on. The idea 64 * here is that it makes it easier to map to the schematic or extend 65 * later. 66 * 67 * If two rails are substantially the same from the AP's point of 68 * view, though, we won't create a full fixed regulator. We'll just 69 * put the child rail as an alias of the parent rail. Sometimes rails 70 * look the same to the AP because one of these is true: 71 * - The EC controls the enable and the EC always enables a rail as 72 * long as the AP is running. 73 * - The rails are actually connected to each other by a jumper and 74 * the distinction is just there to add clarity/flexibility to the 75 * schematic. 76 */ 77 78 ppvar_sys: ppvar-sys { 79 compatible = "regulator-fixed"; 80 regulator-name = "ppvar_sys"; 81 regulator-always-on; 82 regulator-boot-on; 83 }; 84 85 pp900_ap: pp900-ap { 86 compatible = "regulator-fixed"; 87 regulator-name = "pp900_ap"; 88 89 /* EC turns on w/ pp900_ap_en; always on for AP */ 90 regulator-always-on; 91 regulator-boot-on; 92 regulator-min-microvolt = <900000>; 93 regulator-max-microvolt = <900000>; 94 95 vin-supply = <&ppvar_sys>; 96 }; 97 98 pp1200_lpddr: pp1200-lpddr { 99 compatible = "regulator-fixed"; 100 regulator-name = "pp1200_lpddr"; 101 102 /* EC turns on w/ lpddr_pwr_en; always on for AP */ 103 regulator-always-on; 104 regulator-boot-on; 105 regulator-min-microvolt = <1200000>; 106 regulator-max-microvolt = <1200000>; 107 108 vin-supply = <&ppvar_sys>; 109 }; 110 111 pp1800: pp1800 { 112 compatible = "regulator-fixed"; 113 regulator-name = "pp1800"; 114 115 /* Always on when ppvar_sys shows power good */ 116 regulator-always-on; 117 regulator-boot-on; 118 regulator-min-microvolt = <1800000>; 119 regulator-max-microvolt = <1800000>; 120 121 vin-supply = <&ppvar_sys>; 122 }; 123 124 pp3000: pp3000 { 125 compatible = "regulator-fixed"; 126 regulator-name = "pp3000"; 127 pinctrl-names = "default"; 128 pinctrl-0 = <&pp3000_en>; 129 130 enable-active-high; 131 gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; 132 133 regulator-always-on; 134 regulator-boot-on; 135 regulator-min-microvolt = <3000000>; 136 regulator-max-microvolt = <3000000>; 137 138 vin-supply = <&ppvar_sys>; 139 }; 140 141 pp3300: pp3300 { 142 compatible = "regulator-fixed"; 143 regulator-name = "pp3300"; 144 145 /* Always on; plain and simple */ 146 regulator-always-on; 147 regulator-boot-on; 148 regulator-min-microvolt = <3300000>; 149 regulator-max-microvolt = <3300000>; 150 151 vin-supply = <&ppvar_sys>; 152 }; 153 154 pp5000: pp5000 { 155 compatible = "regulator-fixed"; 156 regulator-name = "pp5000"; 157 158 /* EC turns on w/ pp5000_en; always on for AP */ 159 regulator-always-on; 160 regulator-boot-on; 161 regulator-min-microvolt = <5000000>; 162 regulator-max-microvolt = <5000000>; 163 164 vin-supply = <&ppvar_sys>; 165 }; 166 167 ppvar_bigcpu_pwm: ppvar-bigcpu-pwm { 168 compatible = "pwm-regulator"; 169 regulator-name = "ppvar_bigcpu_pwm"; 170 171 pwms = <&pwm1 0 3337 0>; 172 pwm-supply = <&ppvar_sys>; 173 pwm-dutycycle-range = <100 0>; 174 pwm-dutycycle-unit = <100>; 175 176 /* EC turns on w/ ap_core_en; always on for AP */ 177 regulator-always-on; 178 regulator-boot-on; 179 regulator-min-microvolt = <800107>; 180 regulator-max-microvolt = <1302232>; 181 }; 182 183 ppvar_bigcpu: ppvar-bigcpu { 184 compatible = "vctrl-regulator"; 185 regulator-name = "ppvar_bigcpu"; 186 187 regulator-min-microvolt = <800107>; 188 regulator-max-microvolt = <1302232>; 189 190 ctrl-supply = <&ppvar_bigcpu_pwm>; 191 ctrl-voltage-range = <800107 1302232>; 192 193 regulator-settling-time-up-us = <322>; 194 min-slew-down-rate = <225>; 195 ovp-threshold-percent = <16>; 196 }; 197 198 ppvar_litcpu_pwm: ppvar-litcpu-pwm { 199 compatible = "pwm-regulator"; 200 regulator-name = "ppvar_litcpu_pwm"; 201 202 pwms = <&pwm2 0 3337 0>; 203 pwm-supply = <&ppvar_sys>; 204 pwm-dutycycle-range = <100 0>; 205 pwm-dutycycle-unit = <100>; 206 207 /* EC turns on w/ ap_core_en; always on for AP */ 208 regulator-always-on; 209 regulator-boot-on; 210 regulator-min-microvolt = <797743>; 211 regulator-max-microvolt = <1307837>; 212 }; 213 214 ppvar_litcpu: ppvar-litcpu { 215 compatible = "vctrl-regulator"; 216 regulator-name = "ppvar_litcpu"; 217 218 regulator-min-microvolt = <797743>; 219 regulator-max-microvolt = <1307837>; 220 221 ctrl-supply = <&ppvar_litcpu_pwm>; 222 ctrl-voltage-range = <797743 1307837>; 223 224 regulator-settling-time-up-us = <384>; 225 min-slew-down-rate = <225>; 226 ovp-threshold-percent = <16>; 227 }; 228 229 ppvar_gpu_pwm: ppvar-gpu-pwm { 230 compatible = "pwm-regulator"; 231 regulator-name = "ppvar_gpu_pwm"; 232 233 pwms = <&pwm0 0 3337 0>; 234 pwm-supply = <&ppvar_sys>; 235 pwm-dutycycle-range = <100 0>; 236 pwm-dutycycle-unit = <100>; 237 238 /* EC turns on w/ ap_core_en; always on for AP */ 239 regulator-always-on; 240 regulator-boot-on; 241 regulator-min-microvolt = <786384>; 242 regulator-max-microvolt = <1217747>; 243 }; 244 245 ppvar_gpu: ppvar-gpu { 246 compatible = "vctrl-regulator"; 247 regulator-name = "ppvar_gpu"; 248 249 regulator-min-microvolt = <786384>; 250 regulator-max-microvolt = <1217747>; 251 252 ctrl-supply = <&ppvar_gpu_pwm>; 253 ctrl-voltage-range = <786384 1217747>; 254 255 regulator-settling-time-up-us = <390>; 256 min-slew-down-rate = <225>; 257 ovp-threshold-percent = <16>; 258 }; 259 260 ppvar_centerlogic_pwm: ppvar-centerlogic-pwm { 261 compatible = "pwm-regulator"; 262 regulator-name = "ppvar_centerlogic_pwm"; 263 264 pwms = <&pwm3 0 3337 0>; 265 pwm-supply = <&ppvar_sys>; 266 pwm-dutycycle-range = <100 0>; 267 pwm-dutycycle-unit = <100>; 268 269 /* EC turns on w/ ppvar_centerlogic_en; always on for AP */ 270 regulator-always-on; 271 regulator-boot-on; 272 regulator-min-microvolt = <799434>; 273 regulator-max-microvolt = <1049925>; 274 }; 275 276 ppvar_centerlogic: ppvar-centerlogic { 277 compatible = "vctrl-regulator"; 278 regulator-name = "ppvar_centerlogic"; 279 280 regulator-min-microvolt = <799434>; 281 regulator-max-microvolt = <1049925>; 282 283 ctrl-supply = <&ppvar_centerlogic_pwm>; 284 ctrl-voltage-range = <799434 1049925>; 285 286 regulator-settling-time-up-us = <378>; 287 min-slew-down-rate = <225>; 288 ovp-threshold-percent = <16>; 289 }; 290 291 /* Schematics call this PPVAR even though it's fixed */ 292 ppvar_logic: ppvar-logic { 293 compatible = "regulator-fixed"; 294 regulator-name = "ppvar_logic"; 295 296 /* EC turns on w/ ppvar_logic_en; always on for AP */ 297 regulator-always-on; 298 regulator-boot-on; 299 regulator-min-microvolt = <900000>; 300 regulator-max-microvolt = <900000>; 301 302 vin-supply = <&ppvar_sys>; 303 }; 304 305 /* EC turns on w/ pp900_ddrpll_en */ 306 pp900_ddrpll: pp900-ap { 307 }; 308 309 /* EC turns on w/ pp900_pcie_en */ 310 pp900_pcie: pp900-ap { 311 }; 312 313 /* EC turns on w/ pp900_pll_en */ 314 pp900_pll: pp900-ap { 315 }; 316 317 /* EC turns on w/ pp900_pmu_en */ 318 pp900_pmu: pp900-ap { 319 }; 320 321 /* EC turns on w/ pp900_usb_en */ 322 pp900_usb: pp900-ap { 323 }; 324 325 /* EC turns on w/ pp1800_s0_en_l */ 326 pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: pp1800 { 327 }; 328 329 /* EC turns on w/ pp1800_avdd_en_l */ 330 pp1800_avdd: pp1800 { 331 }; 332 333 /* EC turns on w/ pp1800_lid_en_l */ 334 pp1800_lid: pp1800_mic: pp1800 { 335 }; 336 337 /* EC turns on w/ lpddr_pwr_en */ 338 pp1800_lpddr: pp1800 { 339 }; 340 341 /* EC turns on w/ pp1800_pmu_en_l */ 342 pp1800_pmu: pp1800 { 343 }; 344 345 /* EC turns on w/ pp1800_usb_en_l */ 346 pp1800_usb: pp1800 { 347 }; 348 349 pp1500_ap_io: pp1500-ap-io { 350 compatible = "regulator-fixed"; 351 regulator-name = "pp1500_ap_io"; 352 pinctrl-names = "default"; 353 pinctrl-0 = <&pp1500_en>; 354 355 enable-active-high; 356 gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>; 357 358 regulator-always-on; 359 regulator-boot-on; 360 regulator-min-microvolt = <1500000>; 361 regulator-max-microvolt = <1500000>; 362 363 vin-supply = <&pp1800>; 364 }; 365 366 pp1800_audio: pp1800-audio { 367 compatible = "regulator-fixed"; 368 regulator-name = "pp1800_audio"; 369 pinctrl-names = "default"; 370 pinctrl-0 = <&pp1800_audio_en>; 371 372 enable-active-high; 373 gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>; 374 375 regulator-always-on; 376 regulator-boot-on; 377 378 vin-supply = <&pp1800>; 379 }; 380 381 /* gpio is shared with pp3300_wifi_bt */ 382 pp1800_pcie: pp1800-pcie { 383 compatible = "regulator-fixed"; 384 regulator-name = "pp1800_pcie"; 385 pinctrl-names = "default"; 386 pinctrl-0 = <&wlan_module_pd_l>; 387 388 enable-active-high; 389 gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; 390 391 /* 392 * Need to wait 1ms + ramp-up time before we can power on WiFi. 393 * This has been approximated as 8ms total. 394 */ 395 regulator-enable-ramp-delay = <8000>; 396 397 vin-supply = <&pp1800>; 398 }; 399 400 /* 401 * This is a bit of a hack. The WiFi module should be reset at least 402 * 1ms after its regulators have ramped up (max rampup time is ~7ms). 403 * With some stretching of the imagination, we can call the 1.8V 404 * regulator a supply. 405 */ 406 wlan_pd_n: wlan-pd-n { 407 compatible = "regulator-fixed"; 408 regulator-name = "wlan_pd_n"; 409 pinctrl-names = "default"; 410 pinctrl-0 = <&wlan_module_reset_l>; 411 412 enable-active-high; 413 gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; 414 415 vin-supply = <&pp1800_pcie>; 416 }; 417 418 /* Always on; plain and simple */ 419 pp3000_ap: pp3000_emmc: pp3000 { 420 }; 421 422 pp3000_sd_slot: pp3000-sd-slot { 423 compatible = "regulator-fixed"; 424 regulator-name = "pp3000_sd_slot"; 425 pinctrl-names = "default"; 426 pinctrl-0 = <&sd_slot_pwr_en>; 427 428 enable-active-high; 429 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; 430 431 vin-supply = <&pp3000>; 432 }; 433 434 /* 435 * Technically, this is a small abuse of 'regulator-gpio'; this 436 * regulator is a mux between pp1800 and pp3300. pp1800 and pp3300 are 437 * always on though, so it is sufficient to simply control the mux 438 * here. 439 */ 440 ppvar_sd_card_io: ppvar-sd-card-io { 441 compatible = "regulator-gpio"; 442 regulator-name = "ppvar_sd_card_io"; 443 pinctrl-names = "default"; 444 pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>; 445 446 enable-active-high; 447 enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; 448 gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; 449 states = <1800000 0x1 450 3000000 0x0>; 451 452 regulator-min-microvolt = <1800000>; 453 regulator-max-microvolt = <3000000>; 454 }; 455 456 /* EC turns on w/ pp3300_trackpad_en_l */ 457 pp3300_trackpad: pp3300-trackpad { 458 }; 459 460 /* EC turns on w/ pp3300_usb_en_l */ 461 pp3300_usb: pp3300 { 462 }; 463 464 pp3300_disp: pp3300-disp { 465 compatible = "regulator-fixed"; 466 regulator-name = "pp3300_disp"; 467 pinctrl-names = "default"; 468 pinctrl-0 = <&pp3300_disp_en>; 469 470 enable-active-high; 471 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; 472 473 startup-delay-us = <2000>; 474 vin-supply = <&pp3300>; 475 }; 476 477 /* gpio is shared with pp1800_pcie and pinctrl is set there */ 478 pp3300_wifi_bt: pp3300-wifi-bt { 479 compatible = "regulator-fixed"; 480 regulator-name = "pp3300_wifi_bt"; 481 482 enable-active-high; 483 gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; 484 485 vin-supply = <&pp3300>; 486 }; 487 488 /* EC turns on w/ usb_a_en */ 489 pp5000_usb_a_vbus: pp5000 { 490 }; 491 492 gpio_keys: gpio-keys { 493 compatible = "gpio-keys"; 494 pinctrl-names = "default"; 495 pinctrl-0 = <&bt_host_wake_l>; 496 497 wake-on-bt { 498 label = "Wake-on-Bluetooth"; 499 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; 500 linux,code = <KEY_WAKEUP>; 501 wakeup-source; 502 }; 503 }; 504 505 max98357a: max98357a { 506 compatible = "maxim,max98357a"; 507 pinctrl-names = "default"; 508 pinctrl-0 = <&sdmode_en>; 509 sdmode-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 510 sdmode-delay = <2>; 511 #sound-dai-cells = <0>; 512 status = "okay"; 513 }; 514 515 sound { 516 compatible = "rockchip,rk3399-gru-sound"; 517 rockchip,cpu = <&i2s0 &i2s2>; 518 rockchip,codec = <&max98357a &headsetcodec &codec>; 519 }; 520}; 521 522/* 523 * Set some suspend operating points to avoid OVP in suspend 524 * 525 * When we go into S3 ARM Trusted Firmware will transition our PWM regulators 526 * from wherever they're at back to the "default" operating point (whatever 527 * voltage we get when we set the PWM pins to "input"). 528 * 529 * This quick transition under light load has the possibility to trigger the 530 * regulator "over voltage protection" (OVP). 531 * 532 * To make extra certain that we don't hit this OVP at suspend time, we'll 533 * transition to a voltage that's much closer to the default (~1.0 V) so that 534 * there will not be a big jump. Technically we only need to get within 200 mV 535 * of the default voltage, but the speed here should be fast enough and we need 536 * suspend/resume to be rock solid. 537 */ 538 539&cluster0_opp { 540 opp05 { 541 opp-suspend; 542 }; 543}; 544 545&cluster1_opp { 546 opp06 { 547 opp-suspend; 548 }; 549}; 550 551&cpu_l0 { 552 cpu-supply = <&ppvar_litcpu>; 553}; 554 555&cpu_l1 { 556 cpu-supply = <&ppvar_litcpu>; 557}; 558 559&cpu_l2 { 560 cpu-supply = <&ppvar_litcpu>; 561}; 562 563&cpu_l3 { 564 cpu-supply = <&ppvar_litcpu>; 565}; 566 567&cpu_b0 { 568 cpu-supply = <&ppvar_bigcpu>; 569}; 570 571&cpu_b1 { 572 cpu-supply = <&ppvar_bigcpu>; 573}; 574 575 576&cru { 577 assigned-clocks = 578 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 579 <&cru PLL_NPLL>, 580 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 581 <&cru PCLK_PERIHP>, 582 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 583 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 584 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; 585 assigned-clock-rates = 586 <600000000>, <800000000>, 587 <1000000000>, 588 <150000000>, <75000000>, 589 <37500000>, 590 <100000000>, <100000000>, 591 <50000000>, <800000000>, 592 <100000000>, <50000000>; 593}; 594 595&emmc_phy { 596 status = "okay"; 597}; 598 599&gpu { 600 mali-supply = <&ppvar_gpu>; 601 status = "okay"; 602}; 603 604ap_i2c_mic: &i2c1 { 605 status = "okay"; 606 607 clock-frequency = <400000>; 608 609 /* These are relatively safe rise/fall times */ 610 i2c-scl-falling-time-ns = <50>; 611 i2c-scl-rising-time-ns = <300>; 612 613 headsetcodec: rt5514@57 { 614 compatible = "realtek,rt5514"; 615 reg = <0x57>; 616 realtek,dmic-init-delay-ms = <20>; 617 }; 618}; 619 620ap_i2c_ts: &i2c3 { 621 status = "okay"; 622 623 clock-frequency = <400000>; 624 625 /* These are relatively safe rise/fall times */ 626 i2c-scl-falling-time-ns = <50>; 627 i2c-scl-rising-time-ns = <300>; 628}; 629 630ap_i2c_tp: &i2c5 { 631 status = "okay"; 632 633 clock-frequency = <400000>; 634 635 /* These are relatively safe rise/fall times */ 636 i2c-scl-falling-time-ns = <50>; 637 i2c-scl-rising-time-ns = <300>; 638 639 /* 640 * Note strange pullup enable. Apparently this avoids leakage but 641 * still allows us to get nice 4.7K pullups for high speed i2c 642 * transfers. Basically we want the pullup on whenever the ap is 643 * alive, so the "en" pin just gets set to output high. 644 */ 645 pinctrl-0 = <&i2c5_xfer &ap_i2c_tp_pu_en>; 646}; 647 648ap_i2c_audio: &i2c8 { 649 status = "okay"; 650 651 clock-frequency = <400000>; 652 653 /* These are relatively safe rise/fall times */ 654 i2c-scl-falling-time-ns = <50>; 655 i2c-scl-rising-time-ns = <300>; 656 657 codec: da7219@1a { 658 compatible = "dlg,da7219"; 659 reg = <0x1a>; 660 interrupt-parent = <&gpio1>; 661 interrupts = <23 IRQ_TYPE_LEVEL_LOW>; 662 clocks = <&cru SCLK_I2S_8CH_OUT>; 663 clock-names = "mclk"; 664 dlg,micbias-lvl = <2600>; 665 dlg,mic-amp-in-sel = "diff"; 666 pinctrl-names = "default"; 667 pinctrl-0 = <&headset_int_l>; 668 VDD-supply = <&pp1800>; 669 VDDMIC-supply = <&pp3300>; 670 VDDIO-supply = <&pp1800>; 671 672 da7219_aad { 673 dlg,adc-1bit-rpt = <1>; 674 dlg,btn-avg = <4>; 675 dlg,btn-cfg = <50>; 676 dlg,mic-det-thr = <500>; 677 dlg,jack-ins-deb = <20>; 678 dlg,jack-det-rate = "32ms_64ms"; 679 dlg,jack-rem-deb = <1>; 680 681 dlg,a-d-btn-thr = <0xa>; 682 dlg,d-b-btn-thr = <0x16>; 683 dlg,b-c-btn-thr = <0x21>; 684 dlg,c-mic-btn-thr = <0x3E>; 685 }; 686 }; 687}; 688 689&i2s0 { 690 status = "okay"; 691}; 692 693&i2s2 { 694 status = "okay"; 695}; 696 697&io_domains { 698 status = "okay"; 699 700 audio-supply = <&pp1800_audio>; /* APIO5_VDD; 3d 4a */ 701 bt656-supply = <&pp1800_ap_io>; /* APIO2_VDD; 2a 2b */ 702 gpio1830-supply = <&pp3000_ap>; /* APIO4_VDD; 4c 4d */ 703 sdmmc-supply = <&ppvar_sd_card_io>; /* SDMMC0_VDD; 4b */ 704}; 705 706&pcie0 { 707 status = "okay"; 708 709 ep-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; 710 pinctrl-names = "default"; 711 pinctrl-0 = <&pcie_clkreqn_cpm>, <&wifi_perst_l>; 712 vpcie3v3-supply = <&pp3300_wifi_bt>; 713 vpcie1v8-supply = <&wlan_pd_n>; /* HACK: see &wlan_pd_n */ 714 vpcie0v9-supply = <&pp900_pcie>; 715 716 pci_rootport: pcie@0,0 { 717 reg = <0x83000000 0x0 0x00000000 0x0 0x00000000>; 718 #address-cells = <3>; 719 #size-cells = <2>; 720 ranges; 721 722 mvl_wifi: wifi@0,0 { 723 compatible = "pci1b4b,2b42"; 724 reg = <0x83010000 0x0 0x00000000 0x0 0x00100000 725 0x83010000 0x0 0x00100000 0x0 0x00100000>; 726 interrupt-parent = <&gpio0>; 727 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 728 pinctrl-names = "default"; 729 pinctrl-0 = <&wlan_host_wake_l>; 730 wakeup-source; 731 }; 732 }; 733}; 734 735&pcie_phy { 736 status = "okay"; 737}; 738 739&pmu_io_domains { 740 status = "okay"; 741 742 pmu1830-supply = <&pp1800_pmu>; /* PMUIO2_VDD */ 743}; 744 745&pwm0 { 746 status = "okay"; 747}; 748 749&pwm1 { 750 status = "okay"; 751}; 752 753&pwm2 { 754 status = "okay"; 755}; 756 757&pwm3 { 758 status = "okay"; 759}; 760 761&sdhci { 762 /* 763 * Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the 764 * same (or nearly the same) performance for all eMMC that are intended 765 * to be used. 766 */ 767 assigned-clock-rates = <150000000>; 768 769 bus-width = <8>; 770 mmc-hs400-1_8v; 771 mmc-hs400-enhanced-strobe; 772 non-removable; 773 status = "okay"; 774}; 775 776&sdmmc { 777 status = "okay"; 778 779 /* 780 * Note: configure "sdmmc_cd" as card detect even though it's actually 781 * hooked to ground. Because we specified "cd-gpios" below dw_mmc 782 * should be ignoring card detect anyway. Specifying the pin as 783 * sdmmc_cd means that even if you've got GRF_SOC_CON7[12] (force_jtag) 784 * turned on that the system will still make sure the port is 785 * configured as SDMMC and not JTAG. 786 */ 787 pinctrl-names = "default"; 788 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_gpio 789 &sdmmc_bus4>; 790 791 bus-width = <4>; 792 cap-mmc-highspeed; 793 cap-sd-highspeed; 794 cd-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; 795 disable-wp; 796 sd-uhs-sdr12; 797 sd-uhs-sdr25; 798 sd-uhs-sdr50; 799 sd-uhs-sdr104; 800 vmmc-supply = <&pp3000_sd_slot>; 801 vqmmc-supply = <&ppvar_sd_card_io>; 802}; 803 804&spi1 { 805 status = "okay"; 806 807 pinctrl-names = "default", "sleep"; 808 pinctrl-1 = <&spi1_sleep>; 809 810 spiflash@0 { 811 compatible = "jedec,spi-nor"; 812 reg = <0>; 813 814 /* May run faster once verified. */ 815 spi-max-frequency = <10000000>; 816 }; 817}; 818 819&spi2 { 820 status = "okay"; 821 822 wacky_spi_audio: spi2@0 { 823 compatible = "realtek,rt5514"; 824 reg = <0>; 825 interrupt-parent = <&gpio1>; 826 interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; 827 pinctrl-names = "default"; 828 pinctrl-0 = <&mic_int>; 829 /* May run faster once verified. */ 830 spi-max-frequency = <10000000>; 831 wakeup-source; 832 }; 833}; 834 835&spi5 { 836 status = "okay"; 837 838 cros_ec: ec@0 { 839 compatible = "google,cros-ec-spi"; 840 reg = <0>; 841 interrupt-parent = <&gpio0>; 842 interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 843 pinctrl-names = "default"; 844 pinctrl-0 = <&ec_ap_int_l>; 845 spi-max-frequency = <3000000>; 846 847 i2c_tunnel: i2c-tunnel { 848 compatible = "google,cros-ec-i2c-tunnel"; 849 google,remote-bus = <4>; 850 #address-cells = <1>; 851 #size-cells = <0>; 852 }; 853 854 cros_ec_pwm: ec-pwm { 855 compatible = "google,cros-ec-pwm"; 856 #pwm-cells = <1>; 857 }; 858 }; 859}; 860 861&tsadc { 862 status = "okay"; 863 864 rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ 865 rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ 866}; 867 868&u2phy0 { 869 status = "okay"; 870}; 871 872&u2phy1 { 873 status = "okay"; 874}; 875 876&u2phy0_host { 877 status = "okay"; 878}; 879 880&u2phy1_host { 881 status = "okay"; 882}; 883 884&u2phy0_otg { 885 status = "okay"; 886}; 887 888&u2phy1_otg { 889 status = "okay"; 890}; 891 892&uart2 { 893 status = "okay"; 894}; 895 896&usb_host0_ehci { 897 status = "okay"; 898}; 899 900&usb_host0_ohci { 901 status = "okay"; 902}; 903 904&usb_host1_ehci { 905 status = "okay"; 906}; 907 908&usb_host1_ohci { 909 status = "okay"; 910}; 911 912&usbdrd3_0 { 913 status = "okay"; 914}; 915 916&usbdrd_dwc3_0 { 917 status = "okay"; 918 dr_mode = "host"; 919}; 920 921&usbdrd3_1 { 922 status = "okay"; 923}; 924 925&usbdrd_dwc3_1 { 926 status = "okay"; 927 dr_mode = "host"; 928}; 929 930#include <arm/cros-ec-keyboard.dtsi> 931#include <arm/cros-ec-sbs.dtsi> 932 933&pinctrl { 934 /* 935 * pinctrl settings for pins that have no real owners. 936 * 937 * At the moment settings are identical for S0 and S3, but if we later 938 * need to configure things differently for S3 we'll adjust here. 939 */ 940 pinctrl-names = "default"; 941 pinctrl-0 = < 942 &ap_pwroff /* AP will auto-assert this when in S3 */ 943 &clk_32k /* This pin is always 32k on gru boards */ 944 >; 945 946 pcfg_output_low: pcfg-output-low { 947 output-low; 948 }; 949 950 pcfg_output_high: pcfg-output-high { 951 output-high; 952 }; 953 954 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 955 bias-disable; 956 drive-strength = <8>; 957 }; 958 959 backlight-enable { 960 bl_en: bl-en { 961 rockchip,pins = <1 17 RK_FUNC_GPIO &pcfg_pull_none>; 962 }; 963 }; 964 965 cros-ec { 966 ec_ap_int_l: ec-ap-int-l { 967 rockchip,pins = <RK_GPIO0 1 RK_FUNC_GPIO &pcfg_pull_up>; 968 }; 969 }; 970 971 discrete-regulators { 972 pp1500_en: pp1500-en { 973 rockchip,pins = <RK_GPIO0 10 RK_FUNC_GPIO 974 &pcfg_pull_none>; 975 }; 976 977 pp1800_audio_en: pp1800-audio-en { 978 rockchip,pins = <RK_GPIO0 2 RK_FUNC_GPIO 979 &pcfg_pull_down>; 980 }; 981 982 pp3300_disp_en: pp3300-disp-en { 983 rockchip,pins = <RK_GPIO4 27 RK_FUNC_GPIO 984 &pcfg_pull_none>; 985 }; 986 987 pp3000_en: pp3000-en { 988 rockchip,pins = <RK_GPIO0 12 RK_FUNC_GPIO 989 &pcfg_pull_none>; 990 }; 991 992 sd_io_pwr_en: sd-io-pwr-en { 993 rockchip,pins = <RK_GPIO2 2 RK_FUNC_GPIO 994 &pcfg_pull_none>; 995 }; 996 997 sd_pwr_1800_sel: sd-pwr-1800-sel { 998 rockchip,pins = <RK_GPIO2 28 RK_FUNC_GPIO 999 &pcfg_pull_none>; 1000 }; 1001 1002 sd_slot_pwr_en: sd-slot-pwr-en { 1003 rockchip,pins = <RK_GPIO4 29 RK_FUNC_GPIO 1004 &pcfg_pull_none>; 1005 }; 1006 1007 wlan_module_pd_l: wlan-module-pd-l { 1008 rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO 1009 &pcfg_pull_down>; 1010 }; 1011 }; 1012 1013 codec { 1014 /* Has external pullup */ 1015 headset_int_l: headset-int-l { 1016 rockchip,pins = <1 23 RK_FUNC_GPIO &pcfg_pull_none>; 1017 }; 1018 1019 mic_int: mic-int { 1020 rockchip,pins = <1 13 RK_FUNC_GPIO &pcfg_pull_down>; 1021 }; 1022 }; 1023 1024 max98357a { 1025 sdmode_en: sdmode-en { 1026 rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_down>; 1027 }; 1028 }; 1029 1030 pcie { 1031 pcie_clkreqn_cpm: pci-clkreqn-cpm { 1032 /* 1033 * Since our pcie doesn't support ClockPM(CPM), we want 1034 * to hack this as gpio, so the EP could be able to 1035 * de-assert it along and make ClockPM(CPM) work. 1036 */ 1037 rockchip,pins = <2 26 RK_FUNC_GPIO &pcfg_pull_none>; 1038 }; 1039 }; 1040 1041 sdmmc { 1042 /* 1043 * We run sdmmc at max speed; bump up drive strength. 1044 * We also have external pulls, so disable the internal ones. 1045 */ 1046 sdmmc_bus4: sdmmc-bus4 { 1047 rockchip,pins = 1048 <4 8 RK_FUNC_1 &pcfg_pull_none_8ma>, 1049 <4 9 RK_FUNC_1 &pcfg_pull_none_8ma>, 1050 <4 10 RK_FUNC_1 &pcfg_pull_none_8ma>, 1051 <4 11 RK_FUNC_1 &pcfg_pull_none_8ma>; 1052 }; 1053 1054 sdmmc_clk: sdmmc-clk { 1055 rockchip,pins = 1056 <4 12 RK_FUNC_1 &pcfg_pull_none_8ma>; 1057 }; 1058 1059 sdmmc_cmd: sdmmc-cmd { 1060 rockchip,pins = 1061 <4 13 RK_FUNC_1 &pcfg_pull_none_8ma>; 1062 }; 1063 1064 /* 1065 * In our case the official card detect is hooked to ground 1066 * to avoid getting access to JTAG just by sticking something 1067 * in the SD card slot (see the force_jtag bit in the TRM). 1068 * 1069 * We still configure it as card detect because it doesn't 1070 * hurt and dw_mmc will ignore it. We make sure to disable 1071 * the pull though so we don't burn needless power. 1072 */ 1073 sdmmc_cd: sdmmc-cd { 1074 rockchip,pins = 1075 <0 7 RK_FUNC_1 &pcfg_pull_none>; 1076 }; 1077 1078 /* This is where we actually hook up CD; has external pull */ 1079 sdmmc_cd_gpio: sdmmc-cd-gpio { 1080 rockchip,pins = <4 24 RK_FUNC_GPIO &pcfg_pull_none>; 1081 }; 1082 }; 1083 1084 spi1 { 1085 spi1_sleep: spi1-sleep { 1086 /* 1087 * Pull down SPI1 CLK/CS/RX/TX during suspend, to 1088 * prevent leakage. 1089 */ 1090 rockchip,pins = <1 9 RK_FUNC_GPIO &pcfg_pull_down>, 1091 <1 10 RK_FUNC_GPIO &pcfg_pull_down>, 1092 <1 7 RK_FUNC_GPIO &pcfg_pull_down>, 1093 <1 8 RK_FUNC_GPIO &pcfg_pull_down>; 1094 }; 1095 }; 1096 1097 touchscreen { 1098 touch_int_l: touch-int-l { 1099 rockchip,pins = <3 13 RK_FUNC_GPIO &pcfg_pull_up>; 1100 }; 1101 1102 touch_reset_l: touch-reset-l { 1103 rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_pull_none>; 1104 }; 1105 }; 1106 1107 trackpad { 1108 ap_i2c_tp_pu_en: ap-i2c-tp-pu-en { 1109 rockchip,pins = <3 12 RK_FUNC_GPIO &pcfg_output_high>; 1110 }; 1111 1112 trackpad_int_l: trackpad-int-l { 1113 rockchip,pins = <1 4 RK_FUNC_GPIO &pcfg_pull_up>; 1114 }; 1115 }; 1116 1117 wifi { 1118 wifi_perst_l: wifi-perst-l { 1119 rockchip,pins = <2 27 RK_FUNC_GPIO &pcfg_pull_none>; 1120 }; 1121 1122 wlan_module_reset_l: wlan-module-reset-l { 1123 rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_pull_none>; 1124 }; 1125 1126 bt_host_wake_l: bt-host-wake-l { 1127 /* Kevin has an external pull up, but Gru does not */ 1128 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>; 1129 }; 1130 }; 1131 1132 write-protect { 1133 ap_fw_wp: ap-fw-wp { 1134 rockchip,pins = <1 18 RK_FUNC_GPIO &pcfg_pull_up>; 1135 }; 1136 }; 1137}; 1138