1 /*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/of.h>
27 #include <linux/of_platform.h>
28 #include <linux/of_device.h>
29 #include <linux/platform_data/davinci_asp.h>
30 #include <linux/math64.h>
31
32 #include <sound/asoundef.h>
33 #include <sound/core.h>
34 #include <sound/pcm.h>
35 #include <sound/pcm_params.h>
36 #include <sound/initval.h>
37 #include <sound/soc.h>
38 #include <sound/dmaengine_pcm.h>
39 #include <sound/omap-pcm.h>
40
41 #include "edma-pcm.h"
42 #include "davinci-mcasp.h"
43
44 #define MCASP_MAX_AFIFO_DEPTH 64
45
46 #ifdef CONFIG_PM
47 static u32 context_regs[] = {
48 DAVINCI_MCASP_TXFMCTL_REG,
49 DAVINCI_MCASP_RXFMCTL_REG,
50 DAVINCI_MCASP_TXFMT_REG,
51 DAVINCI_MCASP_RXFMT_REG,
52 DAVINCI_MCASP_ACLKXCTL_REG,
53 DAVINCI_MCASP_ACLKRCTL_REG,
54 DAVINCI_MCASP_AHCLKXCTL_REG,
55 DAVINCI_MCASP_AHCLKRCTL_REG,
56 DAVINCI_MCASP_PDIR_REG,
57 DAVINCI_MCASP_RXMASK_REG,
58 DAVINCI_MCASP_TXMASK_REG,
59 DAVINCI_MCASP_RXTDM_REG,
60 DAVINCI_MCASP_TXTDM_REG,
61 };
62
63 struct davinci_mcasp_context {
64 u32 config_regs[ARRAY_SIZE(context_regs)];
65 u32 afifo_regs[2]; /* for read/write fifo control registers */
66 u32 *xrsr_regs; /* for serializer configuration */
67 bool pm_state;
68 };
69 #endif
70
71 struct davinci_mcasp_ruledata {
72 struct davinci_mcasp *mcasp;
73 int serializers;
74 };
75
76 struct davinci_mcasp {
77 struct snd_dmaengine_dai_dma_data dma_data[2];
78 void __iomem *base;
79 u32 fifo_base;
80 struct device *dev;
81 struct snd_pcm_substream *substreams[2];
82 unsigned int dai_fmt;
83
84 /* McASP specific data */
85 int tdm_slots;
86 u32 tdm_mask[2];
87 int slot_width;
88 u8 op_mode;
89 u8 num_serializer;
90 u8 *serial_dir;
91 u8 version;
92 u8 bclk_div;
93 int streams;
94 u32 irq_request[2];
95 int dma_request[2];
96
97 int sysclk_freq;
98 bool bclk_master;
99
100 /* McASP FIFO related */
101 u8 txnumevt;
102 u8 rxnumevt;
103
104 bool dat_port;
105
106 /* Used for comstraint setting on the second stream */
107 u32 channels;
108
109 #ifdef CONFIG_PM_SLEEP
110 struct davinci_mcasp_context context;
111 #endif
112
113 struct davinci_mcasp_ruledata ruledata[2];
114 struct snd_pcm_hw_constraint_list chconstr[2];
115 };
116
mcasp_set_bits(struct davinci_mcasp * mcasp,u32 offset,u32 val)117 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
118 u32 val)
119 {
120 void __iomem *reg = mcasp->base + offset;
121 __raw_writel(__raw_readl(reg) | val, reg);
122 }
123
mcasp_clr_bits(struct davinci_mcasp * mcasp,u32 offset,u32 val)124 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
125 u32 val)
126 {
127 void __iomem *reg = mcasp->base + offset;
128 __raw_writel((__raw_readl(reg) & ~(val)), reg);
129 }
130
mcasp_mod_bits(struct davinci_mcasp * mcasp,u32 offset,u32 val,u32 mask)131 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
132 u32 val, u32 mask)
133 {
134 void __iomem *reg = mcasp->base + offset;
135 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
136 }
137
mcasp_set_reg(struct davinci_mcasp * mcasp,u32 offset,u32 val)138 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
139 u32 val)
140 {
141 __raw_writel(val, mcasp->base + offset);
142 }
143
mcasp_get_reg(struct davinci_mcasp * mcasp,u32 offset)144 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
145 {
146 return (u32)__raw_readl(mcasp->base + offset);
147 }
148
mcasp_set_ctl_reg(struct davinci_mcasp * mcasp,u32 ctl_reg,u32 val)149 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
150 {
151 int i = 0;
152
153 mcasp_set_bits(mcasp, ctl_reg, val);
154
155 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
156 /* loop count is to avoid the lock-up */
157 for (i = 0; i < 1000; i++) {
158 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
159 break;
160 }
161
162 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
163 printk(KERN_ERR "GBLCTL write error\n");
164 }
165
mcasp_is_synchronous(struct davinci_mcasp * mcasp)166 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
167 {
168 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
169 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
170
171 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
172 }
173
mcasp_start_rx(struct davinci_mcasp * mcasp)174 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
175 {
176 if (mcasp->rxnumevt) { /* enable FIFO */
177 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
178
179 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
180 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
181 }
182
183 /* Start clocks */
184 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
185 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
186 /*
187 * When ASYNC == 0 the transmit and receive sections operate
188 * synchronously from the transmit clock and frame sync. We need to make
189 * sure that the TX signlas are enabled when starting reception.
190 */
191 if (mcasp_is_synchronous(mcasp)) {
192 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
193 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
194 }
195
196 /* Activate serializer(s) */
197 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
198 /* Release RX state machine */
199 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
200 /* Release Frame Sync generator */
201 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
202 if (mcasp_is_synchronous(mcasp))
203 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
204
205 /* enable receive IRQs */
206 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
207 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
208 }
209
mcasp_start_tx(struct davinci_mcasp * mcasp)210 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
211 {
212 u32 cnt;
213
214 if (mcasp->txnumevt) { /* enable FIFO */
215 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
216
217 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
218 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
219 }
220
221 /* Start clocks */
222 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
223 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
224 /* Activate serializer(s) */
225 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
226
227 /* wait for XDATA to be cleared */
228 cnt = 0;
229 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
230 (cnt < 100000))
231 cnt++;
232
233 /* Release TX state machine */
234 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
235 /* Release Frame Sync generator */
236 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
237
238 /* enable transmit IRQs */
239 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
240 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
241 }
242
davinci_mcasp_start(struct davinci_mcasp * mcasp,int stream)243 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
244 {
245 mcasp->streams++;
246
247 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
248 mcasp_start_tx(mcasp);
249 else
250 mcasp_start_rx(mcasp);
251 }
252
mcasp_stop_rx(struct davinci_mcasp * mcasp)253 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
254 {
255 /* disable IRQ sources */
256 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
257 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
258
259 /*
260 * In synchronous mode stop the TX clocks if no other stream is
261 * running
262 */
263 if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
264 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
265
266 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
267 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
268
269 if (mcasp->rxnumevt) { /* disable FIFO */
270 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
271
272 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
273 }
274 }
275
mcasp_stop_tx(struct davinci_mcasp * mcasp)276 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
277 {
278 u32 val = 0;
279
280 /* disable IRQ sources */
281 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
282 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
283
284 /*
285 * In synchronous mode keep TX clocks running if the capture stream is
286 * still running.
287 */
288 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
289 val = TXHCLKRST | TXCLKRST | TXFSRST;
290
291 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
292 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
293
294 if (mcasp->txnumevt) { /* disable FIFO */
295 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
296
297 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
298 }
299 }
300
davinci_mcasp_stop(struct davinci_mcasp * mcasp,int stream)301 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
302 {
303 mcasp->streams--;
304
305 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
306 mcasp_stop_tx(mcasp);
307 else
308 mcasp_stop_rx(mcasp);
309 }
310
davinci_mcasp_tx_irq_handler(int irq,void * data)311 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
312 {
313 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
314 struct snd_pcm_substream *substream;
315 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
316 u32 handled_mask = 0;
317 u32 stat;
318
319 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
320 if (stat & XUNDRN & irq_mask) {
321 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
322 handled_mask |= XUNDRN;
323
324 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
325 if (substream) {
326 snd_pcm_stream_lock_irq(substream);
327 if (snd_pcm_running(substream))
328 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
329 snd_pcm_stream_unlock_irq(substream);
330 }
331 }
332
333 if (!handled_mask)
334 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
335 stat);
336
337 if (stat & XRERR)
338 handled_mask |= XRERR;
339
340 /* Ack the handled event only */
341 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
342
343 return IRQ_RETVAL(handled_mask);
344 }
345
davinci_mcasp_rx_irq_handler(int irq,void * data)346 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
347 {
348 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
349 struct snd_pcm_substream *substream;
350 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
351 u32 handled_mask = 0;
352 u32 stat;
353
354 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
355 if (stat & ROVRN & irq_mask) {
356 dev_warn(mcasp->dev, "Receive buffer overflow\n");
357 handled_mask |= ROVRN;
358
359 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
360 if (substream) {
361 snd_pcm_stream_lock_irq(substream);
362 if (snd_pcm_running(substream))
363 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
364 snd_pcm_stream_unlock_irq(substream);
365 }
366 }
367
368 if (!handled_mask)
369 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
370 stat);
371
372 if (stat & XRERR)
373 handled_mask |= XRERR;
374
375 /* Ack the handled event only */
376 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
377
378 return IRQ_RETVAL(handled_mask);
379 }
380
davinci_mcasp_common_irq_handler(int irq,void * data)381 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
382 {
383 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
384 irqreturn_t ret = IRQ_NONE;
385
386 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
387 ret = davinci_mcasp_tx_irq_handler(irq, data);
388
389 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
390 ret |= davinci_mcasp_rx_irq_handler(irq, data);
391
392 return ret;
393 }
394
davinci_mcasp_set_dai_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)395 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
396 unsigned int fmt)
397 {
398 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
399 int ret = 0;
400 u32 data_delay;
401 bool fs_pol_rising;
402 bool inv_fs = false;
403
404 if (!fmt)
405 return 0;
406
407 pm_runtime_get_sync(mcasp->dev);
408 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
409 case SND_SOC_DAIFMT_DSP_A:
410 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
411 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
412 /* 1st data bit occur one ACLK cycle after the frame sync */
413 data_delay = 1;
414 break;
415 case SND_SOC_DAIFMT_DSP_B:
416 case SND_SOC_DAIFMT_AC97:
417 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
418 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
419 /* No delay after FS */
420 data_delay = 0;
421 break;
422 case SND_SOC_DAIFMT_I2S:
423 /* configure a full-word SYNC pulse (LRCLK) */
424 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
425 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
426 /* 1st data bit occur one ACLK cycle after the frame sync */
427 data_delay = 1;
428 /* FS need to be inverted */
429 inv_fs = true;
430 break;
431 case SND_SOC_DAIFMT_LEFT_J:
432 /* configure a full-word SYNC pulse (LRCLK) */
433 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
434 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
435 /* No delay after FS */
436 data_delay = 0;
437 break;
438 default:
439 ret = -EINVAL;
440 goto out;
441 }
442
443 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
444 FSXDLY(3));
445 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
446 FSRDLY(3));
447
448 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
449 case SND_SOC_DAIFMT_CBS_CFS:
450 /* codec is clock and frame slave */
451 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
452 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
453
454 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
455 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
456
457 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
458 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
459 mcasp->bclk_master = 1;
460 break;
461 case SND_SOC_DAIFMT_CBS_CFM:
462 /* codec is clock slave and frame master */
463 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
464 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
465
466 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
467 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
468
469 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
470 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
471 mcasp->bclk_master = 1;
472 break;
473 case SND_SOC_DAIFMT_CBM_CFS:
474 /* codec is clock master and frame slave */
475 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
476 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
477
478 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
479 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
480
481 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
482 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
483 mcasp->bclk_master = 0;
484 break;
485 case SND_SOC_DAIFMT_CBM_CFM:
486 /* codec is clock and frame master */
487 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
488 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
489
490 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
491 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
492
493 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
494 ACLKX | AFSX | ACLKR | AHCLKR | AFSR);
495 mcasp->bclk_master = 0;
496 break;
497 default:
498 ret = -EINVAL;
499 goto out;
500 }
501
502 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
503 case SND_SOC_DAIFMT_IB_NF:
504 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
505 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
506 fs_pol_rising = true;
507 break;
508 case SND_SOC_DAIFMT_NB_IF:
509 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
510 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
511 fs_pol_rising = false;
512 break;
513 case SND_SOC_DAIFMT_IB_IF:
514 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
515 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
516 fs_pol_rising = false;
517 break;
518 case SND_SOC_DAIFMT_NB_NF:
519 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
520 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
521 fs_pol_rising = true;
522 break;
523 default:
524 ret = -EINVAL;
525 goto out;
526 }
527
528 if (inv_fs)
529 fs_pol_rising = !fs_pol_rising;
530
531 if (fs_pol_rising) {
532 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
533 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
534 } else {
535 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
536 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
537 }
538
539 mcasp->dai_fmt = fmt;
540 out:
541 pm_runtime_put(mcasp->dev);
542 return ret;
543 }
544
__davinci_mcasp_set_clkdiv(struct davinci_mcasp * mcasp,int div_id,int div,bool explicit)545 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,
546 int div, bool explicit)
547 {
548 pm_runtime_get_sync(mcasp->dev);
549 switch (div_id) {
550 case MCASP_CLKDIV_AUXCLK: /* MCLK divider */
551 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
552 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
553 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
554 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
555 break;
556
557 case MCASP_CLKDIV_BCLK: /* BCLK divider */
558 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
559 ACLKXDIV(div - 1), ACLKXDIV_MASK);
560 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
561 ACLKRDIV(div - 1), ACLKRDIV_MASK);
562 if (explicit)
563 mcasp->bclk_div = div;
564 break;
565
566 case MCASP_CLKDIV_BCLK_FS_RATIO:
567 /*
568 * BCLK/LRCLK ratio descries how many bit-clock cycles
569 * fit into one frame. The clock ratio is given for a
570 * full period of data (for I2S format both left and
571 * right channels), so it has to be divided by number
572 * of tdm-slots (for I2S - divided by 2).
573 * Instead of storing this ratio, we calculate a new
574 * tdm_slot width by dividing the the ratio by the
575 * number of configured tdm slots.
576 */
577 mcasp->slot_width = div / mcasp->tdm_slots;
578 if (div % mcasp->tdm_slots)
579 dev_warn(mcasp->dev,
580 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
581 __func__, div, mcasp->tdm_slots);
582 break;
583
584 default:
585 return -EINVAL;
586 }
587
588 pm_runtime_put(mcasp->dev);
589 return 0;
590 }
591
davinci_mcasp_set_clkdiv(struct snd_soc_dai * dai,int div_id,int div)592 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
593 int div)
594 {
595 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
596
597 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1);
598 }
599
davinci_mcasp_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)600 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
601 unsigned int freq, int dir)
602 {
603 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
604
605 pm_runtime_get_sync(mcasp->dev);
606 if (dir == SND_SOC_CLOCK_OUT) {
607 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
608 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
609 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
610 } else {
611 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
612 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
613 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
614 }
615
616 mcasp->sysclk_freq = freq;
617
618 pm_runtime_put(mcasp->dev);
619 return 0;
620 }
621
622 /* All serializers must have equal number of channels */
davinci_mcasp_ch_constraint(struct davinci_mcasp * mcasp,int stream,int serializers)623 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
624 int serializers)
625 {
626 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
627 unsigned int *list = (unsigned int *) cl->list;
628 int slots = mcasp->tdm_slots;
629 int i, count = 0;
630
631 if (mcasp->tdm_mask[stream])
632 slots = hweight32(mcasp->tdm_mask[stream]);
633
634 for (i = 1; i <= slots; i++)
635 list[count++] = i;
636
637 for (i = 2; i <= serializers; i++)
638 list[count++] = i*slots;
639
640 cl->count = count;
641
642 return 0;
643 }
644
davinci_mcasp_set_ch_constraints(struct davinci_mcasp * mcasp)645 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
646 {
647 int rx_serializers = 0, tx_serializers = 0, ret, i;
648
649 for (i = 0; i < mcasp->num_serializer; i++)
650 if (mcasp->serial_dir[i] == TX_MODE)
651 tx_serializers++;
652 else if (mcasp->serial_dir[i] == RX_MODE)
653 rx_serializers++;
654
655 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
656 tx_serializers);
657 if (ret)
658 return ret;
659
660 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
661 rx_serializers);
662
663 return ret;
664 }
665
666
davinci_mcasp_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)667 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
668 unsigned int tx_mask,
669 unsigned int rx_mask,
670 int slots, int slot_width)
671 {
672 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
673
674 dev_dbg(mcasp->dev,
675 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",
676 __func__, tx_mask, rx_mask, slots, slot_width);
677
678 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
679 dev_err(mcasp->dev,
680 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
681 tx_mask, rx_mask, slots);
682 return -EINVAL;
683 }
684
685 if (slot_width &&
686 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {
687 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
688 __func__, slot_width);
689 return -EINVAL;
690 }
691
692 mcasp->tdm_slots = slots;
693 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
694 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
695 mcasp->slot_width = slot_width;
696
697 return davinci_mcasp_set_ch_constraints(mcasp);
698 }
699
davinci_config_channel_size(struct davinci_mcasp * mcasp,int sample_width)700 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
701 int sample_width)
702 {
703 u32 fmt;
704 u32 tx_rotate = (sample_width / 4) & 0x7;
705 u32 mask = (1ULL << sample_width) - 1;
706 u32 slot_width = sample_width;
707
708 /*
709 * For captured data we should not rotate, inversion and masking is
710 * enoguh to get the data to the right position:
711 * Format data from bus after reverse (XRBUF)
712 * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB|
713 * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
714 * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
715 * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB|
716 */
717 u32 rx_rotate = 0;
718
719 /*
720 * Setting the tdm slot width either with set_clkdiv() or
721 * set_tdm_slot() allows us to for example send 32 bits per
722 * channel to the codec, while only 16 of them carry audio
723 * payload.
724 */
725 if (mcasp->slot_width) {
726 /*
727 * When we have more bclk then it is needed for the
728 * data, we need to use the rotation to move the
729 * received samples to have correct alignment.
730 */
731 slot_width = mcasp->slot_width;
732 rx_rotate = (slot_width - sample_width) / 4;
733 }
734
735 /* mapping of the XSSZ bit-field as described in the datasheet */
736 fmt = (slot_width >> 1) - 1;
737
738 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
739 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
740 RXSSZ(0x0F));
741 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
742 TXSSZ(0x0F));
743 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
744 TXROT(7));
745 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
746 RXROT(7));
747 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
748 }
749
750 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
751
752 return 0;
753 }
754
mcasp_common_hw_param(struct davinci_mcasp * mcasp,int stream,int period_words,int channels)755 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
756 int period_words, int channels)
757 {
758 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
759 int i;
760 u8 tx_ser = 0;
761 u8 rx_ser = 0;
762 u8 slots = mcasp->tdm_slots;
763 u8 max_active_serializers = (channels + slots - 1) / slots;
764 int active_serializers, numevt;
765 u32 reg;
766 /* Default configuration */
767 if (mcasp->version < MCASP_VERSION_3)
768 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
769
770 /* All PINS as McASP */
771 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
772
773 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
774 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
775 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
776 } else {
777 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
778 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
779 }
780
781 for (i = 0; i < mcasp->num_serializer; i++) {
782 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
783 mcasp->serial_dir[i]);
784 if (mcasp->serial_dir[i] == TX_MODE &&
785 tx_ser < max_active_serializers) {
786 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
787 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
788 DISMOD_LOW, DISMOD_MASK);
789 tx_ser++;
790 } else if (mcasp->serial_dir[i] == RX_MODE &&
791 rx_ser < max_active_serializers) {
792 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
793 rx_ser++;
794 } else {
795 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
796 SRMOD_INACTIVE, SRMOD_MASK);
797 }
798 }
799
800 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
801 active_serializers = tx_ser;
802 numevt = mcasp->txnumevt;
803 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
804 } else {
805 active_serializers = rx_ser;
806 numevt = mcasp->rxnumevt;
807 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
808 }
809
810 if (active_serializers < max_active_serializers) {
811 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
812 "enabled in mcasp (%d)\n", channels,
813 active_serializers * slots);
814 return -EINVAL;
815 }
816
817 /* AFIFO is not in use */
818 if (!numevt) {
819 /* Configure the burst size for platform drivers */
820 if (active_serializers > 1) {
821 /*
822 * If more than one serializers are in use we have one
823 * DMA request to provide data for all serializers.
824 * For example if three serializers are enabled the DMA
825 * need to transfer three words per DMA request.
826 */
827 dma_data->maxburst = active_serializers;
828 } else {
829 dma_data->maxburst = 0;
830 }
831 return 0;
832 }
833
834 if (period_words % active_serializers) {
835 dev_err(mcasp->dev, "Invalid combination of period words and "
836 "active serializers: %d, %d\n", period_words,
837 active_serializers);
838 return -EINVAL;
839 }
840
841 /*
842 * Calculate the optimal AFIFO depth for platform side:
843 * The number of words for numevt need to be in steps of active
844 * serializers.
845 */
846 numevt = (numevt / active_serializers) * active_serializers;
847
848 while (period_words % numevt && numevt > 0)
849 numevt -= active_serializers;
850 if (numevt <= 0)
851 numevt = active_serializers;
852
853 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
854 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
855
856 /* Configure the burst size for platform drivers */
857 if (numevt == 1)
858 numevt = 0;
859 dma_data->maxburst = numevt;
860
861 return 0;
862 }
863
mcasp_i2s_hw_param(struct davinci_mcasp * mcasp,int stream,int channels)864 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
865 int channels)
866 {
867 int i, active_slots;
868 int total_slots;
869 int active_serializers;
870 u32 mask = 0;
871 u32 busel = 0;
872
873 total_slots = mcasp->tdm_slots;
874
875 /*
876 * If more than one serializer is needed, then use them with
877 * all the specified tdm_slots. Otherwise, one serializer can
878 * cope with the transaction using just as many slots as there
879 * are channels in the stream.
880 */
881 if (mcasp->tdm_mask[stream]) {
882 active_slots = hweight32(mcasp->tdm_mask[stream]);
883 active_serializers = (channels + active_slots - 1) /
884 active_slots;
885 if (active_serializers == 1)
886 active_slots = channels;
887 for (i = 0; i < total_slots; i++) {
888 if ((1 << i) & mcasp->tdm_mask[stream]) {
889 mask |= (1 << i);
890 if (--active_slots <= 0)
891 break;
892 }
893 }
894 } else {
895 active_serializers = (channels + total_slots - 1) / total_slots;
896 if (active_serializers == 1)
897 active_slots = channels;
898 else
899 active_slots = total_slots;
900
901 for (i = 0; i < active_slots; i++)
902 mask |= (1 << i);
903 }
904 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
905
906 if (!mcasp->dat_port)
907 busel = TXSEL;
908
909 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
910 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
911 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
912 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
913 FSXMOD(total_slots), FSXMOD(0x1FF));
914 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
915 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
916 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
917 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
918 FSRMOD(total_slots), FSRMOD(0x1FF));
919 /*
920 * If McASP is set to be TX/RX synchronous and the playback is
921 * not running already we need to configure the TX slots in
922 * order to have correct FSX on the bus
923 */
924 if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
925 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
926 FSXMOD(total_slots), FSXMOD(0x1FF));
927 }
928
929 return 0;
930 }
931
932 /* S/PDIF */
mcasp_dit_hw_param(struct davinci_mcasp * mcasp,unsigned int rate)933 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
934 unsigned int rate)
935 {
936 u32 cs_value = 0;
937 u8 *cs_bytes = (u8*) &cs_value;
938
939 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
940 and LSB first */
941 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
942
943 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
944 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
945
946 /* Set the TX tdm : for all the slots */
947 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
948
949 /* Set the TX clock controls : div = 1 and internal */
950 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
951
952 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
953
954 /* Only 44100 and 48000 are valid, both have the same setting */
955 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
956
957 /* Enable the DIT */
958 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
959
960 /* Set S/PDIF channel status bits */
961 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
962 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
963
964 switch (rate) {
965 case 22050:
966 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
967 break;
968 case 24000:
969 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
970 break;
971 case 32000:
972 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
973 break;
974 case 44100:
975 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
976 break;
977 case 48000:
978 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
979 break;
980 case 88200:
981 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
982 break;
983 case 96000:
984 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
985 break;
986 case 176400:
987 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
988 break;
989 case 192000:
990 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
991 break;
992 default:
993 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
994 return -EINVAL;
995 }
996
997 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
998 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
999
1000 return 0;
1001 }
1002
davinci_mcasp_calc_clk_div(struct davinci_mcasp * mcasp,unsigned int bclk_freq,bool set)1003 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
1004 unsigned int bclk_freq, bool set)
1005 {
1006 int error_ppm;
1007 unsigned int sysclk_freq = mcasp->sysclk_freq;
1008 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);
1009 int div = sysclk_freq / bclk_freq;
1010 int rem = sysclk_freq % bclk_freq;
1011 int aux_div = 1;
1012
1013 if (div > (ACLKXDIV_MASK + 1)) {
1014 if (reg & AHCLKXE) {
1015 aux_div = div / (ACLKXDIV_MASK + 1);
1016 if (div % (ACLKXDIV_MASK + 1))
1017 aux_div++;
1018
1019 sysclk_freq /= aux_div;
1020 div = sysclk_freq / bclk_freq;
1021 rem = sysclk_freq % bclk_freq;
1022 } else if (set) {
1023 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n",
1024 sysclk_freq);
1025 }
1026 }
1027
1028 if (rem != 0) {
1029 if (div == 0 ||
1030 ((sysclk_freq / div) - bclk_freq) >
1031 (bclk_freq - (sysclk_freq / (div+1)))) {
1032 div++;
1033 rem = rem - bclk_freq;
1034 }
1035 }
1036 error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem,
1037 (int)bclk_freq)) / div - 1000000;
1038
1039 if (set) {
1040 if (error_ppm)
1041 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
1042 error_ppm);
1043
1044 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0);
1045 if (reg & AHCLKXE)
1046 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK,
1047 aux_div, 0);
1048 }
1049
1050 return error_ppm;
1051 }
1052
davinci_mcasp_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * cpu_dai)1053 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
1054 struct snd_pcm_hw_params *params,
1055 struct snd_soc_dai *cpu_dai)
1056 {
1057 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1058 int word_length;
1059 int channels = params_channels(params);
1060 int period_size = params_period_size(params);
1061 int ret;
1062
1063 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt);
1064 if (ret)
1065 return ret;
1066
1067 /*
1068 * If mcasp is BCLK master, and a BCLK divider was not provided by
1069 * the machine driver, we need to calculate the ratio.
1070 */
1071 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1072 int slots = mcasp->tdm_slots;
1073 int rate = params_rate(params);
1074 int sbits = params_width(params);
1075
1076 if (mcasp->slot_width)
1077 sbits = mcasp->slot_width;
1078
1079 davinci_mcasp_calc_clk_div(mcasp, rate * sbits * slots, true);
1080 }
1081
1082 ret = mcasp_common_hw_param(mcasp, substream->stream,
1083 period_size * channels, channels);
1084 if (ret)
1085 return ret;
1086
1087 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1088 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
1089 else
1090 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
1091 channels);
1092
1093 if (ret)
1094 return ret;
1095
1096 switch (params_format(params)) {
1097 case SNDRV_PCM_FORMAT_U8:
1098 case SNDRV_PCM_FORMAT_S8:
1099 word_length = 8;
1100 break;
1101
1102 case SNDRV_PCM_FORMAT_U16_LE:
1103 case SNDRV_PCM_FORMAT_S16_LE:
1104 word_length = 16;
1105 break;
1106
1107 case SNDRV_PCM_FORMAT_U24_3LE:
1108 case SNDRV_PCM_FORMAT_S24_3LE:
1109 word_length = 24;
1110 break;
1111
1112 case SNDRV_PCM_FORMAT_U24_LE:
1113 case SNDRV_PCM_FORMAT_S24_LE:
1114 word_length = 24;
1115 break;
1116
1117 case SNDRV_PCM_FORMAT_U32_LE:
1118 case SNDRV_PCM_FORMAT_S32_LE:
1119 word_length = 32;
1120 break;
1121
1122 default:
1123 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
1124 return -EINVAL;
1125 }
1126
1127 davinci_config_channel_size(mcasp, word_length);
1128
1129 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
1130 mcasp->channels = channels;
1131
1132 return 0;
1133 }
1134
davinci_mcasp_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * cpu_dai)1135 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
1136 int cmd, struct snd_soc_dai *cpu_dai)
1137 {
1138 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1139 int ret = 0;
1140
1141 switch (cmd) {
1142 case SNDRV_PCM_TRIGGER_RESUME:
1143 case SNDRV_PCM_TRIGGER_START:
1144 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1145 davinci_mcasp_start(mcasp, substream->stream);
1146 break;
1147 case SNDRV_PCM_TRIGGER_SUSPEND:
1148 case SNDRV_PCM_TRIGGER_STOP:
1149 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1150 davinci_mcasp_stop(mcasp, substream->stream);
1151 break;
1152
1153 default:
1154 ret = -EINVAL;
1155 }
1156
1157 return ret;
1158 }
1159
davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)1160 static int davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params *params,
1161 struct snd_pcm_hw_rule *rule)
1162 {
1163 struct davinci_mcasp_ruledata *rd = rule->private;
1164 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1165 struct snd_mask nfmt;
1166 int i, slot_width;
1167
1168 snd_mask_none(&nfmt);
1169 slot_width = rd->mcasp->slot_width;
1170
1171 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1172 if (snd_mask_test(fmt, i)) {
1173 if (snd_pcm_format_width(i) <= slot_width) {
1174 snd_mask_set(&nfmt, i);
1175 }
1176 }
1177 }
1178
1179 return snd_mask_refine(fmt, &nfmt);
1180 }
1181
1182 static const unsigned int davinci_mcasp_dai_rates[] = {
1183 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1184 88200, 96000, 176400, 192000,
1185 };
1186
1187 #define DAVINCI_MAX_RATE_ERROR_PPM 1000
1188
davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)1189 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1190 struct snd_pcm_hw_rule *rule)
1191 {
1192 struct davinci_mcasp_ruledata *rd = rule->private;
1193 struct snd_interval *ri =
1194 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1195 int sbits = params_width(params);
1196 int slots = rd->mcasp->tdm_slots;
1197 struct snd_interval range;
1198 int i;
1199
1200 if (rd->mcasp->slot_width)
1201 sbits = rd->mcasp->slot_width;
1202
1203 snd_interval_any(&range);
1204 range.empty = 1;
1205
1206 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
1207 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
1208 uint bclk_freq = sbits*slots*
1209 davinci_mcasp_dai_rates[i];
1210 int ppm;
1211
1212 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq,
1213 false);
1214 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1215 if (range.empty) {
1216 range.min = davinci_mcasp_dai_rates[i];
1217 range.empty = 0;
1218 }
1219 range.max = davinci_mcasp_dai_rates[i];
1220 }
1221 }
1222 }
1223
1224 dev_dbg(rd->mcasp->dev,
1225 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
1226 ri->min, ri->max, range.min, range.max, sbits, slots);
1227
1228 return snd_interval_refine(hw_param_interval(params, rule->var),
1229 &range);
1230 }
1231
davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)1232 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1233 struct snd_pcm_hw_rule *rule)
1234 {
1235 struct davinci_mcasp_ruledata *rd = rule->private;
1236 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1237 struct snd_mask nfmt;
1238 int rate = params_rate(params);
1239 int slots = rd->mcasp->tdm_slots;
1240 int i, count = 0;
1241
1242 snd_mask_none(&nfmt);
1243
1244 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1245 if (snd_mask_test(fmt, i)) {
1246 uint sbits = snd_pcm_format_width(i);
1247 int ppm;
1248
1249 if (rd->mcasp->slot_width)
1250 sbits = rd->mcasp->slot_width;
1251
1252 ppm = davinci_mcasp_calc_clk_div(rd->mcasp,
1253 sbits * slots * rate,
1254 false);
1255 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1256 snd_mask_set(&nfmt, i);
1257 count++;
1258 }
1259 }
1260 }
1261 dev_dbg(rd->mcasp->dev,
1262 "%d possible sample format for %d Hz and %d tdm slots\n",
1263 count, rate, slots);
1264
1265 return snd_mask_refine(fmt, &nfmt);
1266 }
1267
davinci_mcasp_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)1268 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1269 struct snd_soc_dai *cpu_dai)
1270 {
1271 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1272 struct davinci_mcasp_ruledata *ruledata =
1273 &mcasp->ruledata[substream->stream];
1274 u32 max_channels = 0;
1275 int i, dir, ret;
1276 int tdm_slots = mcasp->tdm_slots;
1277
1278 /* Do not allow more then one stream per direction */
1279 if (mcasp->substreams[substream->stream])
1280 return -EBUSY;
1281
1282 mcasp->substreams[substream->stream] = substream;
1283
1284 if (mcasp->tdm_mask[substream->stream])
1285 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1286
1287 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1288 return 0;
1289
1290 /*
1291 * Limit the maximum allowed channels for the first stream:
1292 * number of serializers for the direction * tdm slots per serializer
1293 */
1294 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1295 dir = TX_MODE;
1296 else
1297 dir = RX_MODE;
1298
1299 for (i = 0; i < mcasp->num_serializer; i++) {
1300 if (mcasp->serial_dir[i] == dir)
1301 max_channels++;
1302 }
1303 ruledata->serializers = max_channels;
1304 ruledata->mcasp = mcasp;
1305 max_channels *= tdm_slots;
1306 /*
1307 * If the already active stream has less channels than the calculated
1308 * limnit based on the seirializers * tdm_slots, we need to use that as
1309 * a constraint for the second stream.
1310 * Otherwise (first stream or less allowed channels) we use the
1311 * calculated constraint.
1312 */
1313 if (mcasp->channels && mcasp->channels < max_channels)
1314 max_channels = mcasp->channels;
1315 /*
1316 * But we can always allow channels upto the amount of
1317 * the available tdm_slots.
1318 */
1319 if (max_channels < tdm_slots)
1320 max_channels = tdm_slots;
1321
1322 snd_pcm_hw_constraint_minmax(substream->runtime,
1323 SNDRV_PCM_HW_PARAM_CHANNELS,
1324 0, max_channels);
1325
1326 snd_pcm_hw_constraint_list(substream->runtime,
1327 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1328 &mcasp->chconstr[substream->stream]);
1329
1330 if (mcasp->slot_width) {
1331 /* Only allow formats require <= slot_width bits on the bus */
1332 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1333 SNDRV_PCM_HW_PARAM_FORMAT,
1334 davinci_mcasp_hw_rule_slot_width,
1335 ruledata,
1336 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1337 if (ret)
1338 return ret;
1339 }
1340
1341 /*
1342 * If we rely on implicit BCLK divider setting we should
1343 * set constraints based on what we can provide.
1344 */
1345 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1346 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1347 SNDRV_PCM_HW_PARAM_RATE,
1348 davinci_mcasp_hw_rule_rate,
1349 ruledata,
1350 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1351 if (ret)
1352 return ret;
1353 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1354 SNDRV_PCM_HW_PARAM_FORMAT,
1355 davinci_mcasp_hw_rule_format,
1356 ruledata,
1357 SNDRV_PCM_HW_PARAM_RATE, -1);
1358 if (ret)
1359 return ret;
1360 }
1361
1362 return 0;
1363 }
1364
davinci_mcasp_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)1365 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1366 struct snd_soc_dai *cpu_dai)
1367 {
1368 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1369
1370 mcasp->substreams[substream->stream] = NULL;
1371
1372 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1373 return;
1374
1375 if (!cpu_dai->active)
1376 mcasp->channels = 0;
1377 }
1378
1379 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
1380 .startup = davinci_mcasp_startup,
1381 .shutdown = davinci_mcasp_shutdown,
1382 .trigger = davinci_mcasp_trigger,
1383 .hw_params = davinci_mcasp_hw_params,
1384 .set_fmt = davinci_mcasp_set_dai_fmt,
1385 .set_clkdiv = davinci_mcasp_set_clkdiv,
1386 .set_sysclk = davinci_mcasp_set_sysclk,
1387 .set_tdm_slot = davinci_mcasp_set_tdm_slot,
1388 };
1389
davinci_mcasp_dai_probe(struct snd_soc_dai * dai)1390 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1391 {
1392 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1393
1394 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1395 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1396
1397 return 0;
1398 }
1399
1400 #ifdef CONFIG_PM_SLEEP
davinci_mcasp_suspend(struct snd_soc_dai * dai)1401 static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
1402 {
1403 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1404 struct davinci_mcasp_context *context = &mcasp->context;
1405 u32 reg;
1406 int i;
1407
1408 context->pm_state = pm_runtime_active(mcasp->dev);
1409 if (!context->pm_state)
1410 pm_runtime_get_sync(mcasp->dev);
1411
1412 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1413 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
1414
1415 if (mcasp->txnumevt) {
1416 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1417 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
1418 }
1419 if (mcasp->rxnumevt) {
1420 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1421 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
1422 }
1423
1424 for (i = 0; i < mcasp->num_serializer; i++)
1425 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
1426 DAVINCI_MCASP_XRSRCTL_REG(i));
1427
1428 pm_runtime_put_sync(mcasp->dev);
1429
1430 return 0;
1431 }
1432
davinci_mcasp_resume(struct snd_soc_dai * dai)1433 static int davinci_mcasp_resume(struct snd_soc_dai *dai)
1434 {
1435 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1436 struct davinci_mcasp_context *context = &mcasp->context;
1437 u32 reg;
1438 int i;
1439
1440 pm_runtime_get_sync(mcasp->dev);
1441
1442 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1443 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
1444
1445 if (mcasp->txnumevt) {
1446 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1447 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
1448 }
1449 if (mcasp->rxnumevt) {
1450 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1451 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
1452 }
1453
1454 for (i = 0; i < mcasp->num_serializer; i++)
1455 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
1456 context->xrsr_regs[i]);
1457
1458 if (!context->pm_state)
1459 pm_runtime_put_sync(mcasp->dev);
1460
1461 return 0;
1462 }
1463 #else
1464 #define davinci_mcasp_suspend NULL
1465 #define davinci_mcasp_resume NULL
1466 #endif
1467
1468 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
1469
1470 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1471 SNDRV_PCM_FMTBIT_U8 | \
1472 SNDRV_PCM_FMTBIT_S16_LE | \
1473 SNDRV_PCM_FMTBIT_U16_LE | \
1474 SNDRV_PCM_FMTBIT_S24_LE | \
1475 SNDRV_PCM_FMTBIT_U24_LE | \
1476 SNDRV_PCM_FMTBIT_S24_3LE | \
1477 SNDRV_PCM_FMTBIT_U24_3LE | \
1478 SNDRV_PCM_FMTBIT_S32_LE | \
1479 SNDRV_PCM_FMTBIT_U32_LE)
1480
1481 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
1482 {
1483 .name = "davinci-mcasp.0",
1484 .probe = davinci_mcasp_dai_probe,
1485 .suspend = davinci_mcasp_suspend,
1486 .resume = davinci_mcasp_resume,
1487 .playback = {
1488 .channels_min = 1,
1489 .channels_max = 32 * 16,
1490 .rates = DAVINCI_MCASP_RATES,
1491 .formats = DAVINCI_MCASP_PCM_FMTS,
1492 },
1493 .capture = {
1494 .channels_min = 1,
1495 .channels_max = 32 * 16,
1496 .rates = DAVINCI_MCASP_RATES,
1497 .formats = DAVINCI_MCASP_PCM_FMTS,
1498 },
1499 .ops = &davinci_mcasp_dai_ops,
1500
1501 .symmetric_samplebits = 1,
1502 .symmetric_rates = 1,
1503 },
1504 {
1505 .name = "davinci-mcasp.1",
1506 .probe = davinci_mcasp_dai_probe,
1507 .playback = {
1508 .channels_min = 1,
1509 .channels_max = 384,
1510 .rates = DAVINCI_MCASP_RATES,
1511 .formats = DAVINCI_MCASP_PCM_FMTS,
1512 },
1513 .ops = &davinci_mcasp_dai_ops,
1514 },
1515
1516 };
1517
1518 static const struct snd_soc_component_driver davinci_mcasp_component = {
1519 .name = "davinci-mcasp",
1520 };
1521
1522 /* Some HW specific values and defaults. The rest is filled in from DT. */
1523 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
1524 .tx_dma_offset = 0x400,
1525 .rx_dma_offset = 0x400,
1526 .version = MCASP_VERSION_1,
1527 };
1528
1529 static struct davinci_mcasp_pdata da830_mcasp_pdata = {
1530 .tx_dma_offset = 0x2000,
1531 .rx_dma_offset = 0x2000,
1532 .version = MCASP_VERSION_2,
1533 };
1534
1535 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
1536 .tx_dma_offset = 0,
1537 .rx_dma_offset = 0,
1538 .version = MCASP_VERSION_3,
1539 };
1540
1541 static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
1542 /* The CFG port offset will be calculated if it is needed */
1543 .tx_dma_offset = 0,
1544 .rx_dma_offset = 0,
1545 .version = MCASP_VERSION_4,
1546 };
1547
1548 static const struct of_device_id mcasp_dt_ids[] = {
1549 {
1550 .compatible = "ti,dm646x-mcasp-audio",
1551 .data = &dm646x_mcasp_pdata,
1552 },
1553 {
1554 .compatible = "ti,da830-mcasp-audio",
1555 .data = &da830_mcasp_pdata,
1556 },
1557 {
1558 .compatible = "ti,am33xx-mcasp-audio",
1559 .data = &am33xx_mcasp_pdata,
1560 },
1561 {
1562 .compatible = "ti,dra7-mcasp-audio",
1563 .data = &dra7_mcasp_pdata,
1564 },
1565 { /* sentinel */ }
1566 };
1567 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1568
mcasp_reparent_fck(struct platform_device * pdev)1569 static int mcasp_reparent_fck(struct platform_device *pdev)
1570 {
1571 struct device_node *node = pdev->dev.of_node;
1572 struct clk *gfclk, *parent_clk;
1573 const char *parent_name;
1574 int ret;
1575
1576 if (!node)
1577 return 0;
1578
1579 parent_name = of_get_property(node, "fck_parent", NULL);
1580 if (!parent_name)
1581 return 0;
1582
1583 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n");
1584
1585 gfclk = clk_get(&pdev->dev, "fck");
1586 if (IS_ERR(gfclk)) {
1587 dev_err(&pdev->dev, "failed to get fck\n");
1588 return PTR_ERR(gfclk);
1589 }
1590
1591 parent_clk = clk_get(NULL, parent_name);
1592 if (IS_ERR(parent_clk)) {
1593 dev_err(&pdev->dev, "failed to get parent clock\n");
1594 ret = PTR_ERR(parent_clk);
1595 goto err1;
1596 }
1597
1598 ret = clk_set_parent(gfclk, parent_clk);
1599 if (ret) {
1600 dev_err(&pdev->dev, "failed to reparent fck\n");
1601 goto err2;
1602 }
1603
1604 err2:
1605 clk_put(parent_clk);
1606 err1:
1607 clk_put(gfclk);
1608 return ret;
1609 }
1610
davinci_mcasp_set_pdata_from_of(struct platform_device * pdev)1611 static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
1612 struct platform_device *pdev)
1613 {
1614 struct device_node *np = pdev->dev.of_node;
1615 struct davinci_mcasp_pdata *pdata = NULL;
1616 const struct of_device_id *match =
1617 of_match_device(mcasp_dt_ids, &pdev->dev);
1618 struct of_phandle_args dma_spec;
1619
1620 const u32 *of_serial_dir32;
1621 u32 val;
1622 int i, ret = 0;
1623
1624 if (pdev->dev.platform_data) {
1625 pdata = pdev->dev.platform_data;
1626 return pdata;
1627 } else if (match) {
1628 pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata),
1629 GFP_KERNEL);
1630 if (!pdata) {
1631 ret = -ENOMEM;
1632 return pdata;
1633 }
1634 } else {
1635 /* control shouldn't reach here. something is wrong */
1636 ret = -EINVAL;
1637 goto nodata;
1638 }
1639
1640 ret = of_property_read_u32(np, "op-mode", &val);
1641 if (ret >= 0)
1642 pdata->op_mode = val;
1643
1644 ret = of_property_read_u32(np, "tdm-slots", &val);
1645 if (ret >= 0) {
1646 if (val < 2 || val > 32) {
1647 dev_err(&pdev->dev,
1648 "tdm-slots must be in rage [2-32]\n");
1649 ret = -EINVAL;
1650 goto nodata;
1651 }
1652
1653 pdata->tdm_slots = val;
1654 }
1655
1656 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1657 val /= sizeof(u32);
1658 if (of_serial_dir32) {
1659 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1660 (sizeof(*of_serial_dir) * val),
1661 GFP_KERNEL);
1662 if (!of_serial_dir) {
1663 ret = -ENOMEM;
1664 goto nodata;
1665 }
1666
1667 for (i = 0; i < val; i++)
1668 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1669
1670 pdata->num_serializer = val;
1671 pdata->serial_dir = of_serial_dir;
1672 }
1673
1674 ret = of_property_match_string(np, "dma-names", "tx");
1675 if (ret < 0)
1676 goto nodata;
1677
1678 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1679 &dma_spec);
1680 if (ret < 0)
1681 goto nodata;
1682
1683 pdata->tx_dma_channel = dma_spec.args[0];
1684
1685 /* RX is not valid in DIT mode */
1686 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
1687 ret = of_property_match_string(np, "dma-names", "rx");
1688 if (ret < 0)
1689 goto nodata;
1690
1691 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1692 &dma_spec);
1693 if (ret < 0)
1694 goto nodata;
1695
1696 pdata->rx_dma_channel = dma_spec.args[0];
1697 }
1698
1699 ret = of_property_read_u32(np, "tx-num-evt", &val);
1700 if (ret >= 0)
1701 pdata->txnumevt = val;
1702
1703 ret = of_property_read_u32(np, "rx-num-evt", &val);
1704 if (ret >= 0)
1705 pdata->rxnumevt = val;
1706
1707 ret = of_property_read_u32(np, "sram-size-playback", &val);
1708 if (ret >= 0)
1709 pdata->sram_size_playback = val;
1710
1711 ret = of_property_read_u32(np, "sram-size-capture", &val);
1712 if (ret >= 0)
1713 pdata->sram_size_capture = val;
1714
1715 return pdata;
1716
1717 nodata:
1718 if (ret < 0) {
1719 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1720 ret);
1721 pdata = NULL;
1722 }
1723 return pdata;
1724 }
1725
1726 enum {
1727 PCM_EDMA,
1728 PCM_SDMA,
1729 };
1730 static const char *sdma_prefix = "ti,omap";
1731
davinci_mcasp_get_dma_type(struct davinci_mcasp * mcasp)1732 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
1733 {
1734 struct dma_chan *chan;
1735 const char *tmp;
1736 int ret = PCM_EDMA;
1737
1738 if (!mcasp->dev->of_node)
1739 return PCM_EDMA;
1740
1741 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
1742 chan = dma_request_slave_channel_reason(mcasp->dev, tmp);
1743 if (IS_ERR(chan)) {
1744 if (PTR_ERR(chan) != -EPROBE_DEFER)
1745 dev_err(mcasp->dev,
1746 "Can't verify DMA configuration (%ld)\n",
1747 PTR_ERR(chan));
1748 return PTR_ERR(chan);
1749 }
1750 if (WARN_ON(!chan->device || !chan->device->dev))
1751 return -EINVAL;
1752
1753 if (chan->device->dev->of_node)
1754 ret = of_property_read_string(chan->device->dev->of_node,
1755 "compatible", &tmp);
1756 else
1757 dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
1758
1759 dma_release_channel(chan);
1760 if (ret)
1761 return ret;
1762
1763 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
1764 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))
1765 return PCM_SDMA;
1766
1767 return PCM_EDMA;
1768 }
1769
davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata * pdata)1770 static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata)
1771 {
1772 int i;
1773 u32 offset = 0;
1774
1775 if (pdata->version != MCASP_VERSION_4)
1776 return pdata->tx_dma_offset;
1777
1778 for (i = 0; i < pdata->num_serializer; i++) {
1779 if (pdata->serial_dir[i] == TX_MODE) {
1780 if (!offset) {
1781 offset = DAVINCI_MCASP_TXBUF_REG(i);
1782 } else {
1783 pr_err("%s: Only one serializer allowed!\n",
1784 __func__);
1785 break;
1786 }
1787 }
1788 }
1789
1790 return offset;
1791 }
1792
davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata * pdata)1793 static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata)
1794 {
1795 int i;
1796 u32 offset = 0;
1797
1798 if (pdata->version != MCASP_VERSION_4)
1799 return pdata->rx_dma_offset;
1800
1801 for (i = 0; i < pdata->num_serializer; i++) {
1802 if (pdata->serial_dir[i] == RX_MODE) {
1803 if (!offset) {
1804 offset = DAVINCI_MCASP_RXBUF_REG(i);
1805 } else {
1806 pr_err("%s: Only one serializer allowed!\n",
1807 __func__);
1808 break;
1809 }
1810 }
1811 }
1812
1813 return offset;
1814 }
1815
davinci_mcasp_probe(struct platform_device * pdev)1816 static int davinci_mcasp_probe(struct platform_device *pdev)
1817 {
1818 struct snd_dmaengine_dai_dma_data *dma_data;
1819 struct resource *mem, *res, *dat;
1820 struct davinci_mcasp_pdata *pdata;
1821 struct davinci_mcasp *mcasp;
1822 char *irq_name;
1823 int *dma;
1824 int irq;
1825 int ret;
1826
1827 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1828 dev_err(&pdev->dev, "No platform data supplied\n");
1829 return -EINVAL;
1830 }
1831
1832 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
1833 GFP_KERNEL);
1834 if (!mcasp)
1835 return -ENOMEM;
1836
1837 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1838 if (!pdata) {
1839 dev_err(&pdev->dev, "no platform data\n");
1840 return -EINVAL;
1841 }
1842
1843 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1844 if (!mem) {
1845 dev_warn(mcasp->dev,
1846 "\"mpu\" mem resource not found, using index 0\n");
1847 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1848 if (!mem) {
1849 dev_err(&pdev->dev, "no mem resource?\n");
1850 return -ENODEV;
1851 }
1852 }
1853
1854 mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
1855 if (IS_ERR(mcasp->base))
1856 return PTR_ERR(mcasp->base);
1857
1858 pm_runtime_enable(&pdev->dev);
1859
1860 mcasp->op_mode = pdata->op_mode;
1861 /* sanity check for tdm slots parameter */
1862 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1863 if (pdata->tdm_slots < 2) {
1864 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1865 pdata->tdm_slots);
1866 mcasp->tdm_slots = 2;
1867 } else if (pdata->tdm_slots > 32) {
1868 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1869 pdata->tdm_slots);
1870 mcasp->tdm_slots = 32;
1871 } else {
1872 mcasp->tdm_slots = pdata->tdm_slots;
1873 }
1874 }
1875
1876 mcasp->num_serializer = pdata->num_serializer;
1877 #ifdef CONFIG_PM_SLEEP
1878 mcasp->context.xrsr_regs = devm_kzalloc(&pdev->dev,
1879 sizeof(u32) * mcasp->num_serializer,
1880 GFP_KERNEL);
1881 if (!mcasp->context.xrsr_regs) {
1882 ret = -ENOMEM;
1883 goto err;
1884 }
1885 #endif
1886 mcasp->serial_dir = pdata->serial_dir;
1887 mcasp->version = pdata->version;
1888 mcasp->txnumevt = pdata->txnumevt;
1889 mcasp->rxnumevt = pdata->rxnumevt;
1890
1891 mcasp->dev = &pdev->dev;
1892
1893 irq = platform_get_irq_byname(pdev, "common");
1894 if (irq >= 0) {
1895 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",
1896 dev_name(&pdev->dev));
1897 if (!irq_name) {
1898 ret = -ENOMEM;
1899 goto err;
1900 }
1901 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1902 davinci_mcasp_common_irq_handler,
1903 IRQF_ONESHOT | IRQF_SHARED,
1904 irq_name, mcasp);
1905 if (ret) {
1906 dev_err(&pdev->dev, "common IRQ request failed\n");
1907 goto err;
1908 }
1909
1910 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1911 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1912 }
1913
1914 irq = platform_get_irq_byname(pdev, "rx");
1915 if (irq >= 0) {
1916 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",
1917 dev_name(&pdev->dev));
1918 if (!irq_name) {
1919 ret = -ENOMEM;
1920 goto err;
1921 }
1922 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1923 davinci_mcasp_rx_irq_handler,
1924 IRQF_ONESHOT, irq_name, mcasp);
1925 if (ret) {
1926 dev_err(&pdev->dev, "RX IRQ request failed\n");
1927 goto err;
1928 }
1929
1930 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1931 }
1932
1933 irq = platform_get_irq_byname(pdev, "tx");
1934 if (irq >= 0) {
1935 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",
1936 dev_name(&pdev->dev));
1937 if (!irq_name) {
1938 ret = -ENOMEM;
1939 goto err;
1940 }
1941 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1942 davinci_mcasp_tx_irq_handler,
1943 IRQF_ONESHOT, irq_name, mcasp);
1944 if (ret) {
1945 dev_err(&pdev->dev, "TX IRQ request failed\n");
1946 goto err;
1947 }
1948
1949 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1950 }
1951
1952 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
1953 if (dat)
1954 mcasp->dat_port = true;
1955
1956 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1957 if (dat)
1958 dma_data->addr = dat->start;
1959 else
1960 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata);
1961
1962 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
1963 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1964 if (res)
1965 *dma = res->start;
1966 else
1967 *dma = pdata->tx_dma_channel;
1968
1969 /* dmaengine filter data for DT and non-DT boot */
1970 if (pdev->dev.of_node)
1971 dma_data->filter_data = "tx";
1972 else
1973 dma_data->filter_data = dma;
1974
1975 /* RX is not valid in DIT mode */
1976 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
1977 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1978 if (dat)
1979 dma_data->addr = dat->start;
1980 else
1981 dma_data->addr =
1982 mem->start + davinci_mcasp_rxdma_offset(pdata);
1983
1984 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
1985 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1986 if (res)
1987 *dma = res->start;
1988 else
1989 *dma = pdata->rx_dma_channel;
1990
1991 /* dmaengine filter data for DT and non-DT boot */
1992 if (pdev->dev.of_node)
1993 dma_data->filter_data = "rx";
1994 else
1995 dma_data->filter_data = dma;
1996 }
1997
1998 if (mcasp->version < MCASP_VERSION_3) {
1999 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
2000 /* dma_params->dma_addr is pointing to the data port address */
2001 mcasp->dat_port = true;
2002 } else {
2003 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
2004 }
2005
2006 /* Allocate memory for long enough list for all possible
2007 * scenarios. Maximum number tdm slots is 32 and there cannot
2008 * be more serializers than given in the configuration. The
2009 * serializer directions could be taken into account, but it
2010 * would make code much more complex and save only couple of
2011 * bytes.
2012 */
2013 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
2014 devm_kzalloc(mcasp->dev, sizeof(unsigned int) *
2015 (32 + mcasp->num_serializer - 1),
2016 GFP_KERNEL);
2017
2018 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
2019 devm_kzalloc(mcasp->dev, sizeof(unsigned int) *
2020 (32 + mcasp->num_serializer - 1),
2021 GFP_KERNEL);
2022
2023 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
2024 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) {
2025 ret = -ENOMEM;
2026 goto err;
2027 }
2028
2029 ret = davinci_mcasp_set_ch_constraints(mcasp);
2030 if (ret)
2031 goto err;
2032
2033 dev_set_drvdata(&pdev->dev, mcasp);
2034
2035 mcasp_reparent_fck(pdev);
2036
2037 ret = devm_snd_soc_register_component(&pdev->dev,
2038 &davinci_mcasp_component,
2039 &davinci_mcasp_dai[pdata->op_mode], 1);
2040
2041 if (ret != 0)
2042 goto err;
2043
2044 ret = davinci_mcasp_get_dma_type(mcasp);
2045 switch (ret) {
2046 case PCM_EDMA:
2047 #if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \
2048 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
2049 IS_MODULE(CONFIG_SND_EDMA_SOC))
2050 ret = edma_pcm_platform_register(&pdev->dev);
2051 #else
2052 dev_err(&pdev->dev, "Missing SND_EDMA_SOC\n");
2053 ret = -EINVAL;
2054 goto err;
2055 #endif
2056 break;
2057 case PCM_SDMA:
2058 #if IS_BUILTIN(CONFIG_SND_OMAP_SOC) || \
2059 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
2060 IS_MODULE(CONFIG_SND_OMAP_SOC))
2061 ret = omap_pcm_platform_register(&pdev->dev);
2062 #else
2063 dev_err(&pdev->dev, "Missing SND_SDMA_SOC\n");
2064 ret = -EINVAL;
2065 goto err;
2066 #endif
2067 break;
2068 default:
2069 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);
2070 case -EPROBE_DEFER:
2071 goto err;
2072 break;
2073 }
2074
2075 if (ret) {
2076 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
2077 goto err;
2078 }
2079
2080 return 0;
2081
2082 err:
2083 pm_runtime_disable(&pdev->dev);
2084 return ret;
2085 }
2086
davinci_mcasp_remove(struct platform_device * pdev)2087 static int davinci_mcasp_remove(struct platform_device *pdev)
2088 {
2089 pm_runtime_disable(&pdev->dev);
2090
2091 return 0;
2092 }
2093
2094 static struct platform_driver davinci_mcasp_driver = {
2095 .probe = davinci_mcasp_probe,
2096 .remove = davinci_mcasp_remove,
2097 .driver = {
2098 .name = "davinci-mcasp",
2099 .of_match_table = mcasp_dt_ids,
2100 },
2101 };
2102
2103 module_platform_driver(davinci_mcasp_driver);
2104
2105 MODULE_AUTHOR("Steve Chen");
2106 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
2107 MODULE_LICENSE("GPL");
2108