1 /*
2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
3 *
4 * Author: Timur Tabi <timur@freescale.com>
5 *
6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 *
12 *
13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
14 *
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developed with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
25 * rate.
26 * Reading and writing AC97 registers is another challenge. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
31 */
32
33 #include <linux/init.h>
34 #include <linux/io.h>
35 #include <linux/module.h>
36 #include <linux/interrupt.h>
37 #include <linux/clk.h>
38 #include <linux/ctype.h>
39 #include <linux/device.h>
40 #include <linux/delay.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/of.h>
44 #include <linux/of_address.h>
45 #include <linux/of_irq.h>
46 #include <linux/of_platform.h>
47
48 #include <sound/core.h>
49 #include <sound/pcm.h>
50 #include <sound/pcm_params.h>
51 #include <sound/initval.h>
52 #include <sound/soc.h>
53 #include <sound/dmaengine_pcm.h>
54
55 #include "fsl_ssi.h"
56 #include "imx-pcm.h"
57
58 /**
59 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
60 *
61 * The SSI has a limitation in that the samples must be in the same byte
62 * order as the host CPU. This is because when multiple bytes are written
63 * to the STX register, the bytes and bits must be written in the same
64 * order. The STX is a shift register, so all the bits need to be aligned
65 * (bit-endianness must match byte-endianness). Processors typically write
66 * the bits within a byte in the same order that the bytes of a word are
67 * written in. So if the host CPU is big-endian, then only big-endian
68 * samples will be written to STX properly.
69 */
70 #ifdef __BIG_ENDIAN
71 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
72 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
73 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
74 #else
75 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
76 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
77 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
78 #endif
79
80 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \
81 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \
82 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN)
83 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
84 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
85 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
86
87 enum fsl_ssi_type {
88 FSL_SSI_MCP8610,
89 FSL_SSI_MX21,
90 FSL_SSI_MX35,
91 FSL_SSI_MX51,
92 };
93
94 struct fsl_ssi_reg_val {
95 u32 sier;
96 u32 srcr;
97 u32 stcr;
98 u32 scr;
99 };
100
101 struct fsl_ssi_rxtx_reg_val {
102 struct fsl_ssi_reg_val rx;
103 struct fsl_ssi_reg_val tx;
104 };
105
fsl_ssi_readable_reg(struct device * dev,unsigned int reg)106 static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg)
107 {
108 switch (reg) {
109 case CCSR_SSI_SACCEN:
110 case CCSR_SSI_SACCDIS:
111 return false;
112 default:
113 return true;
114 }
115 }
116
fsl_ssi_volatile_reg(struct device * dev,unsigned int reg)117 static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg)
118 {
119 switch (reg) {
120 case CCSR_SSI_STX0:
121 case CCSR_SSI_STX1:
122 case CCSR_SSI_SRX0:
123 case CCSR_SSI_SRX1:
124 case CCSR_SSI_SISR:
125 case CCSR_SSI_SFCSR:
126 case CCSR_SSI_SACNT:
127 case CCSR_SSI_SACADD:
128 case CCSR_SSI_SACDAT:
129 case CCSR_SSI_SATAG:
130 case CCSR_SSI_SACCST:
131 case CCSR_SSI_SOR:
132 return true;
133 default:
134 return false;
135 }
136 }
137
fsl_ssi_precious_reg(struct device * dev,unsigned int reg)138 static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg)
139 {
140 switch (reg) {
141 case CCSR_SSI_SRX0:
142 case CCSR_SSI_SRX1:
143 case CCSR_SSI_SISR:
144 case CCSR_SSI_SACADD:
145 case CCSR_SSI_SACDAT:
146 case CCSR_SSI_SATAG:
147 return true;
148 default:
149 return false;
150 }
151 }
152
fsl_ssi_writeable_reg(struct device * dev,unsigned int reg)153 static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg)
154 {
155 switch (reg) {
156 case CCSR_SSI_SRX0:
157 case CCSR_SSI_SRX1:
158 case CCSR_SSI_SACCST:
159 return false;
160 default:
161 return true;
162 }
163 }
164
165 static const struct regmap_config fsl_ssi_regconfig = {
166 .max_register = CCSR_SSI_SACCDIS,
167 .reg_bits = 32,
168 .val_bits = 32,
169 .reg_stride = 4,
170 .val_format_endian = REGMAP_ENDIAN_NATIVE,
171 .num_reg_defaults_raw = CCSR_SSI_SACCDIS / sizeof(uint32_t) + 1,
172 .readable_reg = fsl_ssi_readable_reg,
173 .volatile_reg = fsl_ssi_volatile_reg,
174 .precious_reg = fsl_ssi_precious_reg,
175 .writeable_reg = fsl_ssi_writeable_reg,
176 .cache_type = REGCACHE_FLAT,
177 };
178
179 struct fsl_ssi_soc_data {
180 bool imx;
181 bool imx21regs; /* imx21-class SSI - no SACC{ST,EN,DIS} regs */
182 bool offline_config;
183 u32 sisr_write_mask;
184 };
185
186 /**
187 * fsl_ssi_private: per-SSI private data
188 *
189 * @reg: Pointer to the regmap registers
190 * @irq: IRQ of this SSI
191 * @cpu_dai_drv: CPU DAI driver for this device
192 *
193 * @dai_fmt: DAI configuration this device is currently used with
194 * @i2s_mode: i2s and network mode configuration of the device. Is used to
195 * switch between normal and i2s/network mode
196 * mode depending on the number of channels
197 * @use_dma: DMA is used or FIQ with stream filter
198 * @use_dual_fifo: DMA with support for both FIFOs used
199 * @fifo_deph: Depth of the SSI FIFOs
200 * @rxtx_reg_val: Specific register settings for receive/transmit configuration
201 *
202 * @clk: SSI clock
203 * @baudclk: SSI baud clock for master mode
204 * @baudclk_streams: Active streams that are using baudclk
205 * @bitclk_freq: bitclock frequency set by .set_dai_sysclk
206 *
207 * @dma_params_tx: DMA transmit parameters
208 * @dma_params_rx: DMA receive parameters
209 * @ssi_phys: physical address of the SSI registers
210 *
211 * @fiq_params: FIQ stream filtering parameters
212 *
213 * @pdev: Pointer to pdev used for deprecated fsl-ssi sound card
214 *
215 * @dbg_stats: Debugging statistics
216 *
217 * @soc: SoC specific data
218 *
219 * @fifo_watermark: the FIFO watermark setting. Notifies DMA when
220 * there are @fifo_watermark or fewer words in TX fifo or
221 * @fifo_watermark or more empty words in RX fifo.
222 * @dma_maxburst: max number of words to transfer in one go. So far,
223 * this is always the same as fifo_watermark.
224 */
225 struct fsl_ssi_private {
226 struct regmap *regs;
227 int irq;
228 struct snd_soc_dai_driver cpu_dai_drv;
229
230 unsigned int dai_fmt;
231 u8 i2s_mode;
232 bool use_dma;
233 bool use_dual_fifo;
234 bool has_ipg_clk_name;
235 unsigned int fifo_depth;
236 struct fsl_ssi_rxtx_reg_val rxtx_reg_val;
237
238 struct clk *clk;
239 struct clk *baudclk;
240 unsigned int baudclk_streams;
241 unsigned int bitclk_freq;
242
243 /* regcache for volatile regs */
244 u32 regcache_sfcsr;
245 u32 regcache_sacnt;
246
247 /* DMA params */
248 struct snd_dmaengine_dai_dma_data dma_params_tx;
249 struct snd_dmaengine_dai_dma_data dma_params_rx;
250 dma_addr_t ssi_phys;
251
252 /* params for non-dma FIQ stream filtered mode */
253 struct imx_pcm_fiq_params fiq_params;
254
255 /* Used when using fsl-ssi as sound-card. This is only used by ppc and
256 * should be replaced with simple-sound-card. */
257 struct platform_device *pdev;
258
259 struct fsl_ssi_dbg dbg_stats;
260
261 const struct fsl_ssi_soc_data *soc;
262 struct device *dev;
263
264 u32 fifo_watermark;
265 u32 dma_maxburst;
266 };
267
268 /*
269 * imx51 and later SoCs have a slightly different IP that allows the
270 * SSI configuration while the SSI unit is running.
271 *
272 * More important, it is necessary on those SoCs to configure the
273 * sperate TX/RX DMA bits just before starting the stream
274 * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
275 * sends any DMA requests to the SDMA unit, otherwise it is not defined
276 * how the SDMA unit handles the DMA request.
277 *
278 * SDMA units are present on devices starting at imx35 but the imx35
279 * reference manual states that the DMA bits should not be changed
280 * while the SSI unit is running (SSIEN). So we support the necessary
281 * online configuration of fsl-ssi starting at imx51.
282 */
283
284 static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
285 .imx = false,
286 .offline_config = true,
287 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
288 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
289 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
290 };
291
292 static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
293 .imx = true,
294 .imx21regs = true,
295 .offline_config = true,
296 .sisr_write_mask = 0,
297 };
298
299 static struct fsl_ssi_soc_data fsl_ssi_imx35 = {
300 .imx = true,
301 .offline_config = true,
302 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
303 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
304 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
305 };
306
307 static struct fsl_ssi_soc_data fsl_ssi_imx51 = {
308 .imx = true,
309 .offline_config = false,
310 .sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
311 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
312 };
313
314 static const struct of_device_id fsl_ssi_ids[] = {
315 { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 },
316 { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 },
317 { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 },
318 { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 },
319 {}
320 };
321 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
322
fsl_ssi_is_ac97(struct fsl_ssi_private * ssi_private)323 static bool fsl_ssi_is_ac97(struct fsl_ssi_private *ssi_private)
324 {
325 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
326 SND_SOC_DAIFMT_AC97;
327 }
328
fsl_ssi_is_i2s_master(struct fsl_ssi_private * ssi_private)329 static bool fsl_ssi_is_i2s_master(struct fsl_ssi_private *ssi_private)
330 {
331 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
332 SND_SOC_DAIFMT_CBS_CFS;
333 }
334
fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi_private * ssi_private)335 static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi_private *ssi_private)
336 {
337 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
338 SND_SOC_DAIFMT_CBM_CFS;
339 }
340 /**
341 * fsl_ssi_isr: SSI interrupt handler
342 *
343 * Although it's possible to use the interrupt handler to send and receive
344 * data to/from the SSI, we use the DMA instead. Programming is more
345 * complicated, but the performance is much better.
346 *
347 * This interrupt handler is used only to gather statistics.
348 *
349 * @irq: IRQ of the SSI device
350 * @dev_id: pointer to the ssi_private structure for this SSI device
351 */
fsl_ssi_isr(int irq,void * dev_id)352 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
353 {
354 struct fsl_ssi_private *ssi_private = dev_id;
355 struct regmap *regs = ssi_private->regs;
356 __be32 sisr;
357 __be32 sisr2;
358
359 /* We got an interrupt, so read the status register to see what we
360 were interrupted for. We mask it with the Interrupt Enable register
361 so that we only check for events that we're interested in.
362 */
363 regmap_read(regs, CCSR_SSI_SISR, &sisr);
364
365 sisr2 = sisr & ssi_private->soc->sisr_write_mask;
366 /* Clear the bits that we set */
367 if (sisr2)
368 regmap_write(regs, CCSR_SSI_SISR, sisr2);
369
370 fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr);
371
372 return IRQ_HANDLED;
373 }
374
375 /*
376 * Enable/Disable all rx/tx config flags at once.
377 */
fsl_ssi_rxtx_config(struct fsl_ssi_private * ssi_private,bool enable)378 static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private,
379 bool enable)
380 {
381 struct regmap *regs = ssi_private->regs;
382 struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val;
383
384 if (enable) {
385 regmap_update_bits(regs, CCSR_SSI_SIER,
386 vals->rx.sier | vals->tx.sier,
387 vals->rx.sier | vals->tx.sier);
388 regmap_update_bits(regs, CCSR_SSI_SRCR,
389 vals->rx.srcr | vals->tx.srcr,
390 vals->rx.srcr | vals->tx.srcr);
391 regmap_update_bits(regs, CCSR_SSI_STCR,
392 vals->rx.stcr | vals->tx.stcr,
393 vals->rx.stcr | vals->tx.stcr);
394 } else {
395 regmap_update_bits(regs, CCSR_SSI_SRCR,
396 vals->rx.srcr | vals->tx.srcr, 0);
397 regmap_update_bits(regs, CCSR_SSI_STCR,
398 vals->rx.stcr | vals->tx.stcr, 0);
399 regmap_update_bits(regs, CCSR_SSI_SIER,
400 vals->rx.sier | vals->tx.sier, 0);
401 }
402 }
403
404 /*
405 * Clear RX or TX FIFO to remove samples from the previous
406 * stream session which may be still present in the FIFO and
407 * may introduce bad samples and/or channel slipping.
408 *
409 * Note: The SOR is not documented in recent IMX datasheet, but
410 * is described in IMX51 reference manual at section 56.3.3.15.
411 */
fsl_ssi_fifo_clear(struct fsl_ssi_private * ssi_private,bool is_rx)412 static void fsl_ssi_fifo_clear(struct fsl_ssi_private *ssi_private,
413 bool is_rx)
414 {
415 if (is_rx) {
416 regmap_update_bits(ssi_private->regs, CCSR_SSI_SOR,
417 CCSR_SSI_SOR_RX_CLR, CCSR_SSI_SOR_RX_CLR);
418 } else {
419 regmap_update_bits(ssi_private->regs, CCSR_SSI_SOR,
420 CCSR_SSI_SOR_TX_CLR, CCSR_SSI_SOR_TX_CLR);
421 }
422 }
423
424 /*
425 * Calculate the bits that have to be disabled for the current stream that is
426 * getting disabled. This keeps the bits enabled that are necessary for the
427 * second stream to work if 'stream_active' is true.
428 *
429 * Detailed calculation:
430 * These are the values that need to be active after disabling. For non-active
431 * second stream, this is 0:
432 * vals_stream * !!stream_active
433 *
434 * The following computes the overall differences between the setup for the
435 * to-disable stream and the active stream, a simple XOR:
436 * vals_disable ^ (vals_stream * !!(stream_active))
437 *
438 * The full expression adds a mask on all values we care about
439 */
440 #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \
441 ((vals_disable) & \
442 ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active))))
443
444 /*
445 * Enable/Disable a ssi configuration. You have to pass either
446 * ssi_private->rxtx_reg_val.rx or tx as vals parameter.
447 */
fsl_ssi_config(struct fsl_ssi_private * ssi_private,bool enable,struct fsl_ssi_reg_val * vals)448 static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
449 struct fsl_ssi_reg_val *vals)
450 {
451 struct regmap *regs = ssi_private->regs;
452 struct fsl_ssi_reg_val *avals;
453 int nr_active_streams;
454 u32 scr_val;
455 int keep_active;
456
457 regmap_read(regs, CCSR_SSI_SCR, &scr_val);
458
459 nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) +
460 !!(scr_val & CCSR_SSI_SCR_RE);
461
462 if (nr_active_streams - 1 > 0)
463 keep_active = 1;
464 else
465 keep_active = 0;
466
467 /* Find the other direction values rx or tx which we do not want to
468 * modify */
469 if (&ssi_private->rxtx_reg_val.rx == vals)
470 avals = &ssi_private->rxtx_reg_val.tx;
471 else
472 avals = &ssi_private->rxtx_reg_val.rx;
473
474 /* If vals should be disabled, start with disabling the unit */
475 if (!enable) {
476 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr,
477 keep_active);
478 regmap_update_bits(regs, CCSR_SSI_SCR, scr, 0);
479 }
480
481 /*
482 * We are running on a SoC which does not support online SSI
483 * reconfiguration, so we have to enable all necessary flags at once
484 * even if we do not use them later (capture and playback configuration)
485 */
486 if (ssi_private->soc->offline_config) {
487 if ((enable && !nr_active_streams) ||
488 (!enable && !keep_active))
489 fsl_ssi_rxtx_config(ssi_private, enable);
490
491 goto config_done;
492 }
493
494 /*
495 * Configure single direction units while the SSI unit is running
496 * (online configuration)
497 */
498 if (enable) {
499 fsl_ssi_fifo_clear(ssi_private, vals->scr & CCSR_SSI_SCR_RE);
500
501 regmap_update_bits(regs, CCSR_SSI_SRCR, vals->srcr, vals->srcr);
502 regmap_update_bits(regs, CCSR_SSI_STCR, vals->stcr, vals->stcr);
503 regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier);
504 } else {
505 u32 sier;
506 u32 srcr;
507 u32 stcr;
508
509 /*
510 * Disabling the necessary flags for one of rx/tx while the
511 * other stream is active is a little bit more difficult. We
512 * have to disable only those flags that differ between both
513 * streams (rx XOR tx) and that are set in the stream that is
514 * disabled now. Otherwise we could alter flags of the other
515 * stream
516 */
517
518 /* These assignments are simply vals without bits set in avals*/
519 sier = fsl_ssi_disable_val(vals->sier, avals->sier,
520 keep_active);
521 srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr,
522 keep_active);
523 stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr,
524 keep_active);
525
526 regmap_update_bits(regs, CCSR_SSI_SRCR, srcr, 0);
527 regmap_update_bits(regs, CCSR_SSI_STCR, stcr, 0);
528 regmap_update_bits(regs, CCSR_SSI_SIER, sier, 0);
529 }
530
531 config_done:
532 /* Enabling of subunits is done after configuration */
533 if (enable) {
534 if (ssi_private->use_dma && (vals->scr & CCSR_SSI_SCR_TE)) {
535 /*
536 * Be sure the Tx FIFO is filled when TE is set.
537 * Otherwise, there are some chances to start the
538 * playback with some void samples inserted first,
539 * generating a channel slip.
540 *
541 * First, SSIEN must be set, to let the FIFO be filled.
542 *
543 * Notes:
544 * - Limit this fix to the DMA case until FIQ cases can
545 * be tested.
546 * - Limit the length of the busy loop to not lock the
547 * system too long, even if 1-2 loops are sufficient
548 * in general.
549 */
550 int i;
551 int max_loop = 100;
552 regmap_update_bits(regs, CCSR_SSI_SCR,
553 CCSR_SSI_SCR_SSIEN, CCSR_SSI_SCR_SSIEN);
554 for (i = 0; i < max_loop; i++) {
555 u32 sfcsr;
556 regmap_read(regs, CCSR_SSI_SFCSR, &sfcsr);
557 if (CCSR_SSI_SFCSR_TFCNT0(sfcsr))
558 break;
559 }
560 if (i == max_loop) {
561 dev_err(ssi_private->dev,
562 "Timeout waiting TX FIFO filling\n");
563 }
564 }
565 regmap_update_bits(regs, CCSR_SSI_SCR, vals->scr, vals->scr);
566 }
567 }
568
569
fsl_ssi_rx_config(struct fsl_ssi_private * ssi_private,bool enable)570 static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable)
571 {
572 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx);
573 }
574
fsl_ssi_tx_config(struct fsl_ssi_private * ssi_private,bool enable)575 static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable)
576 {
577 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx);
578 }
579
580 /*
581 * Setup rx/tx register values used to enable/disable the streams. These will
582 * be used later in fsl_ssi_config to setup the streams without the need to
583 * check for all different SSI modes.
584 */
fsl_ssi_setup_reg_vals(struct fsl_ssi_private * ssi_private)585 static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private)
586 {
587 struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val;
588
589 reg->rx.sier = CCSR_SSI_SIER_RFF0_EN;
590 reg->rx.srcr = CCSR_SSI_SRCR_RFEN0;
591 reg->rx.scr = 0;
592 reg->tx.sier = CCSR_SSI_SIER_TFE0_EN;
593 reg->tx.stcr = CCSR_SSI_STCR_TFEN0;
594 reg->tx.scr = 0;
595
596 if (!fsl_ssi_is_ac97(ssi_private)) {
597 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE;
598 reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN;
599 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE;
600 reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN;
601 }
602
603 if (ssi_private->use_dma) {
604 reg->rx.sier |= CCSR_SSI_SIER_RDMAE;
605 reg->tx.sier |= CCSR_SSI_SIER_TDMAE;
606 } else {
607 reg->rx.sier |= CCSR_SSI_SIER_RIE;
608 reg->tx.sier |= CCSR_SSI_SIER_TIE;
609 }
610
611 reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS;
612 reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS;
613 }
614
fsl_ssi_setup_ac97(struct fsl_ssi_private * ssi_private)615 static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
616 {
617 struct regmap *regs = ssi_private->regs;
618
619 /*
620 * Setup the clock control register
621 */
622 regmap_write(regs, CCSR_SSI_STCCR,
623 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
624 regmap_write(regs, CCSR_SSI_SRCCR,
625 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
626
627 /*
628 * Enable AC97 mode and startup the SSI
629 */
630 regmap_write(regs, CCSR_SSI_SACNT,
631 CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV);
632
633 /* no SACC{ST,EN,DIS} regs on imx21-class SSI */
634 if (!ssi_private->soc->imx21regs) {
635 regmap_write(regs, CCSR_SSI_SACCDIS, 0xff);
636 regmap_write(regs, CCSR_SSI_SACCEN, 0x300);
637 }
638
639 /*
640 * Enable SSI, Transmit and Receive. AC97 has to communicate with the
641 * codec before a stream is started.
642 */
643 regmap_update_bits(regs, CCSR_SSI_SCR,
644 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE,
645 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
646
647 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_WAIT(3));
648 }
649
650 /**
651 * fsl_ssi_startup: create a new substream
652 *
653 * This is the first function called when a stream is opened.
654 *
655 * If this is the first stream open, then grab the IRQ and program most of
656 * the SSI registers.
657 */
fsl_ssi_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)658 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
659 struct snd_soc_dai *dai)
660 {
661 struct snd_soc_pcm_runtime *rtd = substream->private_data;
662 struct fsl_ssi_private *ssi_private =
663 snd_soc_dai_get_drvdata(rtd->cpu_dai);
664 int ret;
665
666 ret = clk_prepare_enable(ssi_private->clk);
667 if (ret)
668 return ret;
669
670 /* When using dual fifo mode, it is safer to ensure an even period
671 * size. If appearing to an odd number while DMA always starts its
672 * task from fifo0, fifo1 would be neglected at the end of each
673 * period. But SSI would still access fifo1 with an invalid data.
674 */
675 if (ssi_private->use_dual_fifo)
676 snd_pcm_hw_constraint_step(substream->runtime, 0,
677 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
678
679 return 0;
680 }
681
682 /**
683 * fsl_ssi_shutdown: shutdown the SSI
684 *
685 */
fsl_ssi_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)686 static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
687 struct snd_soc_dai *dai)
688 {
689 struct snd_soc_pcm_runtime *rtd = substream->private_data;
690 struct fsl_ssi_private *ssi_private =
691 snd_soc_dai_get_drvdata(rtd->cpu_dai);
692
693 clk_disable_unprepare(ssi_private->clk);
694
695 }
696
697 /**
698 * fsl_ssi_set_bclk - configure Digital Audio Interface bit clock
699 *
700 * Note: This function can be only called when using SSI as DAI master
701 *
702 * Quick instruction for parameters:
703 * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
704 * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
705 */
fsl_ssi_set_bclk(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai,struct snd_pcm_hw_params * hw_params)706 static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
707 struct snd_soc_dai *cpu_dai,
708 struct snd_pcm_hw_params *hw_params)
709 {
710 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
711 struct regmap *regs = ssi_private->regs;
712 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;
713 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
714 unsigned long clkrate, baudrate, tmprate;
715 u64 sub, savesub = 100000;
716 unsigned int freq;
717 bool baudclk_is_used;
718
719 /* Prefer the explicitly set bitclock frequency */
720 if (ssi_private->bitclk_freq)
721 freq = ssi_private->bitclk_freq;
722 else
723 freq = params_channels(hw_params) * 32 * params_rate(hw_params);
724
725 /* Don't apply it to any non-baudclk circumstance */
726 if (IS_ERR(ssi_private->baudclk))
727 return -EINVAL;
728
729 /*
730 * Hardware limitation: The bclk rate must be
731 * never greater than 1/5 IPG clock rate
732 */
733 if (freq * 5 > clk_get_rate(ssi_private->clk)) {
734 dev_err(cpu_dai->dev, "bitclk > ipgclk/5\n");
735 return -EINVAL;
736 }
737
738 baudclk_is_used = ssi_private->baudclk_streams & ~(BIT(substream->stream));
739
740 /* It should be already enough to divide clock by setting pm alone */
741 psr = 0;
742 div2 = 0;
743
744 factor = (div2 + 1) * (7 * psr + 1) * 2;
745
746 for (i = 0; i < 255; i++) {
747 tmprate = freq * factor * (i + 1);
748
749 if (baudclk_is_used)
750 clkrate = clk_get_rate(ssi_private->baudclk);
751 else
752 clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
753
754 clkrate /= factor;
755 afreq = clkrate / (i + 1);
756
757 if (freq == afreq)
758 sub = 0;
759 else if (freq / afreq == 1)
760 sub = freq - afreq;
761 else if (afreq / freq == 1)
762 sub = afreq - freq;
763 else
764 continue;
765
766 /* Calculate the fraction */
767 sub *= 100000;
768 do_div(sub, freq);
769
770 if (sub < savesub && !(i == 0 && psr == 0 && div2 == 0)) {
771 baudrate = tmprate;
772 savesub = sub;
773 pm = i;
774 }
775
776 /* We are lucky */
777 if (savesub == 0)
778 break;
779 }
780
781 /* No proper pm found if it is still remaining the initial value */
782 if (pm == 999) {
783 dev_err(cpu_dai->dev, "failed to handle the required sysclk\n");
784 return -EINVAL;
785 }
786
787 stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) |
788 (psr ? CCSR_SSI_SxCCR_PSR : 0);
789 mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 |
790 CCSR_SSI_SxCCR_PSR;
791
792 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous)
793 regmap_update_bits(regs, CCSR_SSI_STCCR, mask, stccr);
794 else
795 regmap_update_bits(regs, CCSR_SSI_SRCCR, mask, stccr);
796
797 if (!baudclk_is_used) {
798 ret = clk_set_rate(ssi_private->baudclk, baudrate);
799 if (ret) {
800 dev_err(cpu_dai->dev, "failed to set baudclk rate\n");
801 return -EINVAL;
802 }
803 }
804
805 return 0;
806 }
807
fsl_ssi_set_dai_sysclk(struct snd_soc_dai * cpu_dai,int clk_id,unsigned int freq,int dir)808 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
809 int clk_id, unsigned int freq, int dir)
810 {
811 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
812
813 ssi_private->bitclk_freq = freq;
814
815 return 0;
816 }
817
818 /**
819 * fsl_ssi_hw_params - program the sample size
820 *
821 * Most of the SSI registers have been programmed in the startup function,
822 * but the word length must be programmed here. Unfortunately, programming
823 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can
824 * cause a problem with supporting simultaneous playback and capture. If
825 * the SSI is already playing a stream, then that stream may be temporarily
826 * stopped when you start capture.
827 *
828 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
829 * clock master.
830 */
fsl_ssi_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * hw_params,struct snd_soc_dai * cpu_dai)831 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
832 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
833 {
834 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
835 struct regmap *regs = ssi_private->regs;
836 unsigned int channels = params_channels(hw_params);
837 unsigned int sample_size = params_width(hw_params);
838 u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
839 int ret;
840 u32 scr_val;
841 int enabled;
842
843 regmap_read(regs, CCSR_SSI_SCR, &scr_val);
844 enabled = scr_val & CCSR_SSI_SCR_SSIEN;
845
846 /*
847 * If we're in synchronous mode, and the SSI is already enabled,
848 * then STCCR is already set properly.
849 */
850 if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
851 return 0;
852
853 if (fsl_ssi_is_i2s_master(ssi_private)) {
854 ret = fsl_ssi_set_bclk(substream, cpu_dai, hw_params);
855 if (ret)
856 return ret;
857
858 /* Do not enable the clock if it is already enabled */
859 if (!(ssi_private->baudclk_streams & BIT(substream->stream))) {
860 ret = clk_prepare_enable(ssi_private->baudclk);
861 if (ret)
862 return ret;
863
864 ssi_private->baudclk_streams |= BIT(substream->stream);
865 }
866 }
867
868 if (!fsl_ssi_is_ac97(ssi_private)) {
869 u8 i2smode;
870 /*
871 * Switch to normal net mode in order to have a frame sync
872 * signal every 32 bits instead of 16 bits
873 */
874 if (fsl_ssi_is_i2s_cbm_cfs(ssi_private) && sample_size == 16)
875 i2smode = CCSR_SSI_SCR_I2S_MODE_NORMAL |
876 CCSR_SSI_SCR_NET;
877 else
878 i2smode = ssi_private->i2s_mode;
879
880 regmap_update_bits(regs, CCSR_SSI_SCR,
881 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
882 channels == 1 ? 0 : i2smode);
883 }
884
885 /*
886 * FIXME: The documentation says that SxCCR[WL] should not be
887 * modified while the SSI is enabled. The only time this can
888 * happen is if we're trying to do simultaneous playback and
889 * capture in asynchronous mode. Unfortunately, I have been enable
890 * to get that to work at all on the P1022DS. Therefore, we don't
891 * bother to disable/enable the SSI when setting SxCCR[WL], because
892 * the SSI will stop anyway. Maybe one day, this will get fixed.
893 */
894
895 /* In synchronous mode, the SSI uses STCCR for capture */
896 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
897 ssi_private->cpu_dai_drv.symmetric_rates)
898 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_WL_MASK,
899 wl);
900 else
901 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_WL_MASK,
902 wl);
903
904 return 0;
905 }
906
fsl_ssi_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)907 static int fsl_ssi_hw_free(struct snd_pcm_substream *substream,
908 struct snd_soc_dai *cpu_dai)
909 {
910 struct snd_soc_pcm_runtime *rtd = substream->private_data;
911 struct fsl_ssi_private *ssi_private =
912 snd_soc_dai_get_drvdata(rtd->cpu_dai);
913
914 if (fsl_ssi_is_i2s_master(ssi_private) &&
915 ssi_private->baudclk_streams & BIT(substream->stream)) {
916 clk_disable_unprepare(ssi_private->baudclk);
917 ssi_private->baudclk_streams &= ~BIT(substream->stream);
918 }
919
920 return 0;
921 }
922
_fsl_ssi_set_dai_fmt(struct device * dev,struct fsl_ssi_private * ssi_private,unsigned int fmt)923 static int _fsl_ssi_set_dai_fmt(struct device *dev,
924 struct fsl_ssi_private *ssi_private,
925 unsigned int fmt)
926 {
927 struct regmap *regs = ssi_private->regs;
928 u32 strcr = 0, stcr, srcr, scr, mask;
929 u8 wm;
930
931 ssi_private->dai_fmt = fmt;
932
933 if (fsl_ssi_is_i2s_master(ssi_private) && IS_ERR(ssi_private->baudclk)) {
934 dev_err(dev, "baudclk is missing which is necessary for master mode\n");
935 return -EINVAL;
936 }
937
938 fsl_ssi_setup_reg_vals(ssi_private);
939
940 regmap_read(regs, CCSR_SSI_SCR, &scr);
941 scr &= ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK);
942 scr |= CCSR_SSI_SCR_SYNC_TX_FS;
943
944 mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR |
945 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL |
946 CCSR_SSI_STCR_TEFS;
947 regmap_read(regs, CCSR_SSI_STCR, &stcr);
948 regmap_read(regs, CCSR_SSI_SRCR, &srcr);
949 stcr &= ~mask;
950 srcr &= ~mask;
951
952 ssi_private->i2s_mode = CCSR_SSI_SCR_NET;
953 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
954 case SND_SOC_DAIFMT_I2S:
955 regmap_update_bits(regs, CCSR_SSI_STCCR,
956 CCSR_SSI_SxCCR_DC_MASK,
957 CCSR_SSI_SxCCR_DC(2));
958 regmap_update_bits(regs, CCSR_SSI_SRCCR,
959 CCSR_SSI_SxCCR_DC_MASK,
960 CCSR_SSI_SxCCR_DC(2));
961 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
962 case SND_SOC_DAIFMT_CBM_CFS:
963 case SND_SOC_DAIFMT_CBS_CFS:
964 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER;
965 break;
966 case SND_SOC_DAIFMT_CBM_CFM:
967 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE;
968 break;
969 default:
970 return -EINVAL;
971 }
972
973 /* Data on rising edge of bclk, frame low, 1clk before data */
974 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP |
975 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
976 break;
977 case SND_SOC_DAIFMT_LEFT_J:
978 /* Data on rising edge of bclk, frame high */
979 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP;
980 break;
981 case SND_SOC_DAIFMT_DSP_A:
982 /* Data on rising edge of bclk, frame high, 1clk before data */
983 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
984 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
985 break;
986 case SND_SOC_DAIFMT_DSP_B:
987 /* Data on rising edge of bclk, frame high */
988 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
989 CCSR_SSI_STCR_TXBIT0;
990 break;
991 case SND_SOC_DAIFMT_AC97:
992 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL;
993 break;
994 default:
995 return -EINVAL;
996 }
997 scr |= ssi_private->i2s_mode;
998
999 /* DAI clock inversion */
1000 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1001 case SND_SOC_DAIFMT_NB_NF:
1002 /* Nothing to do for both normal cases */
1003 break;
1004 case SND_SOC_DAIFMT_IB_NF:
1005 /* Invert bit clock */
1006 strcr ^= CCSR_SSI_STCR_TSCKP;
1007 break;
1008 case SND_SOC_DAIFMT_NB_IF:
1009 /* Invert frame clock */
1010 strcr ^= CCSR_SSI_STCR_TFSI;
1011 break;
1012 case SND_SOC_DAIFMT_IB_IF:
1013 /* Invert both clocks */
1014 strcr ^= CCSR_SSI_STCR_TSCKP;
1015 strcr ^= CCSR_SSI_STCR_TFSI;
1016 break;
1017 default:
1018 return -EINVAL;
1019 }
1020
1021 /* DAI clock master masks */
1022 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1023 case SND_SOC_DAIFMT_CBS_CFS:
1024 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR;
1025 scr |= CCSR_SSI_SCR_SYS_CLK_EN;
1026 break;
1027 case SND_SOC_DAIFMT_CBM_CFM:
1028 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
1029 break;
1030 case SND_SOC_DAIFMT_CBM_CFS:
1031 strcr &= ~CCSR_SSI_STCR_TXDIR;
1032 strcr |= CCSR_SSI_STCR_TFDIR;
1033 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
1034 break;
1035 default:
1036 if (!fsl_ssi_is_ac97(ssi_private))
1037 return -EINVAL;
1038 }
1039
1040 stcr |= strcr;
1041 srcr |= strcr;
1042
1043 if (ssi_private->cpu_dai_drv.symmetric_rates
1044 || fsl_ssi_is_ac97(ssi_private)) {
1045 /* Need to clear RXDIR when using SYNC or AC97 mode */
1046 srcr &= ~CCSR_SSI_SRCR_RXDIR;
1047 scr |= CCSR_SSI_SCR_SYN;
1048 }
1049
1050 regmap_write(regs, CCSR_SSI_STCR, stcr);
1051 regmap_write(regs, CCSR_SSI_SRCR, srcr);
1052 regmap_write(regs, CCSR_SSI_SCR, scr);
1053
1054 wm = ssi_private->fifo_watermark;
1055
1056 regmap_write(regs, CCSR_SSI_SFCSR,
1057 CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
1058 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm));
1059
1060 if (ssi_private->use_dual_fifo) {
1061 regmap_update_bits(regs, CCSR_SSI_SRCR, CCSR_SSI_SRCR_RFEN1,
1062 CCSR_SSI_SRCR_RFEN1);
1063 regmap_update_bits(regs, CCSR_SSI_STCR, CCSR_SSI_STCR_TFEN1,
1064 CCSR_SSI_STCR_TFEN1);
1065 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_TCH_EN,
1066 CCSR_SSI_SCR_TCH_EN);
1067 }
1068
1069 if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_AC97)
1070 fsl_ssi_setup_ac97(ssi_private);
1071
1072 return 0;
1073
1074 }
1075
1076 /**
1077 * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
1078 */
fsl_ssi_set_dai_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)1079 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
1080 {
1081 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
1082
1083 return _fsl_ssi_set_dai_fmt(cpu_dai->dev, ssi_private, fmt);
1084 }
1085
1086 /**
1087 * fsl_ssi_set_dai_tdm_slot - set TDM slot number
1088 *
1089 * Note: This function can be only called when using SSI as DAI master
1090 */
fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai * cpu_dai,u32 tx_mask,u32 rx_mask,int slots,int slot_width)1091 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
1092 u32 rx_mask, int slots, int slot_width)
1093 {
1094 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
1095 struct regmap *regs = ssi_private->regs;
1096 u32 val;
1097
1098 /* The slot number should be >= 2 if using Network mode or I2S mode */
1099 regmap_read(regs, CCSR_SSI_SCR, &val);
1100 val &= CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET;
1101 if (val && slots < 2) {
1102 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n");
1103 return -EINVAL;
1104 }
1105
1106 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_DC_MASK,
1107 CCSR_SSI_SxCCR_DC(slots));
1108 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_DC_MASK,
1109 CCSR_SSI_SxCCR_DC(slots));
1110
1111 /* The register SxMSKs needs SSI to provide essential clock due to
1112 * hardware design. So we here temporarily enable SSI to set them.
1113 */
1114 regmap_read(regs, CCSR_SSI_SCR, &val);
1115 val &= CCSR_SSI_SCR_SSIEN;
1116 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN,
1117 CCSR_SSI_SCR_SSIEN);
1118
1119 regmap_write(regs, CCSR_SSI_STMSK, ~tx_mask);
1120 regmap_write(regs, CCSR_SSI_SRMSK, ~rx_mask);
1121
1122 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, val);
1123
1124 return 0;
1125 }
1126
1127 /**
1128 * fsl_ssi_trigger: start and stop the DMA transfer.
1129 *
1130 * This function is called by ALSA to start, stop, pause, and resume the DMA
1131 * transfer of data.
1132 *
1133 * The DMA channel is in external master start and pause mode, which
1134 * means the SSI completely controls the flow of data.
1135 */
fsl_ssi_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)1136 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
1137 struct snd_soc_dai *dai)
1138 {
1139 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1140 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
1141 struct regmap *regs = ssi_private->regs;
1142
1143 switch (cmd) {
1144 case SNDRV_PCM_TRIGGER_START:
1145 case SNDRV_PCM_TRIGGER_RESUME:
1146 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1147 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1148 fsl_ssi_tx_config(ssi_private, true);
1149 else
1150 fsl_ssi_rx_config(ssi_private, true);
1151 break;
1152
1153 case SNDRV_PCM_TRIGGER_STOP:
1154 case SNDRV_PCM_TRIGGER_SUSPEND:
1155 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1156 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1157 fsl_ssi_tx_config(ssi_private, false);
1158 else
1159 fsl_ssi_rx_config(ssi_private, false);
1160 break;
1161
1162 default:
1163 return -EINVAL;
1164 }
1165
1166 if (fsl_ssi_is_ac97(ssi_private)) {
1167 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1168 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_TX_CLR);
1169 else
1170 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_RX_CLR);
1171 }
1172
1173 return 0;
1174 }
1175
fsl_ssi_dai_probe(struct snd_soc_dai * dai)1176 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
1177 {
1178 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
1179
1180 if (ssi_private->soc->imx && ssi_private->use_dma) {
1181 dai->playback_dma_data = &ssi_private->dma_params_tx;
1182 dai->capture_dma_data = &ssi_private->dma_params_rx;
1183 }
1184
1185 return 0;
1186 }
1187
1188 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
1189 .startup = fsl_ssi_startup,
1190 .shutdown = fsl_ssi_shutdown,
1191 .hw_params = fsl_ssi_hw_params,
1192 .hw_free = fsl_ssi_hw_free,
1193 .set_fmt = fsl_ssi_set_dai_fmt,
1194 .set_sysclk = fsl_ssi_set_dai_sysclk,
1195 .set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
1196 .trigger = fsl_ssi_trigger,
1197 };
1198
1199 /* Template for the CPU dai driver structure */
1200 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
1201 .probe = fsl_ssi_dai_probe,
1202 .playback = {
1203 .stream_name = "CPU-Playback",
1204 .channels_min = 1,
1205 .channels_max = 32,
1206 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1207 .formats = FSLSSI_I2S_FORMATS,
1208 },
1209 .capture = {
1210 .stream_name = "CPU-Capture",
1211 .channels_min = 1,
1212 .channels_max = 32,
1213 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1214 .formats = FSLSSI_I2S_FORMATS,
1215 },
1216 .ops = &fsl_ssi_dai_ops,
1217 };
1218
1219 static const struct snd_soc_component_driver fsl_ssi_component = {
1220 .name = "fsl-ssi",
1221 };
1222
1223 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
1224 .bus_control = true,
1225 .probe = fsl_ssi_dai_probe,
1226 .playback = {
1227 .stream_name = "AC97 Playback",
1228 .channels_min = 2,
1229 .channels_max = 2,
1230 .rates = SNDRV_PCM_RATE_8000_48000,
1231 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1232 },
1233 .capture = {
1234 .stream_name = "AC97 Capture",
1235 .channels_min = 2,
1236 .channels_max = 2,
1237 .rates = SNDRV_PCM_RATE_48000,
1238 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1239 },
1240 .ops = &fsl_ssi_dai_ops,
1241 };
1242
1243
1244 static struct fsl_ssi_private *fsl_ac97_data;
1245
fsl_ssi_ac97_write(struct snd_ac97 * ac97,unsigned short reg,unsigned short val)1246 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
1247 unsigned short val)
1248 {
1249 struct regmap *regs = fsl_ac97_data->regs;
1250 unsigned int lreg;
1251 unsigned int lval;
1252 int ret;
1253
1254 if (reg > 0x7f)
1255 return;
1256
1257 ret = clk_prepare_enable(fsl_ac97_data->clk);
1258 if (ret) {
1259 pr_err("ac97 write clk_prepare_enable failed: %d\n",
1260 ret);
1261 return;
1262 }
1263
1264 lreg = reg << 12;
1265 regmap_write(regs, CCSR_SSI_SACADD, lreg);
1266
1267 lval = val << 4;
1268 regmap_write(regs, CCSR_SSI_SACDAT, lval);
1269
1270 regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
1271 CCSR_SSI_SACNT_WR);
1272 udelay(100);
1273
1274 clk_disable_unprepare(fsl_ac97_data->clk);
1275 }
1276
fsl_ssi_ac97_read(struct snd_ac97 * ac97,unsigned short reg)1277 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
1278 unsigned short reg)
1279 {
1280 struct regmap *regs = fsl_ac97_data->regs;
1281
1282 unsigned short val = -1;
1283 u32 reg_val;
1284 unsigned int lreg;
1285 int ret;
1286
1287 ret = clk_prepare_enable(fsl_ac97_data->clk);
1288 if (ret) {
1289 pr_err("ac97 read clk_prepare_enable failed: %d\n",
1290 ret);
1291 return -1;
1292 }
1293
1294 lreg = (reg & 0x7f) << 12;
1295 regmap_write(regs, CCSR_SSI_SACADD, lreg);
1296 regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
1297 CCSR_SSI_SACNT_RD);
1298
1299 udelay(100);
1300
1301 regmap_read(regs, CCSR_SSI_SACDAT, ®_val);
1302 val = (reg_val >> 4) & 0xffff;
1303
1304 clk_disable_unprepare(fsl_ac97_data->clk);
1305
1306 return val;
1307 }
1308
1309 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
1310 .read = fsl_ssi_ac97_read,
1311 .write = fsl_ssi_ac97_write,
1312 };
1313
1314 /**
1315 * Make every character in a string lower-case
1316 */
make_lowercase(char * s)1317 static void make_lowercase(char *s)
1318 {
1319 if (!s)
1320 return;
1321 for (; *s; s++)
1322 *s = tolower(*s);
1323 }
1324
fsl_ssi_imx_probe(struct platform_device * pdev,struct fsl_ssi_private * ssi_private,void __iomem * iomem)1325 static int fsl_ssi_imx_probe(struct platform_device *pdev,
1326 struct fsl_ssi_private *ssi_private, void __iomem *iomem)
1327 {
1328 struct device_node *np = pdev->dev.of_node;
1329 u32 dmas[4];
1330 int ret;
1331
1332 if (ssi_private->has_ipg_clk_name)
1333 ssi_private->clk = devm_clk_get(&pdev->dev, "ipg");
1334 else
1335 ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
1336 if (IS_ERR(ssi_private->clk)) {
1337 ret = PTR_ERR(ssi_private->clk);
1338 dev_err(&pdev->dev, "could not get clock: %d\n", ret);
1339 return ret;
1340 }
1341
1342 if (!ssi_private->has_ipg_clk_name) {
1343 ret = clk_prepare_enable(ssi_private->clk);
1344 if (ret) {
1345 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1346 return ret;
1347 }
1348 }
1349
1350 /* For those SLAVE implementations, we ignore non-baudclk cases
1351 * and, instead, abandon MASTER mode that needs baud clock.
1352 */
1353 ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud");
1354 if (IS_ERR(ssi_private->baudclk))
1355 dev_dbg(&pdev->dev, "could not get baud clock: %ld\n",
1356 PTR_ERR(ssi_private->baudclk));
1357
1358 ssi_private->dma_params_tx.maxburst = ssi_private->dma_maxburst;
1359 ssi_private->dma_params_rx.maxburst = ssi_private->dma_maxburst;
1360 ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + CCSR_SSI_STX0;
1361 ssi_private->dma_params_rx.addr = ssi_private->ssi_phys + CCSR_SSI_SRX0;
1362
1363 ret = of_property_read_u32_array(np, "dmas", dmas, 4);
1364 if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) {
1365 ssi_private->use_dual_fifo = true;
1366 /* When using dual fifo mode, we need to keep watermark
1367 * as even numbers due to dma script limitation.
1368 */
1369 ssi_private->dma_params_tx.maxburst &= ~0x1;
1370 ssi_private->dma_params_rx.maxburst &= ~0x1;
1371 }
1372
1373 if (!ssi_private->use_dma) {
1374
1375 /*
1376 * Some boards use an incompatible codec. To get it
1377 * working, we are using imx-fiq-pcm-audio, that
1378 * can handle those codecs. DMA is not possible in this
1379 * situation.
1380 */
1381
1382 ssi_private->fiq_params.irq = ssi_private->irq;
1383 ssi_private->fiq_params.base = iomem;
1384 ssi_private->fiq_params.dma_params_rx =
1385 &ssi_private->dma_params_rx;
1386 ssi_private->fiq_params.dma_params_tx =
1387 &ssi_private->dma_params_tx;
1388
1389 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
1390 if (ret)
1391 goto error_pcm;
1392 } else {
1393 ret = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE);
1394 if (ret)
1395 goto error_pcm;
1396 }
1397
1398 return 0;
1399
1400 error_pcm:
1401
1402 if (!ssi_private->has_ipg_clk_name)
1403 clk_disable_unprepare(ssi_private->clk);
1404 return ret;
1405 }
1406
fsl_ssi_imx_clean(struct platform_device * pdev,struct fsl_ssi_private * ssi_private)1407 static void fsl_ssi_imx_clean(struct platform_device *pdev,
1408 struct fsl_ssi_private *ssi_private)
1409 {
1410 if (!ssi_private->use_dma)
1411 imx_pcm_fiq_exit(pdev);
1412 if (!ssi_private->has_ipg_clk_name)
1413 clk_disable_unprepare(ssi_private->clk);
1414 }
1415
fsl_ssi_probe(struct platform_device * pdev)1416 static int fsl_ssi_probe(struct platform_device *pdev)
1417 {
1418 struct fsl_ssi_private *ssi_private;
1419 int ret = 0;
1420 struct device_node *np = pdev->dev.of_node;
1421 struct device_node *root;
1422 const struct of_device_id *of_id;
1423 const char *p, *sprop;
1424 const uint32_t *iprop;
1425 struct resource *res;
1426 void __iomem *iomem;
1427 char name[64];
1428 struct regmap_config regconfig = fsl_ssi_regconfig;
1429
1430 of_id = of_match_device(fsl_ssi_ids, &pdev->dev);
1431 if (!of_id || !of_id->data)
1432 return -EINVAL;
1433
1434 ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private),
1435 GFP_KERNEL);
1436 if (!ssi_private)
1437 return -ENOMEM;
1438
1439 ssi_private->soc = of_id->data;
1440 ssi_private->dev = &pdev->dev;
1441
1442 sprop = of_get_property(np, "fsl,mode", NULL);
1443 if (sprop) {
1444 if (!strcmp(sprop, "ac97-slave"))
1445 ssi_private->dai_fmt = SND_SOC_DAIFMT_AC97;
1446 }
1447
1448 ssi_private->use_dma = !of_property_read_bool(np,
1449 "fsl,fiq-stream-filter");
1450
1451 if (fsl_ssi_is_ac97(ssi_private)) {
1452 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
1453 sizeof(fsl_ssi_ac97_dai));
1454
1455 fsl_ac97_data = ssi_private;
1456 } else {
1457 /* Initialize this copy of the CPU DAI driver structure */
1458 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
1459 sizeof(fsl_ssi_dai_template));
1460 }
1461 ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev);
1462
1463 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1464 iomem = devm_ioremap_resource(&pdev->dev, res);
1465 if (IS_ERR(iomem))
1466 return PTR_ERR(iomem);
1467 ssi_private->ssi_phys = res->start;
1468
1469 if (ssi_private->soc->imx21regs) {
1470 /*
1471 * According to datasheet imx21-class SSI
1472 * don't have SACC{ST,EN,DIS} regs.
1473 */
1474 regconfig.max_register = CCSR_SSI_SRMSK;
1475 regconfig.num_reg_defaults_raw =
1476 CCSR_SSI_SRMSK / sizeof(uint32_t) + 1;
1477 }
1478
1479 ret = of_property_match_string(np, "clock-names", "ipg");
1480 if (ret < 0) {
1481 ssi_private->has_ipg_clk_name = false;
1482 ssi_private->regs = devm_regmap_init_mmio(&pdev->dev, iomem,
1483 ®config);
1484 } else {
1485 ssi_private->has_ipg_clk_name = true;
1486 ssi_private->regs = devm_regmap_init_mmio_clk(&pdev->dev,
1487 "ipg", iomem, ®config);
1488 }
1489 if (IS_ERR(ssi_private->regs)) {
1490 dev_err(&pdev->dev, "Failed to init register map\n");
1491 return PTR_ERR(ssi_private->regs);
1492 }
1493
1494 ssi_private->irq = platform_get_irq(pdev, 0);
1495 if (ssi_private->irq < 0) {
1496 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
1497 return ssi_private->irq;
1498 }
1499
1500 /* Are the RX and the TX clocks locked? */
1501 if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
1502 if (!fsl_ssi_is_ac97(ssi_private))
1503 ssi_private->cpu_dai_drv.symmetric_rates = 1;
1504
1505 ssi_private->cpu_dai_drv.symmetric_channels = 1;
1506 ssi_private->cpu_dai_drv.symmetric_samplebits = 1;
1507 }
1508
1509 /* Determine the FIFO depth. */
1510 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
1511 if (iprop)
1512 ssi_private->fifo_depth = be32_to_cpup(iprop);
1513 else
1514 /* Older 8610 DTs didn't have the fifo-depth property */
1515 ssi_private->fifo_depth = 8;
1516
1517 /*
1518 * Set the watermark for transmit FIFO 0 and receive FIFO 0. We don't
1519 * use FIFO 1 but set the watermark appropriately nontheless.
1520 * We program the transmit water to signal a DMA transfer
1521 * if there are N elements left in the FIFO. For chips with 15-deep
1522 * FIFOs, set watermark to 8. This allows the SSI to operate at a
1523 * high data rate without channel slipping. Behavior is unchanged
1524 * for the older chips with a fifo depth of only 8. A value of 4
1525 * might be appropriate for the older chips, but is left at
1526 * fifo_depth-2 until sombody has a chance to test.
1527 *
1528 * We set the watermark on the same level as the DMA burstsize. For
1529 * fiq it is probably better to use the biggest possible watermark
1530 * size.
1531 */
1532 switch (ssi_private->fifo_depth) {
1533 case 15:
1534 /*
1535 * 2 samples is not enough when running at high data
1536 * rates (like 48kHz @ 16 bits/channel, 16 channels)
1537 * 8 seems to split things evenly and leave enough time
1538 * for the DMA to fill the FIFO before it's over/under
1539 * run.
1540 */
1541 ssi_private->fifo_watermark = 8;
1542 ssi_private->dma_maxburst = 8;
1543 break;
1544 case 8:
1545 default:
1546 /*
1547 * maintain old behavior for older chips.
1548 * Keeping it the same because I don't have an older
1549 * board to test with.
1550 * I suspect this could be changed to be something to
1551 * leave some more space in the fifo.
1552 */
1553 ssi_private->fifo_watermark = ssi_private->fifo_depth - 2;
1554 ssi_private->dma_maxburst = ssi_private->fifo_depth - 2;
1555 break;
1556 }
1557
1558 dev_set_drvdata(&pdev->dev, ssi_private);
1559
1560 if (ssi_private->soc->imx) {
1561 ret = fsl_ssi_imx_probe(pdev, ssi_private, iomem);
1562 if (ret)
1563 return ret;
1564 }
1565
1566 if (fsl_ssi_is_ac97(ssi_private)) {
1567 ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
1568 if (ret) {
1569 dev_err(&pdev->dev, "could not set AC'97 ops\n");
1570 goto error_ac97_ops;
1571 }
1572 }
1573
1574 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
1575 &ssi_private->cpu_dai_drv, 1);
1576 if (ret) {
1577 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1578 goto error_asoc_register;
1579 }
1580
1581 if (ssi_private->use_dma) {
1582 ret = devm_request_irq(&pdev->dev, ssi_private->irq,
1583 fsl_ssi_isr, 0, dev_name(&pdev->dev),
1584 ssi_private);
1585 if (ret < 0) {
1586 dev_err(&pdev->dev, "could not claim irq %u\n",
1587 ssi_private->irq);
1588 goto error_asoc_register;
1589 }
1590 }
1591
1592 ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev);
1593 if (ret)
1594 goto error_asoc_register;
1595
1596 /*
1597 * If codec-handle property is missing from SSI node, we assume
1598 * that the machine driver uses new binding which does not require
1599 * SSI driver to trigger machine driver's probe.
1600 */
1601 if (!of_get_property(np, "codec-handle", NULL))
1602 goto done;
1603
1604 /* Trigger the machine driver's probe function. The platform driver
1605 * name of the machine driver is taken from /compatible property of the
1606 * device tree. We also pass the address of the CPU DAI driver
1607 * structure.
1608 */
1609 root = of_find_node_by_path("/");
1610 sprop = of_get_property(root, "compatible", NULL);
1611 of_node_put(root);
1612 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1613 p = strrchr(sprop, ',');
1614 if (p)
1615 sprop = p + 1;
1616 snprintf(name, sizeof(name), "snd-soc-%s", sprop);
1617 make_lowercase(name);
1618
1619 ssi_private->pdev =
1620 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1621 if (IS_ERR(ssi_private->pdev)) {
1622 ret = PTR_ERR(ssi_private->pdev);
1623 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1624 goto error_sound_card;
1625 }
1626
1627 done:
1628 if (ssi_private->dai_fmt)
1629 _fsl_ssi_set_dai_fmt(&pdev->dev, ssi_private,
1630 ssi_private->dai_fmt);
1631
1632 if (fsl_ssi_is_ac97(ssi_private)) {
1633 u32 ssi_idx;
1634
1635 ret = of_property_read_u32(np, "cell-index", &ssi_idx);
1636 if (ret) {
1637 dev_err(&pdev->dev, "cannot get SSI index property\n");
1638 goto error_sound_card;
1639 }
1640
1641 ssi_private->pdev =
1642 platform_device_register_data(NULL,
1643 "ac97-codec", ssi_idx, NULL, 0);
1644 if (IS_ERR(ssi_private->pdev)) {
1645 ret = PTR_ERR(ssi_private->pdev);
1646 dev_err(&pdev->dev,
1647 "failed to register AC97 codec platform: %d\n",
1648 ret);
1649 goto error_sound_card;
1650 }
1651 }
1652
1653 return 0;
1654
1655 error_sound_card:
1656 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1657
1658 error_asoc_register:
1659 if (fsl_ssi_is_ac97(ssi_private))
1660 snd_soc_set_ac97_ops(NULL);
1661
1662 error_ac97_ops:
1663 if (ssi_private->soc->imx)
1664 fsl_ssi_imx_clean(pdev, ssi_private);
1665
1666 return ret;
1667 }
1668
fsl_ssi_remove(struct platform_device * pdev)1669 static int fsl_ssi_remove(struct platform_device *pdev)
1670 {
1671 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1672
1673 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1674
1675 if (ssi_private->pdev)
1676 platform_device_unregister(ssi_private->pdev);
1677
1678 if (ssi_private->soc->imx)
1679 fsl_ssi_imx_clean(pdev, ssi_private);
1680
1681 if (fsl_ssi_is_ac97(ssi_private))
1682 snd_soc_set_ac97_ops(NULL);
1683
1684 return 0;
1685 }
1686
1687 #ifdef CONFIG_PM_SLEEP
fsl_ssi_suspend(struct device * dev)1688 static int fsl_ssi_suspend(struct device *dev)
1689 {
1690 struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev);
1691 struct regmap *regs = ssi_private->regs;
1692
1693 regmap_read(regs, CCSR_SSI_SFCSR,
1694 &ssi_private->regcache_sfcsr);
1695 regmap_read(regs, CCSR_SSI_SACNT,
1696 &ssi_private->regcache_sacnt);
1697
1698 regcache_cache_only(regs, true);
1699 regcache_mark_dirty(regs);
1700
1701 return 0;
1702 }
1703
fsl_ssi_resume(struct device * dev)1704 static int fsl_ssi_resume(struct device *dev)
1705 {
1706 struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev);
1707 struct regmap *regs = ssi_private->regs;
1708
1709 regcache_cache_only(regs, false);
1710
1711 regmap_update_bits(regs, CCSR_SSI_SFCSR,
1712 CCSR_SSI_SFCSR_RFWM1_MASK | CCSR_SSI_SFCSR_TFWM1_MASK |
1713 CCSR_SSI_SFCSR_RFWM0_MASK | CCSR_SSI_SFCSR_TFWM0_MASK,
1714 ssi_private->regcache_sfcsr);
1715 regmap_write(regs, CCSR_SSI_SACNT,
1716 ssi_private->regcache_sacnt);
1717
1718 return regcache_sync(regs);
1719 }
1720 #endif /* CONFIG_PM_SLEEP */
1721
1722 static const struct dev_pm_ops fsl_ssi_pm = {
1723 SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume)
1724 };
1725
1726 static struct platform_driver fsl_ssi_driver = {
1727 .driver = {
1728 .name = "fsl-ssi-dai",
1729 .of_match_table = fsl_ssi_ids,
1730 .pm = &fsl_ssi_pm,
1731 },
1732 .probe = fsl_ssi_probe,
1733 .remove = fsl_ssi_remove,
1734 };
1735
1736 module_platform_driver(fsl_ssi_driver);
1737
1738 MODULE_ALIAS("platform:fsl-ssi-dai");
1739 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1740 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1741 MODULE_LICENSE("GPL v2");
1742