1 /*
2 * Helper routines for R-Car sound ADG.
3 *
4 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10 #include <linux/clk-provider.h>
11 #include "rsnd.h"
12
13 #define CLKA 0
14 #define CLKB 1
15 #define CLKC 2
16 #define CLKI 3
17 #define CLKMAX 4
18
19 #define CLKOUT 0
20 #define CLKOUT1 1
21 #define CLKOUT2 2
22 #define CLKOUT3 3
23 #define CLKOUTMAX 4
24
25 #define BRRx_MASK(x) (0x3FF & x)
26
27 static struct rsnd_mod_ops adg_ops = {
28 .name = "adg",
29 };
30
31 struct rsnd_adg {
32 struct clk *clk[CLKMAX];
33 struct clk *clkout[CLKOUTMAX];
34 struct clk_onecell_data onecell;
35 struct rsnd_mod mod;
36 int clk_rate[CLKMAX];
37 u32 flags;
38 u32 ckr;
39 u32 rbga;
40 u32 rbgb;
41
42 int rbga_rate_for_441khz; /* RBGA */
43 int rbgb_rate_for_48khz; /* RBGB */
44 };
45
46 #define LRCLK_ASYNC (1 << 0)
47 #define AUDIO_OUT_48 (1 << 1)
48 #define adg_mode_flags(adg) (adg->flags)
49
50 #define for_each_rsnd_clk(pos, adg, i) \
51 for (i = 0; \
52 (i < CLKMAX) && \
53 ((pos) = adg->clk[i]); \
54 i++)
55 #define for_each_rsnd_clkout(pos, adg, i) \
56 for (i = 0; \
57 (i < CLKOUTMAX) && \
58 ((pos) = adg->clkout[i]); \
59 i++)
60 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
61
rsnd_adg_calculate_rbgx(unsigned long div)62 static u32 rsnd_adg_calculate_rbgx(unsigned long div)
63 {
64 int i, ratio;
65
66 if (!div)
67 return 0;
68
69 for (i = 3; i >= 0; i--) {
70 ratio = 2 << (i * 2);
71 if (0 == (div % ratio))
72 return (u32)((i << 8) | ((div / ratio) - 1));
73 }
74
75 return ~0;
76 }
77
rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream * io)78 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
79 {
80 struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io);
81 int id = rsnd_mod_id(ssi_mod);
82 int ws = id;
83
84 if (rsnd_ssi_is_pin_sharing(io)) {
85 switch (id) {
86 case 1:
87 case 2:
88 ws = 0;
89 break;
90 case 4:
91 ws = 3;
92 break;
93 case 8:
94 ws = 7;
95 break;
96 }
97 }
98
99 return (0x6 + ws) << 8;
100 }
101
__rsnd_adg_get_timesel_ratio(struct rsnd_priv * priv,struct rsnd_dai_stream * io,unsigned int target_rate,unsigned int * target_val,unsigned int * target_en)102 static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
103 struct rsnd_dai_stream *io,
104 unsigned int target_rate,
105 unsigned int *target_val,
106 unsigned int *target_en)
107 {
108 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
109 struct device *dev = rsnd_priv_to_dev(priv);
110 int idx, sel, div, step;
111 unsigned int val, en;
112 unsigned int min, diff;
113 unsigned int sel_rate[] = {
114 adg->clk_rate[CLKA], /* 0000: CLKA */
115 adg->clk_rate[CLKB], /* 0001: CLKB */
116 adg->clk_rate[CLKC], /* 0010: CLKC */
117 adg->rbga_rate_for_441khz, /* 0011: RBGA */
118 adg->rbgb_rate_for_48khz, /* 0100: RBGB */
119 };
120
121 min = ~0;
122 val = 0;
123 en = 0;
124 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
125 idx = 0;
126 step = 2;
127
128 if (!sel_rate[sel])
129 continue;
130
131 for (div = 2; div <= 98304; div += step) {
132 diff = abs(target_rate - sel_rate[sel] / div);
133 if (min > diff) {
134 val = (sel << 8) | idx;
135 min = diff;
136 en = 1 << (sel + 1); /* fixme */
137 }
138
139 /*
140 * step of 0_0000 / 0_0001 / 0_1101
141 * are out of order
142 */
143 if ((idx > 2) && (idx % 2))
144 step *= 2;
145 if (idx == 0x1c) {
146 div += step;
147 step *= 2;
148 }
149 idx++;
150 }
151 }
152
153 if (min == ~0) {
154 dev_err(dev, "no Input clock\n");
155 return;
156 }
157
158 *target_val = val;
159 if (target_en)
160 *target_en = en;
161 }
162
rsnd_adg_get_timesel_ratio(struct rsnd_priv * priv,struct rsnd_dai_stream * io,unsigned int in_rate,unsigned int out_rate,u32 * in,u32 * out,u32 * en)163 static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
164 struct rsnd_dai_stream *io,
165 unsigned int in_rate,
166 unsigned int out_rate,
167 u32 *in, u32 *out, u32 *en)
168 {
169 struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
170 unsigned int target_rate;
171 u32 *target_val;
172 u32 _in;
173 u32 _out;
174 u32 _en;
175
176 /* default = SSI WS */
177 _in =
178 _out = rsnd_adg_ssi_ws_timing_gen2(io);
179
180 target_rate = 0;
181 target_val = NULL;
182 _en = 0;
183 if (runtime->rate != in_rate) {
184 target_rate = out_rate;
185 target_val = &_out;
186 } else if (runtime->rate != out_rate) {
187 target_rate = in_rate;
188 target_val = &_in;
189 }
190
191 if (target_rate)
192 __rsnd_adg_get_timesel_ratio(priv, io,
193 target_rate,
194 target_val, &_en);
195
196 if (in)
197 *in = _in;
198 if (out)
199 *out = _out;
200 if (en)
201 *en = _en;
202 }
203
rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod * cmd_mod,struct rsnd_dai_stream * io)204 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod,
205 struct rsnd_dai_stream *io)
206 {
207 struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod);
208 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
209 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
210 int id = rsnd_mod_id(cmd_mod);
211 int shift = (id % 2) ? 16 : 0;
212 u32 mask, val;
213
214 rsnd_adg_get_timesel_ratio(priv, io,
215 rsnd_src_get_in_rate(priv, io),
216 rsnd_src_get_out_rate(priv, io),
217 NULL, &val, NULL);
218
219 val = val << shift;
220 mask = 0x0f1f << shift;
221
222 rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val);
223
224 return 0;
225 }
226
rsnd_adg_set_src_timesel_gen2(struct rsnd_mod * src_mod,struct rsnd_dai_stream * io,unsigned int in_rate,unsigned int out_rate)227 int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod,
228 struct rsnd_dai_stream *io,
229 unsigned int in_rate,
230 unsigned int out_rate)
231 {
232 struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
233 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
234 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
235 u32 in, out;
236 u32 mask, en;
237 int id = rsnd_mod_id(src_mod);
238 int shift = (id % 2) ? 16 : 0;
239
240 rsnd_mod_confirm_src(src_mod);
241
242 rsnd_adg_get_timesel_ratio(priv, io,
243 in_rate, out_rate,
244 &in, &out, &en);
245
246 in = in << shift;
247 out = out << shift;
248 mask = 0x0f1f << shift;
249
250 switch (id / 2) {
251 case 0:
252 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL0, mask, in);
253 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL0, mask, out);
254 break;
255 case 1:
256 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL1, mask, in);
257 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL1, mask, out);
258 break;
259 case 2:
260 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL2, mask, in);
261 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL2, mask, out);
262 break;
263 case 3:
264 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL3, mask, in);
265 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL3, mask, out);
266 break;
267 case 4:
268 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL4, mask, in);
269 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL4, mask, out);
270 break;
271 }
272
273 if (en)
274 rsnd_mod_bset(adg_mod, DIV_EN, en, en);
275
276 return 0;
277 }
278
rsnd_adg_set_ssi_clk(struct rsnd_mod * ssi_mod,u32 val)279 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
280 {
281 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
282 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
283 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
284 int id = rsnd_mod_id(ssi_mod);
285 int shift = (id % 4) * 8;
286 u32 mask = 0xFF << shift;
287
288 rsnd_mod_confirm_ssi(ssi_mod);
289
290 val = val << shift;
291
292 /*
293 * SSI 8 is not connected to ADG.
294 * it works with SSI 7
295 */
296 if (id == 8)
297 return;
298
299 switch (id / 4) {
300 case 0:
301 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL0, mask, val);
302 break;
303 case 1:
304 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL1, mask, val);
305 break;
306 case 2:
307 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL2, mask, val);
308 break;
309 }
310 }
311
rsnd_adg_clk_query(struct rsnd_priv * priv,unsigned int rate)312 int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate)
313 {
314 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
315 struct device *dev = rsnd_priv_to_dev(priv);
316 struct clk *clk;
317 int i;
318 int sel_table[] = {
319 [CLKA] = 0x1,
320 [CLKB] = 0x2,
321 [CLKC] = 0x3,
322 [CLKI] = 0x0,
323 };
324
325 dev_dbg(dev, "request clock = %d\n", rate);
326
327 /*
328 * find suitable clock from
329 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
330 */
331 for_each_rsnd_clk(clk, adg, i) {
332 if (rate == adg->clk_rate[i])
333 return sel_table[i];
334 }
335
336 /*
337 * find divided clock from BRGA/BRGB
338 */
339 if (rate == adg->rbga_rate_for_441khz)
340 return 0x10;
341
342 if (rate == adg->rbgb_rate_for_48khz)
343 return 0x20;
344
345 return -EIO;
346 }
347
rsnd_adg_ssi_clk_stop(struct rsnd_mod * ssi_mod)348 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod)
349 {
350 rsnd_adg_set_ssi_clk(ssi_mod, 0);
351
352 return 0;
353 }
354
rsnd_adg_ssi_clk_try_start(struct rsnd_mod * ssi_mod,unsigned int rate)355 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate)
356 {
357 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
358 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
359 struct device *dev = rsnd_priv_to_dev(priv);
360 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
361 int data;
362 u32 ckr = 0;
363
364 data = rsnd_adg_clk_query(priv, rate);
365 if (data < 0)
366 return data;
367
368 rsnd_adg_set_ssi_clk(ssi_mod, data);
369
370 if (adg_mode_flags(adg) & LRCLK_ASYNC) {
371 if (adg_mode_flags(adg) & AUDIO_OUT_48)
372 ckr = 0x80000000;
373 } else {
374 if (0 == (rate % 8000))
375 ckr = 0x80000000;
376 }
377
378 rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr | ckr);
379 rsnd_mod_write(adg_mod, BRRA, adg->rbga);
380 rsnd_mod_write(adg_mod, BRRB, adg->rbgb);
381
382 dev_dbg(dev, "ADG: %s[%d] selects 0x%x for %d\n",
383 rsnd_mod_name(ssi_mod), rsnd_mod_id(ssi_mod),
384 data, rate);
385
386 return 0;
387 }
388
rsnd_adg_clk_control(struct rsnd_priv * priv,int enable)389 void rsnd_adg_clk_control(struct rsnd_priv *priv, int enable)
390 {
391 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
392 struct device *dev = rsnd_priv_to_dev(priv);
393 struct clk *clk;
394 int i, ret;
395
396 for_each_rsnd_clk(clk, adg, i) {
397 ret = 0;
398 if (enable) {
399 ret = clk_prepare_enable(clk);
400
401 /*
402 * We shouldn't use clk_get_rate() under
403 * atomic context. Let's keep it when
404 * rsnd_adg_clk_enable() was called
405 */
406 adg->clk_rate[i] = clk_get_rate(adg->clk[i]);
407 } else {
408 clk_disable_unprepare(clk);
409 }
410
411 if (ret < 0)
412 dev_warn(dev, "can't use clk %d\n", i);
413 }
414 }
415
rsnd_adg_get_clkin(struct rsnd_priv * priv,struct rsnd_adg * adg)416 static void rsnd_adg_get_clkin(struct rsnd_priv *priv,
417 struct rsnd_adg *adg)
418 {
419 struct device *dev = rsnd_priv_to_dev(priv);
420 struct clk *clk;
421 static const char * const clk_name[] = {
422 [CLKA] = "clk_a",
423 [CLKB] = "clk_b",
424 [CLKC] = "clk_c",
425 [CLKI] = "clk_i",
426 };
427 int i;
428
429 for (i = 0; i < CLKMAX; i++) {
430 clk = devm_clk_get(dev, clk_name[i]);
431 adg->clk[i] = IS_ERR(clk) ? NULL : clk;
432 }
433
434 for_each_rsnd_clk(clk, adg, i)
435 dev_dbg(dev, "clk %d : %p : %ld\n", i, clk, clk_get_rate(clk));
436 }
437
rsnd_adg_get_clkout(struct rsnd_priv * priv,struct rsnd_adg * adg)438 static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
439 struct rsnd_adg *adg)
440 {
441 struct clk *clk;
442 struct device *dev = rsnd_priv_to_dev(priv);
443 struct device_node *np = dev->of_node;
444 struct property *prop;
445 u32 ckr, rbgx, rbga, rbgb;
446 u32 rate, div;
447 #define REQ_SIZE 2
448 u32 req_rate[REQ_SIZE] = {};
449 uint32_t count = 0;
450 unsigned long req_48kHz_rate, req_441kHz_rate;
451 int i, req_size;
452 const char *parent_clk_name = NULL;
453 static const char * const clkout_name[] = {
454 [CLKOUT] = "audio_clkout",
455 [CLKOUT1] = "audio_clkout1",
456 [CLKOUT2] = "audio_clkout2",
457 [CLKOUT3] = "audio_clkout3",
458 };
459 int brg_table[] = {
460 [CLKA] = 0x0,
461 [CLKB] = 0x1,
462 [CLKC] = 0x4,
463 [CLKI] = 0x2,
464 };
465
466 ckr = 0;
467 rbga = 2; /* default 1/6 */
468 rbgb = 2; /* default 1/6 */
469
470 /*
471 * ADG supports BRRA/BRRB output only
472 * this means all clkout0/1/2/3 will be same rate
473 */
474 prop = of_find_property(np, "clock-frequency", NULL);
475 if (!prop)
476 goto rsnd_adg_get_clkout_end;
477
478 req_size = prop->length / sizeof(u32);
479 if (req_size > REQ_SIZE) {
480 dev_err(dev,
481 "too many clock-frequency, use top %d\n", REQ_SIZE);
482 req_size = REQ_SIZE;
483 }
484
485 of_property_read_u32_array(np, "clock-frequency", req_rate, req_size);
486 req_48kHz_rate = 0;
487 req_441kHz_rate = 0;
488 for (i = 0; i < req_size; i++) {
489 if (0 == (req_rate[i] % 44100))
490 req_441kHz_rate = req_rate[i];
491 if (0 == (req_rate[i] % 48000))
492 req_48kHz_rate = req_rate[i];
493 }
494
495 if (req_rate[0] % 48000 == 0)
496 adg->flags |= AUDIO_OUT_48;
497
498 if (of_get_property(np, "clkout-lr-asynchronous", NULL))
499 adg->flags |= LRCLK_ASYNC;
500
501 /*
502 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
503 * have 44.1kHz or 48kHz base clocks for now.
504 *
505 * SSI itself can divide parent clock by 1/1 - 1/16
506 * see
507 * rsnd_adg_ssi_clk_try_start()
508 * rsnd_ssi_master_clk_start()
509 */
510 adg->rbga_rate_for_441khz = 0;
511 adg->rbgb_rate_for_48khz = 0;
512 for_each_rsnd_clk(clk, adg, i) {
513 rate = clk_get_rate(clk);
514
515 if (0 == rate) /* not used */
516 continue;
517
518 /* RBGA */
519 if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) {
520 div = 6;
521 if (req_441kHz_rate)
522 div = rate / req_441kHz_rate;
523 rbgx = rsnd_adg_calculate_rbgx(div);
524 if (BRRx_MASK(rbgx) == rbgx) {
525 rbga = rbgx;
526 adg->rbga_rate_for_441khz = rate / div;
527 ckr |= brg_table[i] << 20;
528 if (req_441kHz_rate &&
529 !(adg_mode_flags(adg) & AUDIO_OUT_48))
530 parent_clk_name = __clk_get_name(clk);
531 }
532 }
533
534 /* RBGB */
535 if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) {
536 div = 6;
537 if (req_48kHz_rate)
538 div = rate / req_48kHz_rate;
539 rbgx = rsnd_adg_calculate_rbgx(div);
540 if (BRRx_MASK(rbgx) == rbgx) {
541 rbgb = rbgx;
542 adg->rbgb_rate_for_48khz = rate / div;
543 ckr |= brg_table[i] << 16;
544 if (req_48kHz_rate &&
545 (adg_mode_flags(adg) & AUDIO_OUT_48))
546 parent_clk_name = __clk_get_name(clk);
547 }
548 }
549 }
550
551 /*
552 * ADG supports BRRA/BRRB output only.
553 * this means all clkout0/1/2/3 will be * same rate
554 */
555
556 of_property_read_u32(np, "#clock-cells", &count);
557 /*
558 * for clkout
559 */
560 if (!count) {
561 clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT],
562 parent_clk_name, 0, req_rate[0]);
563 if (!IS_ERR(clk)) {
564 adg->clkout[CLKOUT] = clk;
565 of_clk_add_provider(np, of_clk_src_simple_get, clk);
566 }
567 }
568 /*
569 * for clkout0/1/2/3
570 */
571 else {
572 for (i = 0; i < CLKOUTMAX; i++) {
573 clk = clk_register_fixed_rate(dev, clkout_name[i],
574 parent_clk_name, 0,
575 req_rate[0]);
576 if (!IS_ERR(clk))
577 adg->clkout[i] = clk;
578 }
579 adg->onecell.clks = adg->clkout;
580 adg->onecell.clk_num = CLKOUTMAX;
581 of_clk_add_provider(np, of_clk_src_onecell_get,
582 &adg->onecell);
583 }
584
585 rsnd_adg_get_clkout_end:
586 adg->ckr = ckr;
587 adg->rbga = rbga;
588 adg->rbgb = rbgb;
589
590 for_each_rsnd_clkout(clk, adg, i)
591 dev_dbg(dev, "clkout %d : %p : %ld\n", i, clk, clk_get_rate(clk));
592 dev_dbg(dev, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
593 ckr, rbga, rbgb);
594 }
595
rsnd_adg_probe(struct rsnd_priv * priv)596 int rsnd_adg_probe(struct rsnd_priv *priv)
597 {
598 struct rsnd_adg *adg;
599 struct device *dev = rsnd_priv_to_dev(priv);
600 int ret;
601
602 adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
603 if (!adg)
604 return -ENOMEM;
605
606 ret = rsnd_mod_init(priv, &adg->mod, &adg_ops,
607 NULL, NULL, 0, 0);
608 if (ret)
609 return ret;
610
611 rsnd_adg_get_clkin(priv, adg);
612 rsnd_adg_get_clkout(priv, adg);
613
614 priv->adg = adg;
615
616 rsnd_adg_clk_enable(priv);
617
618 return 0;
619 }
620
rsnd_adg_remove(struct rsnd_priv * priv)621 void rsnd_adg_remove(struct rsnd_priv *priv)
622 {
623 struct device *dev = rsnd_priv_to_dev(priv);
624 struct device_node *np = dev->of_node;
625 struct rsnd_adg *adg = priv->adg;
626 struct clk *clk;
627 int i;
628
629 for_each_rsnd_clkout(clk, adg, i)
630 if (adg->clkout[i])
631 clk_unregister_fixed_rate(adg->clkout[i]);
632
633 of_clk_del_provider(np);
634
635 rsnd_adg_clk_disable(priv);
636 }
637