1 /*
2 * STM32 ALSA SoC Digital Audio Interface (SPDIF-rx) driver.
3 *
4 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
5 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
6 *
7 * License terms: GPL V2.0.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
16 * details.
17 */
18
19 #include <linux/clk.h>
20 #include <linux/completion.h>
21 #include <linux/delay.h>
22 #include <linux/module.h>
23 #include <linux/of_platform.h>
24 #include <linux/regmap.h>
25 #include <linux/reset.h>
26
27 #include <sound/dmaengine_pcm.h>
28 #include <sound/pcm_params.h>
29
30 /* SPDIF-rx Register Map */
31 #define STM32_SPDIFRX_CR 0x00
32 #define STM32_SPDIFRX_IMR 0x04
33 #define STM32_SPDIFRX_SR 0x08
34 #define STM32_SPDIFRX_IFCR 0x0C
35 #define STM32_SPDIFRX_DR 0x10
36 #define STM32_SPDIFRX_CSR 0x14
37 #define STM32_SPDIFRX_DIR 0x18
38
39 /* Bit definition for SPDIF_CR register */
40 #define SPDIFRX_CR_SPDIFEN_SHIFT 0
41 #define SPDIFRX_CR_SPDIFEN_MASK GENMASK(1, SPDIFRX_CR_SPDIFEN_SHIFT)
42 #define SPDIFRX_CR_SPDIFENSET(x) ((x) << SPDIFRX_CR_SPDIFEN_SHIFT)
43
44 #define SPDIFRX_CR_RXDMAEN BIT(2)
45 #define SPDIFRX_CR_RXSTEO BIT(3)
46
47 #define SPDIFRX_CR_DRFMT_SHIFT 4
48 #define SPDIFRX_CR_DRFMT_MASK GENMASK(5, SPDIFRX_CR_DRFMT_SHIFT)
49 #define SPDIFRX_CR_DRFMTSET(x) ((x) << SPDIFRX_CR_DRFMT_SHIFT)
50
51 #define SPDIFRX_CR_PMSK BIT(6)
52 #define SPDIFRX_CR_VMSK BIT(7)
53 #define SPDIFRX_CR_CUMSK BIT(8)
54 #define SPDIFRX_CR_PTMSK BIT(9)
55 #define SPDIFRX_CR_CBDMAEN BIT(10)
56 #define SPDIFRX_CR_CHSEL_SHIFT 11
57 #define SPDIFRX_CR_CHSEL BIT(SPDIFRX_CR_CHSEL_SHIFT)
58
59 #define SPDIFRX_CR_NBTR_SHIFT 12
60 #define SPDIFRX_CR_NBTR_MASK GENMASK(13, SPDIFRX_CR_NBTR_SHIFT)
61 #define SPDIFRX_CR_NBTRSET(x) ((x) << SPDIFRX_CR_NBTR_SHIFT)
62
63 #define SPDIFRX_CR_WFA BIT(14)
64
65 #define SPDIFRX_CR_INSEL_SHIFT 16
66 #define SPDIFRX_CR_INSEL_MASK GENMASK(18, PDIFRX_CR_INSEL_SHIFT)
67 #define SPDIFRX_CR_INSELSET(x) ((x) << SPDIFRX_CR_INSEL_SHIFT)
68
69 #define SPDIFRX_CR_CKSEN_SHIFT 20
70 #define SPDIFRX_CR_CKSEN BIT(20)
71 #define SPDIFRX_CR_CKSBKPEN BIT(21)
72
73 /* Bit definition for SPDIFRX_IMR register */
74 #define SPDIFRX_IMR_RXNEI BIT(0)
75 #define SPDIFRX_IMR_CSRNEIE BIT(1)
76 #define SPDIFRX_IMR_PERRIE BIT(2)
77 #define SPDIFRX_IMR_OVRIE BIT(3)
78 #define SPDIFRX_IMR_SBLKIE BIT(4)
79 #define SPDIFRX_IMR_SYNCDIE BIT(5)
80 #define SPDIFRX_IMR_IFEIE BIT(6)
81
82 #define SPDIFRX_XIMR_MASK GENMASK(6, 0)
83
84 /* Bit definition for SPDIFRX_SR register */
85 #define SPDIFRX_SR_RXNE BIT(0)
86 #define SPDIFRX_SR_CSRNE BIT(1)
87 #define SPDIFRX_SR_PERR BIT(2)
88 #define SPDIFRX_SR_OVR BIT(3)
89 #define SPDIFRX_SR_SBD BIT(4)
90 #define SPDIFRX_SR_SYNCD BIT(5)
91 #define SPDIFRX_SR_FERR BIT(6)
92 #define SPDIFRX_SR_SERR BIT(7)
93 #define SPDIFRX_SR_TERR BIT(8)
94
95 #define SPDIFRX_SR_WIDTH5_SHIFT 16
96 #define SPDIFRX_SR_WIDTH5_MASK GENMASK(30, PDIFRX_SR_WIDTH5_SHIFT)
97 #define SPDIFRX_SR_WIDTH5SET(x) ((x) << SPDIFRX_SR_WIDTH5_SHIFT)
98
99 /* Bit definition for SPDIFRX_IFCR register */
100 #define SPDIFRX_IFCR_PERRCF BIT(2)
101 #define SPDIFRX_IFCR_OVRCF BIT(3)
102 #define SPDIFRX_IFCR_SBDCF BIT(4)
103 #define SPDIFRX_IFCR_SYNCDCF BIT(5)
104
105 #define SPDIFRX_XIFCR_MASK GENMASK(5, 2)
106
107 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b00) */
108 #define SPDIFRX_DR0_DR_SHIFT 0
109 #define SPDIFRX_DR0_DR_MASK GENMASK(23, SPDIFRX_DR0_DR_SHIFT)
110 #define SPDIFRX_DR0_DRSET(x) ((x) << SPDIFRX_DR0_DR_SHIFT)
111
112 #define SPDIFRX_DR0_PE BIT(24)
113
114 #define SPDIFRX_DR0_V BIT(25)
115 #define SPDIFRX_DR0_U BIT(26)
116 #define SPDIFRX_DR0_C BIT(27)
117
118 #define SPDIFRX_DR0_PT_SHIFT 28
119 #define SPDIFRX_DR0_PT_MASK GENMASK(29, SPDIFRX_DR0_PT_SHIFT)
120 #define SPDIFRX_DR0_PTSET(x) ((x) << SPDIFRX_DR0_PT_SHIFT)
121
122 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b01) */
123 #define SPDIFRX_DR1_PE BIT(0)
124 #define SPDIFRX_DR1_V BIT(1)
125 #define SPDIFRX_DR1_U BIT(2)
126 #define SPDIFRX_DR1_C BIT(3)
127
128 #define SPDIFRX_DR1_PT_SHIFT 4
129 #define SPDIFRX_DR1_PT_MASK GENMASK(5, SPDIFRX_DR1_PT_SHIFT)
130 #define SPDIFRX_DR1_PTSET(x) ((x) << SPDIFRX_DR1_PT_SHIFT)
131
132 #define SPDIFRX_DR1_DR_SHIFT 8
133 #define SPDIFRX_DR1_DR_MASK GENMASK(31, SPDIFRX_DR1_DR_SHIFT)
134 #define SPDIFRX_DR1_DRSET(x) ((x) << SPDIFRX_DR1_DR_SHIFT)
135
136 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b10) */
137 #define SPDIFRX_DR1_DRNL1_SHIFT 0
138 #define SPDIFRX_DR1_DRNL1_MASK GENMASK(15, SPDIFRX_DR1_DRNL1_SHIFT)
139 #define SPDIFRX_DR1_DRNL1SET(x) ((x) << SPDIFRX_DR1_DRNL1_SHIFT)
140
141 #define SPDIFRX_DR1_DRNL2_SHIFT 16
142 #define SPDIFRX_DR1_DRNL2_MASK GENMASK(31, SPDIFRX_DR1_DRNL2_SHIFT)
143 #define SPDIFRX_DR1_DRNL2SET(x) ((x) << SPDIFRX_DR1_DRNL2_SHIFT)
144
145 /* Bit definition for SPDIFRX_CSR register */
146 #define SPDIFRX_CSR_USR_SHIFT 0
147 #define SPDIFRX_CSR_USR_MASK GENMASK(15, SPDIFRX_CSR_USR_SHIFT)
148 #define SPDIFRX_CSR_USRGET(x) (((x) & SPDIFRX_CSR_USR_MASK)\
149 >> SPDIFRX_CSR_USR_SHIFT)
150
151 #define SPDIFRX_CSR_CS_SHIFT 16
152 #define SPDIFRX_CSR_CS_MASK GENMASK(23, SPDIFRX_CSR_CS_SHIFT)
153 #define SPDIFRX_CSR_CSGET(x) (((x) & SPDIFRX_CSR_CS_MASK)\
154 >> SPDIFRX_CSR_CS_SHIFT)
155
156 #define SPDIFRX_CSR_SOB BIT(24)
157
158 /* Bit definition for SPDIFRX_DIR register */
159 #define SPDIFRX_DIR_THI_SHIFT 0
160 #define SPDIFRX_DIR_THI_MASK GENMASK(12, SPDIFRX_DIR_THI_SHIFT)
161 #define SPDIFRX_DIR_THI_SET(x) ((x) << SPDIFRX_DIR_THI_SHIFT)
162
163 #define SPDIFRX_DIR_TLO_SHIFT 16
164 #define SPDIFRX_DIR_TLO_MASK GENMASK(28, SPDIFRX_DIR_TLO_SHIFT)
165 #define SPDIFRX_DIR_TLO_SET(x) ((x) << SPDIFRX_DIR_TLO_SHIFT)
166
167 #define SPDIFRX_SPDIFEN_DISABLE 0x0
168 #define SPDIFRX_SPDIFEN_SYNC 0x1
169 #define SPDIFRX_SPDIFEN_ENABLE 0x3
170
171 #define SPDIFRX_IN1 0x1
172 #define SPDIFRX_IN2 0x2
173 #define SPDIFRX_IN3 0x3
174 #define SPDIFRX_IN4 0x4
175 #define SPDIFRX_IN5 0x5
176 #define SPDIFRX_IN6 0x6
177 #define SPDIFRX_IN7 0x7
178 #define SPDIFRX_IN8 0x8
179
180 #define SPDIFRX_NBTR_NONE 0x0
181 #define SPDIFRX_NBTR_3 0x1
182 #define SPDIFRX_NBTR_15 0x2
183 #define SPDIFRX_NBTR_63 0x3
184
185 #define SPDIFRX_DRFMT_RIGHT 0x0
186 #define SPDIFRX_DRFMT_LEFT 0x1
187 #define SPDIFRX_DRFMT_PACKED 0x2
188
189 /* 192 CS bits in S/PDIF frame. i.e 24 CS bytes */
190 #define SPDIFRX_CS_BYTES_NB 24
191 #define SPDIFRX_UB_BYTES_NB 48
192
193 /*
194 * CSR register is retrieved as a 32 bits word
195 * It contains 1 channel status byte and 2 user data bytes
196 * 2 S/PDIF frames are acquired to get all CS/UB bits
197 */
198 #define SPDIFRX_CSR_BUF_LENGTH (SPDIFRX_CS_BYTES_NB * 4 * 2)
199
200 /**
201 * struct stm32_spdifrx_data - private data of SPDIFRX
202 * @pdev: device data pointer
203 * @base: mmio register base virtual address
204 * @regmap: SPDIFRX register map pointer
205 * @regmap_conf: SPDIFRX register map configuration pointer
206 * @cs_completion: channel status retrieving completion
207 * @kclk: kernel clock feeding the SPDIFRX clock generator
208 * @dma_params: dma configuration data for rx channel
209 * @substream: PCM substream data pointer
210 * @dmab: dma buffer info pointer
211 * @ctrl_chan: dma channel for S/PDIF control bits
212 * @desc:dma async transaction descriptor
213 * @slave_config: dma slave channel runtime config pointer
214 * @phys_addr: SPDIFRX registers physical base address
215 * @lock: synchronization enabling lock
216 * @irq_lock: prevent race condition with IRQ on stream state
217 * @cs: channel status buffer
218 * @ub: user data buffer
219 * @irq: SPDIFRX interrupt line
220 * @refcount: keep count of opened DMA channels
221 */
222 struct stm32_spdifrx_data {
223 struct platform_device *pdev;
224 void __iomem *base;
225 struct regmap *regmap;
226 const struct regmap_config *regmap_conf;
227 struct completion cs_completion;
228 struct clk *kclk;
229 struct snd_dmaengine_dai_dma_data dma_params;
230 struct snd_pcm_substream *substream;
231 struct snd_dma_buffer *dmab;
232 struct dma_chan *ctrl_chan;
233 struct dma_async_tx_descriptor *desc;
234 struct dma_slave_config slave_config;
235 dma_addr_t phys_addr;
236 spinlock_t lock; /* Sync enabling lock */
237 spinlock_t irq_lock; /* Prevent race condition on stream state */
238 unsigned char cs[SPDIFRX_CS_BYTES_NB];
239 unsigned char ub[SPDIFRX_UB_BYTES_NB];
240 int irq;
241 int refcount;
242 };
243
stm32_spdifrx_dma_complete(void * data)244 static void stm32_spdifrx_dma_complete(void *data)
245 {
246 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)data;
247 struct platform_device *pdev = spdifrx->pdev;
248 u32 *p_start = (u32 *)spdifrx->dmab->area;
249 u32 *p_end = p_start + (2 * SPDIFRX_CS_BYTES_NB) - 1;
250 u32 *ptr = p_start;
251 u16 *ub_ptr = (short *)spdifrx->ub;
252 int i = 0;
253
254 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
255 SPDIFRX_CR_CBDMAEN,
256 (unsigned int)~SPDIFRX_CR_CBDMAEN);
257
258 if (!spdifrx->dmab->area)
259 return;
260
261 while (ptr <= p_end) {
262 if (*ptr & SPDIFRX_CSR_SOB)
263 break;
264 ptr++;
265 }
266
267 if (ptr > p_end) {
268 dev_err(&pdev->dev, "Start of S/PDIF block not found\n");
269 return;
270 }
271
272 while (i < SPDIFRX_CS_BYTES_NB) {
273 spdifrx->cs[i] = (unsigned char)SPDIFRX_CSR_CSGET(*ptr);
274 *ub_ptr++ = SPDIFRX_CSR_USRGET(*ptr++);
275 if (ptr > p_end) {
276 dev_err(&pdev->dev, "Failed to get channel status\n");
277 return;
278 }
279 i++;
280 }
281
282 complete(&spdifrx->cs_completion);
283 }
284
stm32_spdifrx_dma_ctrl_start(struct stm32_spdifrx_data * spdifrx)285 static int stm32_spdifrx_dma_ctrl_start(struct stm32_spdifrx_data *spdifrx)
286 {
287 dma_cookie_t cookie;
288 int err;
289
290 spdifrx->desc = dmaengine_prep_slave_single(spdifrx->ctrl_chan,
291 spdifrx->dmab->addr,
292 SPDIFRX_CSR_BUF_LENGTH,
293 DMA_DEV_TO_MEM,
294 DMA_CTRL_ACK);
295 if (!spdifrx->desc)
296 return -EINVAL;
297
298 spdifrx->desc->callback = stm32_spdifrx_dma_complete;
299 spdifrx->desc->callback_param = spdifrx;
300 cookie = dmaengine_submit(spdifrx->desc);
301 err = dma_submit_error(cookie);
302 if (err)
303 return -EINVAL;
304
305 dma_async_issue_pending(spdifrx->ctrl_chan);
306
307 return 0;
308 }
309
stm32_spdifrx_dma_ctrl_stop(struct stm32_spdifrx_data * spdifrx)310 static void stm32_spdifrx_dma_ctrl_stop(struct stm32_spdifrx_data *spdifrx)
311 {
312 dmaengine_terminate_async(spdifrx->ctrl_chan);
313 }
314
stm32_spdifrx_start_sync(struct stm32_spdifrx_data * spdifrx)315 static int stm32_spdifrx_start_sync(struct stm32_spdifrx_data *spdifrx)
316 {
317 int cr, cr_mask, imr, ret;
318 unsigned long flags;
319
320 /* Enable IRQs */
321 imr = SPDIFRX_IMR_IFEIE | SPDIFRX_IMR_SYNCDIE | SPDIFRX_IMR_PERRIE;
322 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, imr, imr);
323 if (ret)
324 return ret;
325
326 spin_lock_irqsave(&spdifrx->lock, flags);
327
328 spdifrx->refcount++;
329
330 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr);
331
332 if (!(cr & SPDIFRX_CR_SPDIFEN_MASK)) {
333 /*
334 * Start sync if SPDIFRX is still in idle state.
335 * SPDIFRX reception enabled when sync done
336 */
337 dev_dbg(&spdifrx->pdev->dev, "start synchronization\n");
338
339 /*
340 * SPDIFRX configuration:
341 * Wait for activity before starting sync process. This avoid
342 * to issue sync errors when spdif signal is missing on input.
343 * Preamble, CS, user, validity and parity error bits not copied
344 * to DR register.
345 */
346 cr = SPDIFRX_CR_WFA | SPDIFRX_CR_PMSK | SPDIFRX_CR_VMSK |
347 SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK | SPDIFRX_CR_RXSTEO;
348 cr_mask = cr;
349
350 cr |= SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC);
351 cr_mask |= SPDIFRX_CR_SPDIFEN_MASK;
352 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
353 cr_mask, cr);
354 if (ret < 0)
355 dev_err(&spdifrx->pdev->dev,
356 "Failed to start synchronization\n");
357 }
358
359 spin_unlock_irqrestore(&spdifrx->lock, flags);
360
361 return ret;
362 }
363
stm32_spdifrx_stop(struct stm32_spdifrx_data * spdifrx)364 static void stm32_spdifrx_stop(struct stm32_spdifrx_data *spdifrx)
365 {
366 int cr, cr_mask, reg;
367 unsigned long flags;
368
369 spin_lock_irqsave(&spdifrx->lock, flags);
370
371 if (--spdifrx->refcount) {
372 spin_unlock_irqrestore(&spdifrx->lock, flags);
373 return;
374 }
375
376 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE);
377 cr_mask = SPDIFRX_CR_SPDIFEN_MASK | SPDIFRX_CR_RXDMAEN;
378
379 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, cr_mask, cr);
380
381 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR,
382 SPDIFRX_XIMR_MASK, 0);
383
384 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR,
385 SPDIFRX_XIFCR_MASK, SPDIFRX_XIFCR_MASK);
386
387 /* dummy read to clear CSRNE and RXNE in status register */
388 regmap_read(spdifrx->regmap, STM32_SPDIFRX_DR, ®);
389 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CSR, ®);
390
391 spin_unlock_irqrestore(&spdifrx->lock, flags);
392 }
393
stm32_spdifrx_dma_ctrl_register(struct device * dev,struct stm32_spdifrx_data * spdifrx)394 static int stm32_spdifrx_dma_ctrl_register(struct device *dev,
395 struct stm32_spdifrx_data *spdifrx)
396 {
397 int ret;
398
399 spdifrx->dmab = devm_kzalloc(dev, sizeof(struct snd_dma_buffer),
400 GFP_KERNEL);
401 if (!spdifrx->dmab)
402 return -ENOMEM;
403
404 spdifrx->dmab->dev.type = SNDRV_DMA_TYPE_DEV_IRAM;
405 spdifrx->dmab->dev.dev = dev;
406 ret = snd_dma_alloc_pages(spdifrx->dmab->dev.type, dev,
407 SPDIFRX_CSR_BUF_LENGTH, spdifrx->dmab);
408 if (ret < 0) {
409 dev_err(dev, "snd_dma_alloc_pages returned error %d\n", ret);
410 return ret;
411 }
412
413 spdifrx->ctrl_chan = dma_request_chan(dev, "rx-ctrl");
414 if (!spdifrx->ctrl_chan) {
415 dev_err(dev, "dma_request_slave_channel failed\n");
416 return -EINVAL;
417 }
418
419 spdifrx->slave_config.direction = DMA_DEV_TO_MEM;
420 spdifrx->slave_config.src_addr = (dma_addr_t)(spdifrx->phys_addr +
421 STM32_SPDIFRX_CSR);
422 spdifrx->slave_config.dst_addr = spdifrx->dmab->addr;
423 spdifrx->slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
424 spdifrx->slave_config.src_maxburst = 1;
425
426 ret = dmaengine_slave_config(spdifrx->ctrl_chan,
427 &spdifrx->slave_config);
428 if (ret < 0) {
429 dev_err(dev, "dmaengine_slave_config returned error %d\n", ret);
430 dma_release_channel(spdifrx->ctrl_chan);
431 spdifrx->ctrl_chan = NULL;
432 }
433
434 return ret;
435 };
436
437 static const char * const spdifrx_enum_input[] = {
438 "in0", "in1", "in2", "in3"
439 };
440
441 /* By default CS bits are retrieved from channel A */
442 static const char * const spdifrx_enum_cs_channel[] = {
443 "A", "B"
444 };
445
446 static SOC_ENUM_SINGLE_DECL(ctrl_enum_input,
447 STM32_SPDIFRX_CR, SPDIFRX_CR_INSEL_SHIFT,
448 spdifrx_enum_input);
449
450 static SOC_ENUM_SINGLE_DECL(ctrl_enum_cs_channel,
451 STM32_SPDIFRX_CR, SPDIFRX_CR_CHSEL_SHIFT,
452 spdifrx_enum_cs_channel);
453
stm32_spdifrx_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)454 static int stm32_spdifrx_info(struct snd_kcontrol *kcontrol,
455 struct snd_ctl_elem_info *uinfo)
456 {
457 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
458 uinfo->count = 1;
459
460 return 0;
461 }
462
stm32_spdifrx_ub_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)463 static int stm32_spdifrx_ub_info(struct snd_kcontrol *kcontrol,
464 struct snd_ctl_elem_info *uinfo)
465 {
466 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
467 uinfo->count = 1;
468
469 return 0;
470 }
471
stm32_spdifrx_get_ctrl_data(struct stm32_spdifrx_data * spdifrx)472 static int stm32_spdifrx_get_ctrl_data(struct stm32_spdifrx_data *spdifrx)
473 {
474 int ret = 0;
475
476 memset(spdifrx->cs, 0, SPDIFRX_CS_BYTES_NB);
477 memset(spdifrx->ub, 0, SPDIFRX_UB_BYTES_NB);
478
479 ret = stm32_spdifrx_dma_ctrl_start(spdifrx);
480 if (ret < 0)
481 return ret;
482
483 ret = clk_prepare_enable(spdifrx->kclk);
484 if (ret) {
485 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret);
486 return ret;
487 }
488
489 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
490 SPDIFRX_CR_CBDMAEN, SPDIFRX_CR_CBDMAEN);
491 if (ret < 0)
492 goto end;
493
494 ret = stm32_spdifrx_start_sync(spdifrx);
495 if (ret < 0)
496 goto end;
497
498 if (wait_for_completion_interruptible_timeout(&spdifrx->cs_completion,
499 msecs_to_jiffies(100))
500 <= 0) {
501 dev_err(&spdifrx->pdev->dev, "Failed to get control data\n");
502 ret = -EAGAIN;
503 }
504
505 stm32_spdifrx_stop(spdifrx);
506 stm32_spdifrx_dma_ctrl_stop(spdifrx);
507
508 end:
509 clk_disable_unprepare(spdifrx->kclk);
510
511 return ret;
512 }
513
stm32_spdifrx_capture_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)514 static int stm32_spdifrx_capture_get(struct snd_kcontrol *kcontrol,
515 struct snd_ctl_elem_value *ucontrol)
516 {
517 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
518 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
519
520 stm32_spdifrx_get_ctrl_data(spdifrx);
521
522 ucontrol->value.iec958.status[0] = spdifrx->cs[0];
523 ucontrol->value.iec958.status[1] = spdifrx->cs[1];
524 ucontrol->value.iec958.status[2] = spdifrx->cs[2];
525 ucontrol->value.iec958.status[3] = spdifrx->cs[3];
526 ucontrol->value.iec958.status[4] = spdifrx->cs[4];
527
528 return 0;
529 }
530
stm32_spdif_user_bits_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)531 static int stm32_spdif_user_bits_get(struct snd_kcontrol *kcontrol,
532 struct snd_ctl_elem_value *ucontrol)
533 {
534 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
535 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
536
537 stm32_spdifrx_get_ctrl_data(spdifrx);
538
539 ucontrol->value.iec958.status[0] = spdifrx->ub[0];
540 ucontrol->value.iec958.status[1] = spdifrx->ub[1];
541 ucontrol->value.iec958.status[2] = spdifrx->ub[2];
542 ucontrol->value.iec958.status[3] = spdifrx->ub[3];
543 ucontrol->value.iec958.status[4] = spdifrx->ub[4];
544
545 return 0;
546 }
547
548 static struct snd_kcontrol_new stm32_spdifrx_iec_ctrls[] = {
549 /* Channel status control */
550 {
551 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
552 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
553 .access = SNDRV_CTL_ELEM_ACCESS_READ |
554 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
555 .info = stm32_spdifrx_info,
556 .get = stm32_spdifrx_capture_get,
557 },
558 /* User bits control */
559 {
560 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
561 .name = "IEC958 User Bit Capture Default",
562 .access = SNDRV_CTL_ELEM_ACCESS_READ |
563 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
564 .info = stm32_spdifrx_ub_info,
565 .get = stm32_spdif_user_bits_get,
566 },
567 };
568
569 static struct snd_kcontrol_new stm32_spdifrx_ctrls[] = {
570 SOC_ENUM("SPDIFRX input", ctrl_enum_input),
571 SOC_ENUM("SPDIFRX CS channel", ctrl_enum_cs_channel),
572 };
573
stm32_spdifrx_dai_register_ctrls(struct snd_soc_dai * cpu_dai)574 static int stm32_spdifrx_dai_register_ctrls(struct snd_soc_dai *cpu_dai)
575 {
576 int ret;
577
578 ret = snd_soc_add_dai_controls(cpu_dai, stm32_spdifrx_iec_ctrls,
579 ARRAY_SIZE(stm32_spdifrx_iec_ctrls));
580 if (ret < 0)
581 return ret;
582
583 return snd_soc_add_component_controls(cpu_dai->component,
584 stm32_spdifrx_ctrls,
585 ARRAY_SIZE(stm32_spdifrx_ctrls));
586 }
587
stm32_spdifrx_dai_probe(struct snd_soc_dai * cpu_dai)588 static int stm32_spdifrx_dai_probe(struct snd_soc_dai *cpu_dai)
589 {
590 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(cpu_dai->dev);
591
592 spdifrx->dma_params.addr = (dma_addr_t)(spdifrx->phys_addr +
593 STM32_SPDIFRX_DR);
594 spdifrx->dma_params.maxburst = 1;
595
596 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params);
597
598 return stm32_spdifrx_dai_register_ctrls(cpu_dai);
599 }
600
stm32_spdifrx_readable_reg(struct device * dev,unsigned int reg)601 static bool stm32_spdifrx_readable_reg(struct device *dev, unsigned int reg)
602 {
603 switch (reg) {
604 case STM32_SPDIFRX_CR:
605 case STM32_SPDIFRX_IMR:
606 case STM32_SPDIFRX_SR:
607 case STM32_SPDIFRX_IFCR:
608 case STM32_SPDIFRX_DR:
609 case STM32_SPDIFRX_CSR:
610 case STM32_SPDIFRX_DIR:
611 return true;
612 default:
613 return false;
614 }
615 }
616
stm32_spdifrx_volatile_reg(struct device * dev,unsigned int reg)617 static bool stm32_spdifrx_volatile_reg(struct device *dev, unsigned int reg)
618 {
619 if (reg == STM32_SPDIFRX_DR)
620 return true;
621
622 return false;
623 }
624
stm32_spdifrx_writeable_reg(struct device * dev,unsigned int reg)625 static bool stm32_spdifrx_writeable_reg(struct device *dev, unsigned int reg)
626 {
627 switch (reg) {
628 case STM32_SPDIFRX_CR:
629 case STM32_SPDIFRX_IMR:
630 case STM32_SPDIFRX_IFCR:
631 return true;
632 default:
633 return false;
634 }
635 }
636
637 static const struct regmap_config stm32_h7_spdifrx_regmap_conf = {
638 .reg_bits = 32,
639 .reg_stride = 4,
640 .val_bits = 32,
641 .max_register = STM32_SPDIFRX_DIR,
642 .readable_reg = stm32_spdifrx_readable_reg,
643 .volatile_reg = stm32_spdifrx_volatile_reg,
644 .writeable_reg = stm32_spdifrx_writeable_reg,
645 .fast_io = true,
646 };
647
stm32_spdifrx_isr(int irq,void * devid)648 static irqreturn_t stm32_spdifrx_isr(int irq, void *devid)
649 {
650 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)devid;
651 struct platform_device *pdev = spdifrx->pdev;
652 unsigned int cr, mask, sr, imr;
653 unsigned int flags;
654 int err = 0, err_xrun = 0;
655
656 regmap_read(spdifrx->regmap, STM32_SPDIFRX_SR, &sr);
657 regmap_read(spdifrx->regmap, STM32_SPDIFRX_IMR, &imr);
658
659 mask = imr & SPDIFRX_XIMR_MASK;
660 /* SERR, TERR, FERR IRQs are generated if IFEIE is set */
661 if (mask & SPDIFRX_IMR_IFEIE)
662 mask |= (SPDIFRX_IMR_IFEIE << 1) | (SPDIFRX_IMR_IFEIE << 2);
663
664 flags = sr & mask;
665 if (!flags) {
666 dev_err(&pdev->dev, "Unexpected IRQ. rflags=%#x, imr=%#x\n",
667 sr, imr);
668 return IRQ_NONE;
669 }
670
671 /* Clear IRQs */
672 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR,
673 SPDIFRX_XIFCR_MASK, flags);
674
675 if (flags & SPDIFRX_SR_PERR) {
676 dev_dbg(&pdev->dev, "Parity error\n");
677 err_xrun = 1;
678 }
679
680 if (flags & SPDIFRX_SR_OVR) {
681 dev_dbg(&pdev->dev, "Overrun error\n");
682 err_xrun = 1;
683 }
684
685 if (flags & SPDIFRX_SR_SBD)
686 dev_dbg(&pdev->dev, "Synchronization block detected\n");
687
688 if (flags & SPDIFRX_SR_SYNCD) {
689 dev_dbg(&pdev->dev, "Synchronization done\n");
690
691 /* Enable spdifrx */
692 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_ENABLE);
693 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
694 SPDIFRX_CR_SPDIFEN_MASK, cr);
695 }
696
697 if (flags & SPDIFRX_SR_FERR) {
698 dev_dbg(&pdev->dev, "Frame error\n");
699 err = 1;
700 }
701
702 if (flags & SPDIFRX_SR_SERR) {
703 dev_dbg(&pdev->dev, "Synchronization error\n");
704 err = 1;
705 }
706
707 if (flags & SPDIFRX_SR_TERR) {
708 dev_dbg(&pdev->dev, "Timeout error\n");
709 err = 1;
710 }
711
712 if (err) {
713 /* SPDIFRX in STATE_STOP. Disable SPDIFRX to clear errors */
714 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE);
715 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
716 SPDIFRX_CR_SPDIFEN_MASK, cr);
717
718 spin_lock(&spdifrx->irq_lock);
719 if (spdifrx->substream)
720 snd_pcm_stop(spdifrx->substream,
721 SNDRV_PCM_STATE_DISCONNECTED);
722 spin_unlock(&spdifrx->irq_lock);
723
724 return IRQ_HANDLED;
725 }
726
727 spin_lock(&spdifrx->irq_lock);
728 if (err_xrun && spdifrx->substream)
729 snd_pcm_stop_xrun(spdifrx->substream);
730 spin_unlock(&spdifrx->irq_lock);
731
732 return IRQ_HANDLED;
733 }
734
stm32_spdifrx_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)735 static int stm32_spdifrx_startup(struct snd_pcm_substream *substream,
736 struct snd_soc_dai *cpu_dai)
737 {
738 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
739 unsigned long flags;
740 int ret;
741
742 spin_lock_irqsave(&spdifrx->irq_lock, flags);
743 spdifrx->substream = substream;
744 spin_unlock_irqrestore(&spdifrx->irq_lock, flags);
745
746 ret = clk_prepare_enable(spdifrx->kclk);
747 if (ret)
748 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret);
749
750 return ret;
751 }
752
stm32_spdifrx_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * cpu_dai)753 static int stm32_spdifrx_hw_params(struct snd_pcm_substream *substream,
754 struct snd_pcm_hw_params *params,
755 struct snd_soc_dai *cpu_dai)
756 {
757 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
758 int data_size = params_width(params);
759 int fmt;
760
761 switch (data_size) {
762 case 16:
763 fmt = SPDIFRX_DRFMT_PACKED;
764 spdifrx->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
765 break;
766 case 32:
767 fmt = SPDIFRX_DRFMT_LEFT;
768 spdifrx->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
769 break;
770 default:
771 dev_err(&spdifrx->pdev->dev, "Unexpected data format\n");
772 return -EINVAL;
773 }
774
775 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params);
776
777 return regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
778 SPDIFRX_CR_DRFMT_MASK,
779 SPDIFRX_CR_DRFMTSET(fmt));
780 }
781
stm32_spdifrx_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * cpu_dai)782 static int stm32_spdifrx_trigger(struct snd_pcm_substream *substream, int cmd,
783 struct snd_soc_dai *cpu_dai)
784 {
785 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
786 int ret = 0;
787
788 switch (cmd) {
789 case SNDRV_PCM_TRIGGER_START:
790 case SNDRV_PCM_TRIGGER_RESUME:
791 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
792 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR,
793 SPDIFRX_IMR_OVRIE, SPDIFRX_IMR_OVRIE);
794
795 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
796 SPDIFRX_CR_RXDMAEN, SPDIFRX_CR_RXDMAEN);
797
798 ret = stm32_spdifrx_start_sync(spdifrx);
799 break;
800 case SNDRV_PCM_TRIGGER_SUSPEND:
801 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
802 case SNDRV_PCM_TRIGGER_STOP:
803 stm32_spdifrx_stop(spdifrx);
804 break;
805 default:
806 return -EINVAL;
807 }
808
809 return ret;
810 }
811
stm32_spdifrx_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)812 static void stm32_spdifrx_shutdown(struct snd_pcm_substream *substream,
813 struct snd_soc_dai *cpu_dai)
814 {
815 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
816 unsigned long flags;
817
818 spin_lock_irqsave(&spdifrx->irq_lock, flags);
819 spdifrx->substream = NULL;
820 spin_unlock_irqrestore(&spdifrx->irq_lock, flags);
821
822 clk_disable_unprepare(spdifrx->kclk);
823 }
824
825 static const struct snd_soc_dai_ops stm32_spdifrx_pcm_dai_ops = {
826 .startup = stm32_spdifrx_startup,
827 .hw_params = stm32_spdifrx_hw_params,
828 .trigger = stm32_spdifrx_trigger,
829 .shutdown = stm32_spdifrx_shutdown,
830 };
831
832 static struct snd_soc_dai_driver stm32_spdifrx_dai[] = {
833 {
834 .name = "spdifrx-capture-cpu-dai",
835 .probe = stm32_spdifrx_dai_probe,
836 .capture = {
837 .stream_name = "CPU-Capture",
838 .channels_min = 1,
839 .channels_max = 2,
840 .rates = SNDRV_PCM_RATE_8000_192000,
841 .formats = SNDRV_PCM_FMTBIT_S32_LE |
842 SNDRV_PCM_FMTBIT_S16_LE,
843 },
844 .ops = &stm32_spdifrx_pcm_dai_ops,
845 }
846 };
847
848 static const struct snd_pcm_hardware stm32_spdifrx_pcm_hw = {
849 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
850 .buffer_bytes_max = 8 * PAGE_SIZE,
851 .period_bytes_max = 2048, /* MDMA constraint */
852 .periods_min = 2,
853 .periods_max = 8,
854 };
855
856 static const struct snd_soc_component_driver stm32_spdifrx_component = {
857 .name = "stm32-spdifrx",
858 };
859
860 static const struct snd_dmaengine_pcm_config stm32_spdifrx_pcm_config = {
861 .pcm_hardware = &stm32_spdifrx_pcm_hw,
862 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
863 };
864
865 static const struct of_device_id stm32_spdifrx_ids[] = {
866 {
867 .compatible = "st,stm32h7-spdifrx",
868 .data = &stm32_h7_spdifrx_regmap_conf
869 },
870 {}
871 };
872
stm_spdifrx_parse_of(struct platform_device * pdev,struct stm32_spdifrx_data * spdifrx)873 static int stm_spdifrx_parse_of(struct platform_device *pdev,
874 struct stm32_spdifrx_data *spdifrx)
875 {
876 struct device_node *np = pdev->dev.of_node;
877 const struct of_device_id *of_id;
878 struct resource *res;
879
880 if (!np)
881 return -ENODEV;
882
883 of_id = of_match_device(stm32_spdifrx_ids, &pdev->dev);
884 if (of_id)
885 spdifrx->regmap_conf =
886 (const struct regmap_config *)of_id->data;
887 else
888 return -EINVAL;
889
890 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
891 spdifrx->base = devm_ioremap_resource(&pdev->dev, res);
892 if (IS_ERR(spdifrx->base))
893 return PTR_ERR(spdifrx->base);
894
895 spdifrx->phys_addr = res->start;
896
897 spdifrx->kclk = devm_clk_get(&pdev->dev, "kclk");
898 if (IS_ERR(spdifrx->kclk)) {
899 dev_err(&pdev->dev, "Could not get kclk\n");
900 return PTR_ERR(spdifrx->kclk);
901 }
902
903 spdifrx->irq = platform_get_irq(pdev, 0);
904 if (spdifrx->irq < 0) {
905 dev_err(&pdev->dev, "No irq for node %s\n", pdev->name);
906 return spdifrx->irq;
907 }
908
909 return 0;
910 }
911
stm32_spdifrx_probe(struct platform_device * pdev)912 static int stm32_spdifrx_probe(struct platform_device *pdev)
913 {
914 struct stm32_spdifrx_data *spdifrx;
915 struct reset_control *rst;
916 const struct snd_dmaengine_pcm_config *pcm_config = NULL;
917 int ret;
918
919 spdifrx = devm_kzalloc(&pdev->dev, sizeof(*spdifrx), GFP_KERNEL);
920 if (!spdifrx)
921 return -ENOMEM;
922
923 spdifrx->pdev = pdev;
924 init_completion(&spdifrx->cs_completion);
925 spin_lock_init(&spdifrx->lock);
926 spin_lock_init(&spdifrx->irq_lock);
927
928 platform_set_drvdata(pdev, spdifrx);
929
930 ret = stm_spdifrx_parse_of(pdev, spdifrx);
931 if (ret)
932 return ret;
933
934 spdifrx->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "kclk",
935 spdifrx->base,
936 spdifrx->regmap_conf);
937 if (IS_ERR(spdifrx->regmap)) {
938 dev_err(&pdev->dev, "Regmap init failed\n");
939 return PTR_ERR(spdifrx->regmap);
940 }
941
942 ret = devm_request_irq(&pdev->dev, spdifrx->irq, stm32_spdifrx_isr, 0,
943 dev_name(&pdev->dev), spdifrx);
944 if (ret) {
945 dev_err(&pdev->dev, "IRQ request returned %d\n", ret);
946 return ret;
947 }
948
949 rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
950 if (!IS_ERR(rst)) {
951 reset_control_assert(rst);
952 udelay(2);
953 reset_control_deassert(rst);
954 }
955
956 ret = devm_snd_soc_register_component(&pdev->dev,
957 &stm32_spdifrx_component,
958 stm32_spdifrx_dai,
959 ARRAY_SIZE(stm32_spdifrx_dai));
960 if (ret)
961 return ret;
962
963 ret = stm32_spdifrx_dma_ctrl_register(&pdev->dev, spdifrx);
964 if (ret)
965 goto error;
966
967 pcm_config = &stm32_spdifrx_pcm_config;
968 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, pcm_config, 0);
969 if (ret) {
970 dev_err(&pdev->dev, "PCM DMA register returned %d\n", ret);
971 goto error;
972 }
973
974 return 0;
975
976 error:
977 if (spdifrx->ctrl_chan)
978 dma_release_channel(spdifrx->ctrl_chan);
979 if (spdifrx->dmab)
980 snd_dma_free_pages(spdifrx->dmab);
981
982 return ret;
983 }
984
stm32_spdifrx_remove(struct platform_device * pdev)985 static int stm32_spdifrx_remove(struct platform_device *pdev)
986 {
987 struct stm32_spdifrx_data *spdifrx = platform_get_drvdata(pdev);
988
989 if (spdifrx->ctrl_chan)
990 dma_release_channel(spdifrx->ctrl_chan);
991
992 if (spdifrx->dmab)
993 snd_dma_free_pages(spdifrx->dmab);
994
995 return 0;
996 }
997
998 MODULE_DEVICE_TABLE(of, stm32_spdifrx_ids);
999
1000 static struct platform_driver stm32_spdifrx_driver = {
1001 .driver = {
1002 .name = "st,stm32-spdifrx",
1003 .of_match_table = stm32_spdifrx_ids,
1004 },
1005 .probe = stm32_spdifrx_probe,
1006 .remove = stm32_spdifrx_remove,
1007 };
1008
1009 module_platform_driver(stm32_spdifrx_driver);
1010
1011 MODULE_DESCRIPTION("STM32 Soc spdifrx Interface");
1012 MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>");
1013 MODULE_ALIAS("platform:stm32-spdifrx");
1014 MODULE_LICENSE("GPL v2");
1015