Lines Matching refs:clks
88 clocks = <&clks IMX7D_ARM_A7_ROOT_CLK>, <&clks IMX7D_ARM_A7_ROOT_SRC>,
89 <&clks IMX7D_PLL_ARM_MAIN_CLK>, <&clks IMX7D_PLL_SYS_MAIN_CLK>;
127 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
141 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
192 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
219 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
256 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
296 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
317 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
422 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
429 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
437 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
445 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
459 clocks = <&clks IMX7D_CLK_DUMMY>,
460 <&clks IMX7D_GPT1_ROOT_CLK>;
468 clocks = <&clks IMX7D_CLK_DUMMY>,
469 <&clks IMX7D_GPT2_ROOT_CLK>;
478 clocks = <&clks IMX7D_CLK_DUMMY>,
479 <&clks IMX7D_GPT3_ROOT_CLK>;
488 clocks = <&clks IMX7D_CLK_DUMMY>,
489 <&clks IMX7D_GPT4_ROOT_CLK>;
507 clocks = <&clks IMX7D_CLK_DUMMY>;
561 clks: ccm@30380000 { label
590 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
591 <&clks IMX7D_PWM1_ROOT_CLK>;
601 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
602 <&clks IMX7D_PWM2_ROOT_CLK>;
612 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
613 <&clks IMX7D_PWM3_ROOT_CLK>;
623 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
624 <&clks IMX7D_PWM4_ROOT_CLK>;
643 clocks = <&clks IMX7D_UART1_ROOT_CLK>,
644 <&clks IMX7D_UART1_ROOT_CLK>;
654 clocks = <&clks IMX7D_UART2_ROOT_CLK>,
655 <&clks IMX7D_UART2_ROOT_CLK>;
665 clocks = <&clks IMX7D_UART3_ROOT_CLK>,
666 <&clks IMX7D_UART3_ROOT_CLK>;
677 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
687 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
697 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
707 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
716 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
717 <&clks IMX7D_UART4_ROOT_CLK>;
727 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
728 <&clks IMX7D_UART5_ROOT_CLK>;
738 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
739 <&clks IMX7D_UART6_ROOT_CLK>;
749 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
750 <&clks IMX7D_UART7_ROOT_CLK>;
759 clocks = <&clks IMX7D_USB_CTRL_CLK>;
770 clocks = <&clks IMX7D_USB_CTRL_CLK>;
781 clocks = <&clks IMX7D_USB_CTRL_CLK>;
810 clocks = <&clks IMX7D_USB_PHY1_CLK>;
816 clocks = <&clks IMX7D_USB_PHY2_CLK>;
822 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
830 clocks = <&clks IMX7D_CLK_DUMMY>,
831 <&clks IMX7D_CLK_DUMMY>,
832 <&clks IMX7D_USDHC1_ROOT_CLK>;
842 clocks = <&clks IMX7D_CLK_DUMMY>,
843 <&clks IMX7D_CLK_DUMMY>,
844 <&clks IMX7D_USDHC2_ROOT_CLK>;
854 clocks = <&clks IMX7D_CLK_DUMMY>,
855 <&clks IMX7D_CLK_DUMMY>,
856 <&clks IMX7D_USDHC3_ROOT_CLK>;
868 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
869 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
870 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
871 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
872 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
886 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
887 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
888 <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
889 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
890 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;