1/* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include <dt-bindings/clock/imx7d-clock.h> 44#include <dt-bindings/gpio/gpio.h> 45#include <dt-bindings/interrupt-controller/arm-gic.h> 46#include "imx7d-pinfunc.h" 47#include "skeleton.dtsi" 48 49/ { 50 aliases { 51 gpio0 = &gpio1; 52 gpio1 = &gpio2; 53 gpio2 = &gpio3; 54 gpio3 = &gpio4; 55 gpio4 = &gpio5; 56 gpio5 = &gpio6; 57 gpio6 = &gpio7; 58 i2c0 = &i2c1; 59 i2c1 = &i2c2; 60 i2c2 = &i2c3; 61 i2c3 = &i2c4; 62 mmc0 = &usdhc1; 63 mmc1 = &usdhc2; 64 mmc2 = &usdhc3; 65 serial0 = &uart1; 66 serial1 = &uart2; 67 serial2 = &uart3; 68 serial3 = &uart4; 69 serial4 = &uart5; 70 serial5 = &uart6; 71 serial6 = &uart7; 72 }; 73 74 cpus { 75 #address-cells = <1>; 76 #size-cells = <0>; 77 78 cpu0: cpu@0 { 79 compatible = "arm,cortex-a7"; 80 device_type = "cpu"; 81 reg = <0>; 82 operating-points = < 83 /* KHz uV */ 84 996000 1075000 85 792000 975000 86 >; 87 clock-latency = <61036>; /* two CLK32 periods */ 88 clocks = <&clks IMX7D_ARM_A7_ROOT_CLK>, <&clks IMX7D_ARM_A7_ROOT_SRC>, 89 <&clks IMX7D_PLL_ARM_MAIN_CLK>, <&clks IMX7D_PLL_SYS_MAIN_CLK>; 90 clock-names = "arm", "arm_root_src", "pll_arm", "pll_sys_main"; 91 }; 92 93 cpu1: cpu@1 { 94 compatible = "arm,cortex-a7"; 95 device_type = "cpu"; 96 reg = <1>; 97 }; 98 }; 99 100 intc: interrupt-controller@31001000 { 101 compatible = "arm,cortex-a7-gic"; 102 #interrupt-cells = <3>; 103 interrupt-controller; 104 reg = <0x31001000 0x1000>, 105 <0x31002000 0x1000>, 106 <0x31004000 0x2000>, 107 <0x31006000 0x2000>; 108 }; 109 110 ckil: clock-cki { 111 compatible = "fixed-clock"; 112 #clock-cells = <0>; 113 clock-frequency = <32768>; 114 clock-output-names = "ckil"; 115 }; 116 117 osc: clock-osc { 118 compatible = "fixed-clock"; 119 #clock-cells = <0>; 120 clock-frequency = <24000000>; 121 clock-output-names = "osc"; 122 }; 123 124 etr@30086000 { 125 compatible = "arm,coresight-tmc", "arm,primecell"; 126 reg = <0x30086000 0x1000>; 127 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 128 clock-names = "apb_pclk"; 129 130 port { 131 etr_in_port: endpoint { 132 slave-mode; 133 remote-endpoint = <&replicator_out_port1>; 134 }; 135 }; 136 }; 137 138 tpiu@30087000 { 139 compatible = "arm,coresight-tpiu", "arm,primecell"; 140 reg = <0x30087000 0x1000>; 141 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 142 clock-names = "apb_pclk"; 143 144 port { 145 tpiu_in_port: endpoint { 146 slave-mode; 147 remote-endpoint = <&replicator_out_port1>; 148 }; 149 }; 150 }; 151 152 replicator { 153 /* 154 * non-configurable replicators don't show up on the 155 * AMBA bus. As such no need to add "arm,primecell" 156 */ 157 compatible = "arm,coresight-replicator"; 158 159 ports { 160 #address-cells = <1>; 161 #size-cells = <0>; 162 163 /* replicator output ports */ 164 port@0 { 165 reg = <0>; 166 replicator_out_port0: endpoint { 167 remote-endpoint = <&tpiu_in_port>; 168 }; 169 }; 170 171 port@1 { 172 reg = <1>; 173 replicator_out_port1: endpoint { 174 remote-endpoint = <&etr_in_port>; 175 }; 176 }; 177 178 /* replicator input port */ 179 port@2 { 180 reg = <0>; 181 replicator_in_port0: endpoint { 182 slave-mode; 183 remote-endpoint = <&etf_out_port>; 184 }; 185 }; 186 }; 187 }; 188 189 etf@30084000 { 190 compatible = "arm,coresight-tmc", "arm,primecell"; 191 reg = <0x30084000 0x1000>; 192 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 193 clock-names = "apb_pclk"; 194 195 ports { 196 #address-cells = <1>; 197 #size-cells = <0>; 198 199 port@0 { 200 reg = <0>; 201 etf_in_port: endpoint { 202 slave-mode; 203 remote-endpoint = <&hugo_funnel_out_port0>; 204 }; 205 }; 206 207 port@1 { 208 reg = <0>; 209 etf_out_port: endpoint { 210 remote-endpoint = <&replicator_in_port0>; 211 }; 212 }; 213 }; 214 }; 215 216 funnel@30083000 { 217 compatible = "arm,coresight-funnel", "arm,primecell"; 218 reg = <0x30083000 0x1000>; 219 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 220 clock-names = "apb_pclk"; 221 222 ports { 223 #address-cells = <1>; 224 #size-cells = <0>; 225 226 /* funnel input ports */ 227 port@0 { 228 reg = <0>; 229 hugo_funnel_in_port0: endpoint { 230 slave-mode; 231 remote-endpoint = <&ca_funnel_out_port0>; 232 }; 233 }; 234 235 port@1 { 236 reg = <1>; 237 hugo_funnel_in_port1: endpoint { 238 slave-mode; /* M4 input */ 239 }; 240 }; 241 242 port@2 { 243 reg = <0>; 244 hugo_funnel_out_port0: endpoint { 245 remote-endpoint = <&etf_in_port>; 246 }; 247 }; 248 249 /* the other input ports are not connect to anything */ 250 }; 251 }; 252 253 funnel@30041000 { 254 compatible = "arm,coresight-funnel", "arm,primecell"; 255 reg = <0x30041000 0x1000>; 256 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 257 clock-names = "apb_pclk"; 258 259 ports { 260 #address-cells = <1>; 261 #size-cells = <0>; 262 263 /* funnel input ports */ 264 port@0 { 265 reg = <0>; 266 ca_funnel_in_port0: endpoint { 267 slave-mode; 268 remote-endpoint = <&etm0_out_port>; 269 }; 270 }; 271 272 port@1 { 273 reg = <1>; 274 ca_funnel_in_port1: endpoint { 275 slave-mode; 276 remote-endpoint = <&etm1_out_port>; 277 }; 278 }; 279 280 /* funnel output port */ 281 port@2 { 282 reg = <0>; 283 ca_funnel_out_port0: endpoint { 284 remote-endpoint = <&hugo_funnel_in_port0>; 285 }; 286 }; 287 288 /* the other input ports are not connect to anything */ 289 }; 290 }; 291 292 etm@3007c000 { 293 compatible = "arm,coresight-etm3x", "arm,primecell"; 294 reg = <0x3007c000 0x1000>; 295 cpu = <&cpu0>; 296 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 297 clock-names = "apb_pclk"; 298 299 port { 300 etm0_out_port: endpoint { 301 remote-endpoint = <&ca_funnel_in_port0>; 302 }; 303 }; 304 }; 305 306 etm@3007d000 { 307 compatible = "arm,coresight-etm3x", "arm,primecell"; 308 reg = <0x3007d000 0x1000>; 309 310 /* 311 * System will hang if added nosmp in kernel command line 312 * without arm,primecell-periphid because amba bus try to 313 * read id and core1 power off at this time. 314 */ 315 arm,primecell-periphid = <0xbb956>; 316 cpu = <&cpu1>; 317 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 318 clock-names = "apb_pclk"; 319 320 port { 321 etm1_out_port: endpoint { 322 remote-endpoint = <&ca_funnel_in_port1>; 323 }; 324 }; 325 }; 326 327 soc { 328 #address-cells = <1>; 329 #size-cells = <1>; 330 compatible = "simple-bus"; 331 interrupt-parent = <&intc>; 332 ranges; 333 334 aips1: aips-bus@30000000 { 335 compatible = "fsl,aips-bus", "simple-bus"; 336 #address-cells = <1>; 337 #size-cells = <1>; 338 reg = <0x30000000 0x400000>; 339 ranges; 340 341 gpio1: gpio@30200000 { 342 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 343 reg = <0x30200000 0x10000>; 344 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */ 345 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */ 346 gpio-controller; 347 #gpio-cells = <2>; 348 interrupt-controller; 349 #interrupt-cells = <2>; 350 }; 351 352 gpio2: gpio@30210000 { 353 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 354 reg = <0x30210000 0x10000>; 355 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 357 gpio-controller; 358 #gpio-cells = <2>; 359 interrupt-controller; 360 #interrupt-cells = <2>; 361 }; 362 363 gpio3: gpio@30220000 { 364 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 365 reg = <0x30220000 0x10000>; 366 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 368 gpio-controller; 369 #gpio-cells = <2>; 370 interrupt-controller; 371 #interrupt-cells = <2>; 372 }; 373 374 gpio4: gpio@30230000 { 375 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 376 reg = <0x30230000 0x10000>; 377 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 379 gpio-controller; 380 #gpio-cells = <2>; 381 interrupt-controller; 382 #interrupt-cells = <2>; 383 }; 384 385 gpio5: gpio@30240000 { 386 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 387 reg = <0x30240000 0x10000>; 388 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 390 gpio-controller; 391 #gpio-cells = <2>; 392 interrupt-controller; 393 #interrupt-cells = <2>; 394 }; 395 396 gpio6: gpio@30250000 { 397 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 398 reg = <0x30250000 0x10000>; 399 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 401 gpio-controller; 402 #gpio-cells = <2>; 403 interrupt-controller; 404 #interrupt-cells = <2>; 405 }; 406 407 gpio7: gpio@30260000 { 408 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 409 reg = <0x30260000 0x10000>; 410 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 412 gpio-controller; 413 #gpio-cells = <2>; 414 interrupt-controller; 415 #interrupt-cells = <2>; 416 }; 417 418 wdog1: wdog@30280000 { 419 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 420 reg = <0x30280000 0x10000>; 421 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; 423 }; 424 425 wdog2: wdog@30290000 { 426 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 427 reg = <0x30290000 0x10000>; 428 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>; 430 status = "disabled"; 431 }; 432 433 wdog3: wdog@302a0000 { 434 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 435 reg = <0x302a0000 0x10000>; 436 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 437 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>; 438 status = "disabled"; 439 }; 440 441 wdog4: wdog@302b0000 { 442 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 443 reg = <0x302b0000 0x10000>; 444 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>; 446 status = "disabled"; 447 }; 448 449 iomuxc_lpsr: iomuxc-lpsr@302c0000 { 450 compatible = "fsl,imx7d-iomuxc-lpsr"; 451 reg = <0x302c0000 0x10000>; 452 fsl,input-sel = <&iomuxc>; 453 }; 454 455 gpt1: gpt@302d0000 { 456 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 457 reg = <0x302d0000 0x10000>; 458 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&clks IMX7D_CLK_DUMMY>, 460 <&clks IMX7D_GPT1_ROOT_CLK>; 461 clock-names = "ipg", "per"; 462 }; 463 464 gpt2: gpt@302e0000 { 465 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 466 reg = <0x302e0000 0x10000>; 467 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 468 clocks = <&clks IMX7D_CLK_DUMMY>, 469 <&clks IMX7D_GPT2_ROOT_CLK>; 470 clock-names = "ipg", "per"; 471 status = "disabled"; 472 }; 473 474 gpt3: gpt@302f0000 { 475 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 476 reg = <0x302f0000 0x10000>; 477 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 478 clocks = <&clks IMX7D_CLK_DUMMY>, 479 <&clks IMX7D_GPT3_ROOT_CLK>; 480 clock-names = "ipg", "per"; 481 status = "disabled"; 482 }; 483 484 gpt4: gpt@30300000 { 485 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 486 reg = <0x30300000 0x10000>; 487 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 488 clocks = <&clks IMX7D_CLK_DUMMY>, 489 <&clks IMX7D_GPT4_ROOT_CLK>; 490 clock-names = "ipg", "per"; 491 status = "disabled"; 492 }; 493 494 iomuxc: iomuxc@30330000 { 495 compatible = "fsl,imx7d-iomuxc"; 496 reg = <0x30330000 0x10000>; 497 }; 498 499 gpr: iomuxc-gpr@30340000 { 500 compatible = "fsl,imx7d-iomuxc-gpr", "syscon"; 501 reg = <0x30340000 0x10000>; 502 }; 503 504 ocotp: ocotp-ctrl@30350000 { 505 compatible = "syscon"; 506 reg = <0x30350000 0x10000>; 507 clocks = <&clks IMX7D_CLK_DUMMY>; 508 status = "disabled"; 509 }; 510 511 anatop: anatop@30360000 { 512 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", 513 "syscon", "simple-bus"; 514 reg = <0x30360000 0x10000>; 515 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 517 518 reg_1p0d: regulator-vdd1p0d@210 { 519 compatible = "fsl,anatop-regulator"; 520 regulator-name = "vdd1p0d"; 521 regulator-min-microvolt = <800000>; 522 regulator-max-microvolt = <1200000>; 523 anatop-reg-offset = <0x210>; 524 anatop-vol-bit-shift = <8>; 525 anatop-vol-bit-width = <5>; 526 anatop-min-bit-val = <8>; 527 anatop-min-voltage = <800000>; 528 anatop-max-voltage = <1200000>; 529 anatop-enable-bit = <31>; 530 }; 531 }; 532 533 snvs: snvs@30370000 { 534 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 535 reg = <0x30370000 0x10000>; 536 537 snvs_rtc: snvs-rtc-lp { 538 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 539 regmap = <&snvs>; 540 offset = <0x34>; 541 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 543 }; 544 545 snvs_poweroff: snvs-poweroff { 546 compatible = "syscon-poweroff"; 547 regmap = <&snvs>; 548 offset = <0x38>; 549 mask = <0x60>; 550 }; 551 552 snvs_pwrkey: snvs-powerkey { 553 compatible = "fsl,sec-v4.0-pwrkey"; 554 regmap = <&snvs>; 555 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 556 linux,keycode = <KEY_POWER>; 557 wakeup-source; 558 }; 559 }; 560 561 clks: ccm@30380000 { 562 compatible = "fsl,imx7d-ccm"; 563 reg = <0x30380000 0x10000>; 564 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 566 #clock-cells = <1>; 567 clocks = <&ckil>, <&osc>; 568 clock-names = "ckil", "osc"; 569 }; 570 571 src: src@30390000 { 572 compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon"; 573 reg = <0x30390000 0x10000>; 574 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 575 #reset-cells = <1>; 576 }; 577 }; 578 579 aips2: aips-bus@30400000 { 580 compatible = "fsl,aips-bus", "simple-bus"; 581 #address-cells = <1>; 582 #size-cells = <1>; 583 reg = <0x30400000 0x400000>; 584 ranges; 585 586 pwm1: pwm@30660000 { 587 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 588 reg = <0x30660000 0x10000>; 589 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 590 clocks = <&clks IMX7D_PWM1_ROOT_CLK>, 591 <&clks IMX7D_PWM1_ROOT_CLK>; 592 clock-names = "ipg", "per"; 593 #pwm-cells = <2>; 594 status = "disabled"; 595 }; 596 597 pwm2: pwm@30670000 { 598 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 599 reg = <0x30670000 0x10000>; 600 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 601 clocks = <&clks IMX7D_PWM2_ROOT_CLK>, 602 <&clks IMX7D_PWM2_ROOT_CLK>; 603 clock-names = "ipg", "per"; 604 #pwm-cells = <2>; 605 status = "disabled"; 606 }; 607 608 pwm3: pwm@30680000 { 609 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 610 reg = <0x30680000 0x10000>; 611 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&clks IMX7D_PWM3_ROOT_CLK>, 613 <&clks IMX7D_PWM3_ROOT_CLK>; 614 clock-names = "ipg", "per"; 615 #pwm-cells = <2>; 616 status = "disabled"; 617 }; 618 619 pwm4: pwm@30690000 { 620 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 621 reg = <0x30690000 0x10000>; 622 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 623 clocks = <&clks IMX7D_PWM4_ROOT_CLK>, 624 <&clks IMX7D_PWM4_ROOT_CLK>; 625 clock-names = "ipg", "per"; 626 #pwm-cells = <2>; 627 status = "disabled"; 628 }; 629 }; 630 631 aips3: aips-bus@30800000 { 632 compatible = "fsl,aips-bus", "simple-bus"; 633 #address-cells = <1>; 634 #size-cells = <1>; 635 reg = <0x30800000 0x400000>; 636 ranges; 637 638 uart1: serial@30860000 { 639 compatible = "fsl,imx7d-uart", 640 "fsl,imx6q-uart"; 641 reg = <0x30860000 0x10000>; 642 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&clks IMX7D_UART1_ROOT_CLK>, 644 <&clks IMX7D_UART1_ROOT_CLK>; 645 clock-names = "ipg", "per"; 646 status = "disabled"; 647 }; 648 649 uart2: serial@30890000 { 650 compatible = "fsl,imx7d-uart", 651 "fsl,imx6q-uart"; 652 reg = <0x30890000 0x10000>; 653 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 654 clocks = <&clks IMX7D_UART2_ROOT_CLK>, 655 <&clks IMX7D_UART2_ROOT_CLK>; 656 clock-names = "ipg", "per"; 657 status = "disabled"; 658 }; 659 660 uart3: serial@30880000 { 661 compatible = "fsl,imx7d-uart", 662 "fsl,imx6q-uart"; 663 reg = <0x30880000 0x10000>; 664 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 665 clocks = <&clks IMX7D_UART3_ROOT_CLK>, 666 <&clks IMX7D_UART3_ROOT_CLK>; 667 clock-names = "ipg", "per"; 668 status = "disabled"; 669 }; 670 671 i2c1: i2c@30a20000 { 672 #address-cells = <1>; 673 #size-cells = <0>; 674 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 675 reg = <0x30a20000 0x10000>; 676 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&clks IMX7D_I2C1_ROOT_CLK>; 678 status = "disabled"; 679 }; 680 681 i2c2: i2c@30a30000 { 682 #address-cells = <1>; 683 #size-cells = <0>; 684 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 685 reg = <0x30a30000 0x10000>; 686 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 687 clocks = <&clks IMX7D_I2C2_ROOT_CLK>; 688 status = "disabled"; 689 }; 690 691 i2c3: i2c@30a40000 { 692 #address-cells = <1>; 693 #size-cells = <0>; 694 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 695 reg = <0x30a40000 0x10000>; 696 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 697 clocks = <&clks IMX7D_I2C3_ROOT_CLK>; 698 status = "disabled"; 699 }; 700 701 i2c4: i2c@30a50000 { 702 #address-cells = <1>; 703 #size-cells = <0>; 704 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 705 reg = <0x30a50000 0x10000>; 706 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 707 clocks = <&clks IMX7D_I2C4_ROOT_CLK>; 708 status = "disabled"; 709 }; 710 711 uart4: serial@30a60000 { 712 compatible = "fsl,imx7d-uart", 713 "fsl,imx6q-uart"; 714 reg = <0x30a60000 0x10000>; 715 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 716 clocks = <&clks IMX7D_UART4_ROOT_CLK>, 717 <&clks IMX7D_UART4_ROOT_CLK>; 718 clock-names = "ipg", "per"; 719 status = "disabled"; 720 }; 721 722 uart5: serial@30a70000 { 723 compatible = "fsl,imx7d-uart", 724 "fsl,imx6q-uart"; 725 reg = <0x30a70000 0x10000>; 726 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 727 clocks = <&clks IMX7D_UART5_ROOT_CLK>, 728 <&clks IMX7D_UART5_ROOT_CLK>; 729 clock-names = "ipg", "per"; 730 status = "disabled"; 731 }; 732 733 uart6: serial@30a80000 { 734 compatible = "fsl,imx7d-uart", 735 "fsl,imx6q-uart"; 736 reg = <0x30a80000 0x10000>; 737 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&clks IMX7D_UART6_ROOT_CLK>, 739 <&clks IMX7D_UART6_ROOT_CLK>; 740 clock-names = "ipg", "per"; 741 status = "disabled"; 742 }; 743 744 uart7: serial@30a90000 { 745 compatible = "fsl,imx7d-uart", 746 "fsl,imx6q-uart"; 747 reg = <0x30a90000 0x10000>; 748 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&clks IMX7D_UART7_ROOT_CLK>, 750 <&clks IMX7D_UART7_ROOT_CLK>; 751 clock-names = "ipg", "per"; 752 status = "disabled"; 753 }; 754 755 usbotg1: usb@30b10000 { 756 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 757 reg = <0x30b10000 0x200>; 758 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 759 clocks = <&clks IMX7D_USB_CTRL_CLK>; 760 fsl,usbphy = <&usbphynop1>; 761 fsl,usbmisc = <&usbmisc1 0>; 762 phy-clkgate-delay-us = <400>; 763 status = "disabled"; 764 }; 765 766 usbotg2: usb@30b20000 { 767 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 768 reg = <0x30b20000 0x200>; 769 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 770 clocks = <&clks IMX7D_USB_CTRL_CLK>; 771 fsl,usbphy = <&usbphynop2>; 772 fsl,usbmisc = <&usbmisc2 0>; 773 phy-clkgate-delay-us = <400>; 774 status = "disabled"; 775 }; 776 777 usbh: usb@30b30000 { 778 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 779 reg = <0x30b30000 0x200>; 780 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&clks IMX7D_USB_CTRL_CLK>; 782 fsl,usbphy = <&usbphynop3>; 783 fsl,usbmisc = <&usbmisc3 0>; 784 phy_type = "hsic"; 785 dr_mode = "host"; 786 phy-clkgate-delay-us = <400>; 787 status = "disabled"; 788 }; 789 790 usbmisc1: usbmisc@30b10200 { 791 #index-cells = <1>; 792 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 793 reg = <0x30b10200 0x200>; 794 }; 795 796 usbmisc2: usbmisc@30b20200 { 797 #index-cells = <1>; 798 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 799 reg = <0x30b20200 0x200>; 800 }; 801 802 usbmisc3: usbmisc@30b30200 { 803 #index-cells = <1>; 804 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 805 reg = <0x30b30200 0x200>; 806 }; 807 808 usbphynop1: usbphynop1 { 809 compatible = "usb-nop-xceiv"; 810 clocks = <&clks IMX7D_USB_PHY1_CLK>; 811 clock-names = "main_clk"; 812 }; 813 814 usbphynop2: usbphynop2 { 815 compatible = "usb-nop-xceiv"; 816 clocks = <&clks IMX7D_USB_PHY2_CLK>; 817 clock-names = "main_clk"; 818 }; 819 820 usbphynop3: usbphynop3 { 821 compatible = "usb-nop-xceiv"; 822 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; 823 clock-names = "main_clk"; 824 }; 825 826 usdhc1: usdhc@30b40000 { 827 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 828 reg = <0x30b40000 0x10000>; 829 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 830 clocks = <&clks IMX7D_CLK_DUMMY>, 831 <&clks IMX7D_CLK_DUMMY>, 832 <&clks IMX7D_USDHC1_ROOT_CLK>; 833 clock-names = "ipg", "ahb", "per"; 834 bus-width = <4>; 835 status = "disabled"; 836 }; 837 838 usdhc2: usdhc@30b50000 { 839 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 840 reg = <0x30b50000 0x10000>; 841 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 842 clocks = <&clks IMX7D_CLK_DUMMY>, 843 <&clks IMX7D_CLK_DUMMY>, 844 <&clks IMX7D_USDHC2_ROOT_CLK>; 845 clock-names = "ipg", "ahb", "per"; 846 bus-width = <4>; 847 status = "disabled"; 848 }; 849 850 usdhc3: usdhc@30b60000 { 851 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 852 reg = <0x30b60000 0x10000>; 853 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 854 clocks = <&clks IMX7D_CLK_DUMMY>, 855 <&clks IMX7D_CLK_DUMMY>, 856 <&clks IMX7D_USDHC3_ROOT_CLK>; 857 clock-names = "ipg", "ahb", "per"; 858 bus-width = <4>; 859 status = "disabled"; 860 }; 861 862 fec1: ethernet@30be0000 { 863 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; 864 reg = <0x30be0000 0x10000>; 865 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 867 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 868 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, 869 <&clks IMX7D_ENET_AXI_ROOT_CLK>, 870 <&clks IMX7D_ENET1_TIME_ROOT_CLK>, 871 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, 872 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; 873 clock-names = "ipg", "ahb", "ptp", 874 "enet_clk_ref", "enet_out"; 875 fsl,num-tx-queues=<3>; 876 fsl,num-rx-queues=<3>; 877 status = "disabled"; 878 }; 879 880 fec2: ethernet@30bf0000 { 881 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; 882 reg = <0x30bf0000 0x10000>; 883 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 886 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, 887 <&clks IMX7D_ENET_AXI_ROOT_CLK>, 888 <&clks IMX7D_ENET2_TIME_ROOT_CLK>, 889 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, 890 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; 891 clock-names = "ipg", "ahb", "ptp", 892 "enet_clk_ref", "enet_out"; 893 fsl,num-tx-queues=<3>; 894 fsl,num-rx-queues=<3>; 895 status = "disabled"; 896 }; 897 }; 898 }; 899}; 900