Lines Matching refs:clk_lock
49 static DEFINE_SPINLOCK(clk_lock);
162 ARRAY_SIZE(uart_factor_tbl), &clk_lock); in pxa168_clk_init()
167 apbc_base + APBC_TWSI0, 10, 0, &clk_lock); in pxa168_clk_init()
171 apbc_base + APBC_TWSI1, 10, 0, &clk_lock); in pxa168_clk_init()
175 apbc_base + APBC_GPIO, 10, 0, &clk_lock); in pxa168_clk_init()
179 apbc_base + APBC_KPC, 10, 0, &clk_lock); in pxa168_clk_init()
183 apbc_base + APBC_RTC, 10, 0, &clk_lock); in pxa168_clk_init()
187 apbc_base + APBC_PWM0, 10, 0, &clk_lock); in pxa168_clk_init()
191 apbc_base + APBC_PWM1, 10, 0, &clk_lock); in pxa168_clk_init()
195 apbc_base + APBC_PWM2, 10, 0, &clk_lock); in pxa168_clk_init()
199 apbc_base + APBC_PWM3, 10, 0, &clk_lock); in pxa168_clk_init()
205 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); in pxa168_clk_init()
210 apbc_base + APBC_UART0, 10, 0, &clk_lock); in pxa168_clk_init()
216 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); in pxa168_clk_init()
221 apbc_base + APBC_UART1, 10, 0, &clk_lock); in pxa168_clk_init()
227 apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); in pxa168_clk_init()
232 apbc_base + APBC_UART2, 10, 0, &clk_lock); in pxa168_clk_init()
238 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); in pxa168_clk_init()
242 10, 0, &clk_lock); in pxa168_clk_init()
248 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); in pxa168_clk_init()
252 10, 0, &clk_lock); in pxa168_clk_init()
258 apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock); in pxa168_clk_init()
262 10, 0, &clk_lock); in pxa168_clk_init()
268 apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock); in pxa168_clk_init()
272 10, 0, &clk_lock); in pxa168_clk_init()
278 apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock); in pxa168_clk_init()
282 10, 0, &clk_lock); in pxa168_clk_init()
286 0x19b, &clk_lock); in pxa168_clk_init()
292 apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock); in pxa168_clk_init()
296 0x1b, &clk_lock); in pxa168_clk_init()
302 apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock); in pxa168_clk_init()
306 0x1b, &clk_lock); in pxa168_clk_init()
310 0x9, &clk_lock); in pxa168_clk_init()
314 0x12, &clk_lock); in pxa168_clk_init()
320 apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock); in pxa168_clk_init()
324 apmu_base + APMU_DISP0, 0x1b, &clk_lock); in pxa168_clk_init()
328 apmu_base + APMU_DISP0, 0x24, &clk_lock); in pxa168_clk_init()
334 apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock); in pxa168_clk_init()
338 apmu_base + APMU_CCIC0, 0x1b, &clk_lock); in pxa168_clk_init()
344 apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock); in pxa168_clk_init()
348 apmu_base + APMU_CCIC0, 0x24, &clk_lock); in pxa168_clk_init()
353 10, 5, 0, &clk_lock); in pxa168_clk_init()
357 apmu_base + APMU_CCIC0, 0x300, &clk_lock); in pxa168_clk_init()