1 /*
2 * pxa168 clock framework source file
3 *
4 * Copyright (C) 2012 Marvell
5 * Chao Xie <xiechao.mail@gmail.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/spinlock.h>
16 #include <linux/io.h>
17 #include <linux/delay.h>
18 #include <linux/err.h>
19
20 #include <mach/addr-map.h>
21
22 #include "clk.h"
23
24 #define APBC_RTC 0x28
25 #define APBC_TWSI0 0x2c
26 #define APBC_KPC 0x30
27 #define APBC_UART0 0x0
28 #define APBC_UART1 0x4
29 #define APBC_GPIO 0x8
30 #define APBC_PWM0 0xc
31 #define APBC_PWM1 0x10
32 #define APBC_PWM2 0x14
33 #define APBC_PWM3 0x18
34 #define APBC_SSP0 0x81c
35 #define APBC_SSP1 0x820
36 #define APBC_SSP2 0x84c
37 #define APBC_SSP3 0x858
38 #define APBC_SSP4 0x85c
39 #define APBC_TWSI1 0x6c
40 #define APBC_UART2 0x70
41 #define APMU_SDH0 0x54
42 #define APMU_SDH1 0x58
43 #define APMU_USB 0x5c
44 #define APMU_DISP0 0x4c
45 #define APMU_CCIC0 0x50
46 #define APMU_DFC 0x60
47 #define MPMU_UART_PLL 0x14
48
49 static DEFINE_SPINLOCK(clk_lock);
50
51 static struct mmp_clk_factor_masks uart_factor_masks = {
52 .factor = 2,
53 .num_mask = 0x1fff,
54 .den_mask = 0x1fff,
55 .num_shift = 16,
56 .den_shift = 0,
57 };
58
59 static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
60 {.num = 8125, .den = 1536}, /*14.745MHZ */
61 };
62
63 static const char *uart_parent[] = {"pll1_3_16", "uart_pll"};
64 static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
65 static const char *sdh_parent[] = {"pll1_12", "pll1_13"};
66 static const char *disp_parent[] = {"pll1_2", "pll1_12"};
67 static const char *ccic_parent[] = {"pll1_2", "pll1_12"};
68 static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"};
69
pxa168_clk_init(void)70 void __init pxa168_clk_init(void)
71 {
72 struct clk *clk;
73 struct clk *uart_pll;
74 void __iomem *mpmu_base;
75 void __iomem *apmu_base;
76 void __iomem *apbc_base;
77
78 mpmu_base = ioremap(APB_PHYS_BASE + 0x50000, SZ_4K);
79 if (mpmu_base == NULL) {
80 pr_err("error to ioremap MPMU base\n");
81 return;
82 }
83
84 apmu_base = ioremap(AXI_PHYS_BASE + 0x82800, SZ_4K);
85 if (apmu_base == NULL) {
86 pr_err("error to ioremap APMU base\n");
87 return;
88 }
89
90 apbc_base = ioremap(APB_PHYS_BASE + 0x15000, SZ_4K);
91 if (apbc_base == NULL) {
92 pr_err("error to ioremap APBC base\n");
93 return;
94 }
95
96 clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
97 clk_register_clkdev(clk, "clk32", NULL);
98
99 clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT,
100 26000000);
101 clk_register_clkdev(clk, "vctcxo", NULL);
102
103 clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT,
104 624000000);
105 clk_register_clkdev(clk, "pll1", NULL);
106
107 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
108 CLK_SET_RATE_PARENT, 1, 2);
109 clk_register_clkdev(clk, "pll1_2", NULL);
110
111 clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
112 CLK_SET_RATE_PARENT, 1, 2);
113 clk_register_clkdev(clk, "pll1_4", NULL);
114
115 clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
116 CLK_SET_RATE_PARENT, 1, 2);
117 clk_register_clkdev(clk, "pll1_8", NULL);
118
119 clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
120 CLK_SET_RATE_PARENT, 1, 2);
121 clk_register_clkdev(clk, "pll1_16", NULL);
122
123 clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2",
124 CLK_SET_RATE_PARENT, 1, 3);
125 clk_register_clkdev(clk, "pll1_6", NULL);
126
127 clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
128 CLK_SET_RATE_PARENT, 1, 2);
129 clk_register_clkdev(clk, "pll1_12", NULL);
130
131 clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12",
132 CLK_SET_RATE_PARENT, 1, 2);
133 clk_register_clkdev(clk, "pll1_24", NULL);
134
135 clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24",
136 CLK_SET_RATE_PARENT, 1, 2);
137 clk_register_clkdev(clk, "pll1_48", NULL);
138
139 clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48",
140 CLK_SET_RATE_PARENT, 1, 2);
141 clk_register_clkdev(clk, "pll1_96", NULL);
142
143 clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1",
144 CLK_SET_RATE_PARENT, 1, 13);
145 clk_register_clkdev(clk, "pll1_13", NULL);
146
147 clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1",
148 CLK_SET_RATE_PARENT, 2, 3);
149 clk_register_clkdev(clk, "pll1_13_1_5", NULL);
150
151 clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1",
152 CLK_SET_RATE_PARENT, 2, 3);
153 clk_register_clkdev(clk, "pll1_2_1_5", NULL);
154
155 clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1",
156 CLK_SET_RATE_PARENT, 3, 16);
157 clk_register_clkdev(clk, "pll1_3_16", NULL);
158
159 uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
160 mpmu_base + MPMU_UART_PLL,
161 &uart_factor_masks, uart_factor_tbl,
162 ARRAY_SIZE(uart_factor_tbl), &clk_lock);
163 clk_set_rate(uart_pll, 14745600);
164 clk_register_clkdev(uart_pll, "uart_pll", NULL);
165
166 clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5",
167 apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
168 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
169
170 clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5",
171 apbc_base + APBC_TWSI1, 10, 0, &clk_lock);
172 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
173
174 clk = mmp_clk_register_apbc("gpio", "vctcxo",
175 apbc_base + APBC_GPIO, 10, 0, &clk_lock);
176 clk_register_clkdev(clk, NULL, "mmp-gpio");
177
178 clk = mmp_clk_register_apbc("kpc", "clk32",
179 apbc_base + APBC_KPC, 10, 0, &clk_lock);
180 clk_register_clkdev(clk, NULL, "pxa27x-keypad");
181
182 clk = mmp_clk_register_apbc("rtc", "clk32",
183 apbc_base + APBC_RTC, 10, 0, &clk_lock);
184 clk_register_clkdev(clk, NULL, "sa1100-rtc");
185
186 clk = mmp_clk_register_apbc("pwm0", "pll1_48",
187 apbc_base + APBC_PWM0, 10, 0, &clk_lock);
188 clk_register_clkdev(clk, NULL, "pxa168-pwm.0");
189
190 clk = mmp_clk_register_apbc("pwm1", "pll1_48",
191 apbc_base + APBC_PWM1, 10, 0, &clk_lock);
192 clk_register_clkdev(clk, NULL, "pxa168-pwm.1");
193
194 clk = mmp_clk_register_apbc("pwm2", "pll1_48",
195 apbc_base + APBC_PWM2, 10, 0, &clk_lock);
196 clk_register_clkdev(clk, NULL, "pxa168-pwm.2");
197
198 clk = mmp_clk_register_apbc("pwm3", "pll1_48",
199 apbc_base + APBC_PWM3, 10, 0, &clk_lock);
200 clk_register_clkdev(clk, NULL, "pxa168-pwm.3");
201
202 clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
203 ARRAY_SIZE(uart_parent),
204 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
205 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
206 clk_set_parent(clk, uart_pll);
207 clk_register_clkdev(clk, "uart_mux.0", NULL);
208
209 clk = mmp_clk_register_apbc("uart0", "uart0_mux",
210 apbc_base + APBC_UART0, 10, 0, &clk_lock);
211 clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
212
213 clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
214 ARRAY_SIZE(uart_parent),
215 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
216 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
217 clk_set_parent(clk, uart_pll);
218 clk_register_clkdev(clk, "uart_mux.1", NULL);
219
220 clk = mmp_clk_register_apbc("uart1", "uart1_mux",
221 apbc_base + APBC_UART1, 10, 0, &clk_lock);
222 clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
223
224 clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
225 ARRAY_SIZE(uart_parent),
226 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
227 apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
228 clk_set_parent(clk, uart_pll);
229 clk_register_clkdev(clk, "uart_mux.2", NULL);
230
231 clk = mmp_clk_register_apbc("uart2", "uart2_mux",
232 apbc_base + APBC_UART2, 10, 0, &clk_lock);
233 clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
234
235 clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
236 ARRAY_SIZE(ssp_parent),
237 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
238 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
239 clk_register_clkdev(clk, "uart_mux.0", NULL);
240
241 clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", apbc_base + APBC_SSP0,
242 10, 0, &clk_lock);
243 clk_register_clkdev(clk, NULL, "mmp-ssp.0");
244
245 clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
246 ARRAY_SIZE(ssp_parent),
247 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
248 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
249 clk_register_clkdev(clk, "ssp_mux.1", NULL);
250
251 clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", apbc_base + APBC_SSP1,
252 10, 0, &clk_lock);
253 clk_register_clkdev(clk, NULL, "mmp-ssp.1");
254
255 clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
256 ARRAY_SIZE(ssp_parent),
257 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
258 apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
259 clk_register_clkdev(clk, "ssp_mux.2", NULL);
260
261 clk = mmp_clk_register_apbc("ssp2", "ssp1_mux", apbc_base + APBC_SSP2,
262 10, 0, &clk_lock);
263 clk_register_clkdev(clk, NULL, "mmp-ssp.2");
264
265 clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
266 ARRAY_SIZE(ssp_parent),
267 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
268 apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
269 clk_register_clkdev(clk, "ssp_mux.3", NULL);
270
271 clk = mmp_clk_register_apbc("ssp3", "ssp1_mux", apbc_base + APBC_SSP3,
272 10, 0, &clk_lock);
273 clk_register_clkdev(clk, NULL, "mmp-ssp.3");
274
275 clk = clk_register_mux(NULL, "ssp4_mux", ssp_parent,
276 ARRAY_SIZE(ssp_parent),
277 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
278 apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock);
279 clk_register_clkdev(clk, "ssp_mux.4", NULL);
280
281 clk = mmp_clk_register_apbc("ssp4", "ssp1_mux", apbc_base + APBC_SSP4,
282 10, 0, &clk_lock);
283 clk_register_clkdev(clk, NULL, "mmp-ssp.4");
284
285 clk = mmp_clk_register_apmu("dfc", "pll1_4", apmu_base + APMU_DFC,
286 0x19b, &clk_lock);
287 clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
288
289 clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
290 ARRAY_SIZE(sdh_parent),
291 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
292 apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
293 clk_register_clkdev(clk, "sdh0_mux", NULL);
294
295 clk = mmp_clk_register_apmu("sdh0", "sdh_mux", apmu_base + APMU_SDH0,
296 0x1b, &clk_lock);
297 clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
298
299 clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
300 ARRAY_SIZE(sdh_parent),
301 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
302 apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
303 clk_register_clkdev(clk, "sdh1_mux", NULL);
304
305 clk = mmp_clk_register_apmu("sdh1", "sdh1_mux", apmu_base + APMU_SDH1,
306 0x1b, &clk_lock);
307 clk_register_clkdev(clk, NULL, "sdhci-pxa.1");
308
309 clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB,
310 0x9, &clk_lock);
311 clk_register_clkdev(clk, "usb_clk", NULL);
312
313 clk = mmp_clk_register_apmu("sph", "usb_pll", apmu_base + APMU_USB,
314 0x12, &clk_lock);
315 clk_register_clkdev(clk, "sph_clk", NULL);
316
317 clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
318 ARRAY_SIZE(disp_parent),
319 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
320 apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
321 clk_register_clkdev(clk, "disp_mux.0", NULL);
322
323 clk = mmp_clk_register_apmu("disp0", "disp0_mux",
324 apmu_base + APMU_DISP0, 0x1b, &clk_lock);
325 clk_register_clkdev(clk, "fnclk", "mmp-disp.0");
326
327 clk = mmp_clk_register_apmu("disp0_hclk", "disp0_mux",
328 apmu_base + APMU_DISP0, 0x24, &clk_lock);
329 clk_register_clkdev(clk, "hclk", "mmp-disp.0");
330
331 clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
332 ARRAY_SIZE(ccic_parent),
333 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
334 apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
335 clk_register_clkdev(clk, "ccic_mux.0", NULL);
336
337 clk = mmp_clk_register_apmu("ccic0", "ccic0_mux",
338 apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
339 clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
340
341 clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
342 ARRAY_SIZE(ccic_phy_parent),
343 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
344 apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
345 clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
346
347 clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
348 apmu_base + APMU_CCIC0, 0x24, &clk_lock);
349 clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
350
351 clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
352 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
353 10, 5, 0, &clk_lock);
354 clk_register_clkdev(clk, "sphyclk_div", NULL);
355
356 clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
357 apmu_base + APMU_CCIC0, 0x300, &clk_lock);
358 clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
359 }
360