Lines Matching refs:ath10k_pci_write32

66 	ath10k_pci_write32(ar, ce_ctrl_addr + DST_WR_INDEX_ADDRESS, n);  in ath10k_ce_dest_ring_write_index_set()
79 	ath10k_pci_write32(ar, ce_ctrl_addr + SR_WR_INDEX_ADDRESS, n);  in ath10k_ce_src_ring_write_index_set()
98 	ath10k_pci_write32(ar, ce_ctrl_addr + SR_BA_ADDRESS, addr);  in ath10k_ce_src_ring_base_addr_set()
105 	ath10k_pci_write32(ar, ce_ctrl_addr + SR_SIZE_ADDRESS, n);  in ath10k_ce_src_ring_size_set()
115 	ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,  in ath10k_ce_src_ring_dmax_set()
126 	ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,  in ath10k_ce_src_ring_byte_swap_set()
137 	ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,  in ath10k_ce_dest_ring_byte_swap_set()
152 	ath10k_pci_write32(ar, ce_ctrl_addr + DR_BA_ADDRESS, addr);  in ath10k_ce_dest_ring_base_addr_set()
159 	ath10k_pci_write32(ar, ce_ctrl_addr + DR_SIZE_ADDRESS, n);  in ath10k_ce_dest_ring_size_set()
168 	ath10k_pci_write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS,  in ath10k_ce_src_ring_highmark_set()
179 	ath10k_pci_write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS,  in ath10k_ce_src_ring_lowmark_set()
190 	ath10k_pci_write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS,  in ath10k_ce_dest_ring_highmark_set()
201 	ath10k_pci_write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS,  in ath10k_ce_dest_ring_lowmark_set()
212 	ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,  in ath10k_ce_copy_complete_inter_enable()
222 	ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,  in ath10k_ce_copy_complete_intr_disable()
232 	ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,  in ath10k_ce_watermark_intr_disable()
242 	ath10k_pci_write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS,  in ath10k_ce_error_intr_enable()
252 	ath10k_pci_write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS,  in ath10k_ce_error_intr_disable()
260 	ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IS_ADDRESS, mask);  in ath10k_ce_engine_int_status_clear()