| /arch/metag/tbx/ |
| D | tbictx.S | 156 D SETL [A0.2++],AC0.0,AC1.0 /* Save ACx.0 lower 32-bits */ label
158 D SETL [A0.2++],D0AR.0,D1AR.0 /* Save DSP RAM registers */ label
159 D SETL [A0.2++],D0AR.1,D1AR.1 label
160 D SETL [A0.2++],D0AW.0,D1AW.0 label
161 D SETL [A0.2++],D0AW.1,D1AW.1 label
162 D SETL [A0.2++],D0BR.0,D1BR.0 label
163 D SETL [A0.2++],D0BR.1,D1BR.1 label
164 D SETL [A0.2++],D0BW.0,D1BW.0 label
165 D SETL [A0.2++],D0BW.1,D1BW.1 label
166 D SETL [A0.2++],D0ARI.0,D1ARI.0 label
[all …]
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| /arch/cris/include/arch-v32/arch/hwregs/iop/ |
| D | iop_mpu_macros.h | 96 #define MPU_ADD_RRR(S,N,D) (0x4000008C | ((S & ((1 << 5) - 1)) << 16)\ argument
100 #define MPU_ADD_RRS(S,N,D) (0x4000048C | ((S & ((1 << 5) - 1)) << 16)\ argument
104 #define MPU_ADD_RSR(S,N,D) (0x4000018C | ((S & ((1 << 5) - 1)) << 16)\ argument
108 #define MPU_ADD_RSS(S,N,D) (0x4000058C | ((S & ((1 << 5) - 1)) << 16)\ argument
112 #define MPU_ADD_SRR(S,N,D) (0x4000028C | ((S & ((1 << 5) - 1)) << 16)\ argument
116 #define MPU_ADD_SRS(S,N,D) (0x4000068C | ((S & ((1 << 5) - 1)) << 16)\ argument
120 #define MPU_ADD_SSR(S,N,D) (0x4000038C | ((S & ((1 << 5) - 1)) << 16)\ argument
124 #define MPU_ADD_SSS(S,N,D) (0x4000078C | ((S & ((1 << 5) - 1)) << 16)\ argument
128 #define MPU_ADDQ_RIR(S,N,D) (0x10000000 | ((S & ((1 << 5) - 1)) << 16)\ argument
132 #define MPU_ADDQ_IRR(S,N,D) (0x10000000 | ((S & ((1 << 16) - 1)) << 0)\ argument
[all …]
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| /arch/cris/arch-v10/mm/ |
| D | fault.c | 23 #define D(x) x macro
25 #define D(x) macro
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| D | tlb.c | 17 #define D(x) macro
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| /arch/cris/mm/ |
| D | fault.c | 22 #define D(x) x macro
24 #define D(x) macro
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| D | tlb.c | 14 #define D(x) macro
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| /arch/cris/kernel/ |
| D | time.c | 35 #define D(x) macro
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| /arch/mips/cavium-octeon/executive/ |
| D | cvmx-l2c.c | 525 uint64_t D:1; /* Line dirty */ member
542 uint64_t D:1; /* Line dirty */ member
559 uint64_t D:1; /* Line dirty */ member
576 uint64_t D:1; /* Line dirty */ member
593 uint64_t D:1; /* Line dirty */ member
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| /arch/frv/kernel/ |
| D | irq.c | 38 #define set_IRR(N,A,B,C,D) __set_IRR(N, (A << 28) | (B << 24) | (C << 20) | (D << 16)) argument
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| /arch/ia64/lib/ |
| D | memcpy_mck.S | 64 #define D (C + 1) macro
554 #define D r22 macro
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| D | copy_page_mck.S | 96 #define D (C + 3) macro
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| /arch/x86/crypto/sha-mb/ |
| D | sha1_x8_avx2.S | 246 D = %ymm3 define
275 D = C define
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| /arch/sparc/crypto/ |
| D | sha512_glue.c | 137 u8 D[64]; in sha384_sparc64_final() local
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| D | sha256_glue.c | 133 u8 D[SHA256_DIGEST_SIZE]; in sha224_sparc64_final() local
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| /arch/mips/cavium-octeon/crypto/ |
| D | octeon-sha512.c | 218 u8 D[64]; in octeon_sha384_final() local
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| D | octeon-sha256.c | 203 u8 D[SHA256_DIGEST_SIZE]; in octeon_sha224_final() local
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| /arch/powerpc/crypto/ |
| D | sha256-spe-glue.c | 185 u32 D[SHA256_DIGEST_SIZE >> 2]; in ppc_spe_sha224_final() local
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| /arch/x86/crypto/ |
| D | sha1_avx2_x86_64_asm.S | 103 .set D, REG_D define
325 .set D, C define
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| D | sha1_ssse3_asm.S | 199 .set D, REG_D define
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| /arch/frv/include/asm/ |
| D | gpio-regs.h | 58 #define GPDR_GPIO_DIR(X,D) ((D) << (X)) argument
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| /arch/cris/arch-v10/drivers/ |
| D | i2c.c | 34 #define D(x) macro
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| D | eeprom.c | 35 #define D(x) macro
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| /arch/powerpc/math-emu/ |
| D | math.c | 153 #define D 5 macro
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| /arch/cris/arch-v32/mach-a3/ |
| D | arbiter.c | 52 #define D(x) macro
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| /arch/mips/include/asm/octeon/ |
| D | cvmx-l2c.h | 59 uint64_t D:1; /* Line dirty */ member
|