Searched refs:BFIN_IRQ (Results 1 – 11 of 11) sorted by relevance
14 #define IRQ_SEC_ERR BFIN_IRQ(0) /* SEC Error */15 #define IRQ_CGU_EVT BFIN_IRQ(1) /* CGU Event */16 #define IRQ_WATCH0 BFIN_IRQ(2) /* Watchdog0 Interrupt */17 #define IRQ_WATCH1 BFIN_IRQ(3) /* Watchdog1 Interrupt */18 #define IRQ_L2CTL0_ECC_ERR BFIN_IRQ(4) /* L2 ECC Error */19 #define IRQ_L2CTL0_ECC_WARN BFIN_IRQ(5) /* L2 ECC Waring */20 #define IRQ_C0_DBL_FAULT BFIN_IRQ(6) /* Core 0 Double Fault */21 #define IRQ_C1_DBL_FAULT BFIN_IRQ(7) /* Core 1 Double Fault */22 #define IRQ_C0_HW_ERR BFIN_IRQ(8) /* Core 0 Hardware Error */23 #define IRQ_C1_HW_ERR BFIN_IRQ(9) /* Core 1 Hardware Error */[all …]
14 #define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */15 #define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */16 #define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error */17 #define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Status */18 #define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Status */19 #define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status */20 #define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status */21 #define IRQ_RTC BFIN_IRQ(7) /* RTC */22 #define IRQ_PPI BFIN_IRQ(8) /* DMA Channel 0 (PPI) */23 #define IRQ_SPORT0_RX BFIN_IRQ(9) /* DMA 1 Channel (SPORT0 RX) */[all …]
14 #define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */15 #define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */16 #define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */17 #define IRQ_DMAR1_BLK BFIN_IRQ(3) /* DMAR1 Block Interrupt */18 #define IRQ_DMAR0_OVR BFIN_IRQ(4) /* DMAR0 Overflow Error */19 #define IRQ_DMAR1_OVR BFIN_IRQ(5) /* DMAR1 Overflow Error */20 #define IRQ_PPI_ERROR BFIN_IRQ(6) /* PPI Error */21 #define IRQ_MAC_ERROR BFIN_IRQ(7) /* MAC Status */22 #define IRQ_SPORT0_ERROR BFIN_IRQ(8) /* SPORT0 Status */23 #define IRQ_SPORT1_ERROR BFIN_IRQ(9) /* SPORT1 Status */[all …]
14 #define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */15 #define IRQ_DMA1_ERROR BFIN_IRQ(1) /* DMA1 Error (general) */17 #define IRQ_DMA2_ERROR BFIN_IRQ(2) /* DMA2 Error (general) */18 #define IRQ_IMDMA_ERROR BFIN_IRQ(3) /* IMDMA Error Interrupt */19 #define IRQ_PPI1_ERROR BFIN_IRQ(4) /* PPI1 Error Interrupt */21 #define IRQ_PPI2_ERROR BFIN_IRQ(5) /* PPI2 Error Interrupt */22 #define IRQ_SPORT0_ERROR BFIN_IRQ(6) /* SPORT0 Error Interrupt */23 #define IRQ_SPORT1_ERROR BFIN_IRQ(7) /* SPORT1 Error Interrupt */24 #define IRQ_SPI_ERROR BFIN_IRQ(8) /* SPI Error Interrupt */25 #define IRQ_UART_ERROR BFIN_IRQ(9) /* UART Error Interrupt */[all …]
14 #define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */15 #define IRQ_DMA_ERROR BFIN_IRQ(1) /* DMA Error (general) */16 #define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error Interrupt */17 #define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Error Interrupt */18 #define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Error Interrupt */19 #define IRQ_SPI_ERROR BFIN_IRQ(5) /* SPI Error Interrupt */20 #define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART Error Interrupt */21 #define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */22 #define IRQ_PPI BFIN_IRQ(8) /* DMA0 Interrupt (PPI) */23 #define IRQ_SPORT0_RX BFIN_IRQ(9) /* DMA1 Interrupt (SPORT0 RX) */[all …]
14 #define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */15 #define IRQ_DMA_ERROR BFIN_IRQ(1) /* DMA Error (general) */16 #define IRQ_GENERIC_ERROR BFIN_IRQ(2) /* GENERIC Error Interrupt */17 #define IRQ_RTC BFIN_IRQ(3) /* RTC Interrupt */18 #define IRQ_PPI BFIN_IRQ(4) /* DMA0 Interrupt (PPI) */19 #define IRQ_SPORT0_RX BFIN_IRQ(5) /* DMA3 Interrupt (SPORT0 RX) */20 #define IRQ_SPORT0_TX BFIN_IRQ(6) /* DMA4 Interrupt (SPORT0 TX) */21 #define IRQ_SPORT1_RX BFIN_IRQ(7) /* DMA5 Interrupt (SPORT1 RX) */22 #define IRQ_SPORT1_TX BFIN_IRQ(8) /* DMA6 Interrupt (SPORT1 TX) */23 #define IRQ_TWI BFIN_IRQ(9) /* TWI Interrupt */[all …]
14 #define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */15 #define IRQ_DMAC0_ERROR BFIN_IRQ(1) /* DMAC0 Status Interrupt */16 #define IRQ_EPPI0_ERROR BFIN_IRQ(2) /* EPPI0 Error Interrupt */17 #define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Error Interrupt */18 #define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Error Interrupt */19 #define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status(Error) Interrupt */20 #define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status(Error) Interrupt */21 #define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */22 #define IRQ_EPPI0 BFIN_IRQ(8) /* EPPI0 Interrupt (DMA12) */23 #define IRQ_SPORT0_RX BFIN_IRQ(9) /* SPORT0 RX Interrupt (DMA0) */[all …]
39 #define IRQ_UART2_RX BFIN_IRQ(37) /* UART2 RX USE EPP1 (DMA13) Interrupt */41 #define IRQ_UART2_TX BFIN_IRQ(38) /* UART2 RX USE EPP1 (DMA14) Interrupt */44 #define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */46 #define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */51 #define IRQ_UART3_RX BFIN_IRQ(64) /* UART3 RX USE PIXC IN0 (DMA15) Interrupt */53 #define IRQ_UART3_TX BFIN_IRQ(65) /* UART3 TX USE PIXC IN1 (DMA16) Interrupt */56 #define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */58 #define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */
53 #define BFIN_IRQ(x) ((x) + IVG7) macro
401 for (i = 0; i < SYS_IRQS - BFIN_IRQ(0); i++) { in bfin_sec_set_priority()1182 } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) { in init_arch_irq()1242 return BFIN_IRQ(bfin_read_SEC_SCI(0, SEC_CSID)); in vec_to_irq()1267 if (irq >= BFIN_IRQ(0)) in __ipipe_get_irq_priority()