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Searched refs:ICACHE_REFILLS_WORKAROUND_WAR (Results 1 – 15 of 15) sorted by relevance

/arch/mips/include/asm/
Dwar.h217 #ifndef ICACHE_REFILLS_WORKAROUND_WAR
218 #error Check setting of ICACHE_REFILLS_WORKAROUND_WAR for your platform
/arch/mips/include/asm/mach-malta/
Dwar.h20 #define ICACHE_REFILLS_WORKAROUND_WAR 1 macro
/arch/mips/include/asm/mach-ip22/
Dwar.h24 #define ICACHE_REFILLS_WORKAROUND_WAR 0 macro
/arch/mips/include/asm/mach-ip32/
Dwar.h20 #define ICACHE_REFILLS_WORKAROUND_WAR 1 macro
/arch/mips/include/asm/mach-ip27/
Dwar.h20 #define ICACHE_REFILLS_WORKAROUND_WAR 0 macro
/arch/mips/include/asm/mach-ip28/
Dwar.h20 #define ICACHE_REFILLS_WORKAROUND_WAR 0 macro
/arch/mips/include/asm/mach-generic/
Dwar.h20 #define ICACHE_REFILLS_WORKAROUND_WAR 0 macro
/arch/mips/include/asm/mach-rc32434/
Dwar.h20 #define ICACHE_REFILLS_WORKAROUND_WAR 0 macro
/arch/mips/include/asm/mach-sead3/
Dwar.h20 #define ICACHE_REFILLS_WORKAROUND_WAR 1 macro
/arch/mips/include/asm/mach-rm/
Dwar.h24 #define ICACHE_REFILLS_WORKAROUND_WAR 0 macro
/arch/mips/include/asm/mach-tx49xx/
Dwar.h20 #define ICACHE_REFILLS_WORKAROUND_WAR 0 macro
/arch/mips/include/asm/mach-cavium-octeon/
Dwar.h21 #define ICACHE_REFILLS_WORKAROUND_WAR 0 macro
/arch/mips/include/asm/mach-pmcs-msp71xx/
Dwar.h20 #define ICACHE_REFILLS_WORKAROUND_WAR 0 macro
/arch/mips/include/asm/mach-sibyte/
Dwar.h35 #define ICACHE_REFILLS_WORKAROUND_WAR 0 macro
/arch/mips/kernel/
Dsignal.c539 …return (void __user *)((sp - frame_size) & (ICACHE_REFILLS_WORKAROUND_WAR ? ~(cpu_icache_line_size… in get_sigframe()