| /arch/mips/include/asm/ |
| D | spinlock.h | 68 if (R10000_LLSC_WAR) { in arch_spin_lock()
153 if (R10000_LLSC_WAR) { in arch_spin_trylock()
233 if (R10000_LLSC_WAR) { in arch_read_lock()
268 if (R10000_LLSC_WAR) { in arch_read_unlock()
294 if (R10000_LLSC_WAR) { in arch_write_lock()
340 if (R10000_LLSC_WAR) { in arch_read_trylock()
384 if (R10000_LLSC_WAR) { in arch_write_trylock()
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| D | bitops.h | 74 if (kernel_uses_llsc && R10000_LLSC_WAR) { in set_bit()
126 if (kernel_uses_llsc && R10000_LLSC_WAR) { in clear_bit()
189 if (kernel_uses_llsc && R10000_LLSC_WAR) { in change_bit()
236 if (kernel_uses_llsc && R10000_LLSC_WAR) { in test_and_set_bit()
290 if (kernel_uses_llsc && R10000_LLSC_WAR) { in test_and_set_bit_lock()
345 if (kernel_uses_llsc && R10000_LLSC_WAR) { in test_and_clear_bit()
419 if (kernel_uses_llsc && R10000_LLSC_WAR) { in test_and_change_bit()
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| D | war.h | 225 #ifndef R10000_LLSC_WAR
226 #error Check setting of R10000_LLSC_WAR for your platform
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| D | atomic.h | 47 if (kernel_uses_llsc && R10000_LLSC_WAR) { \
88 if (kernel_uses_llsc && R10000_LLSC_WAR) { \
162 if (kernel_uses_llsc && R10000_LLSC_WAR) { in atomic_sub_if_positive()
330 if (kernel_uses_llsc && R10000_LLSC_WAR) { \
371 if (kernel_uses_llsc && R10000_LLSC_WAR) { \
446 if (kernel_uses_llsc && R10000_LLSC_WAR) { in atomic64_sub_if_positive()
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| D | cmpxchg.h | 22 if (kernel_uses_llsc && R10000_LLSC_WAR) { in __xchg_u32()
75 if (kernel_uses_llsc && R10000_LLSC_WAR) { in __xchg_u64()
145 if (kernel_uses_llsc && R10000_LLSC_WAR) { \
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| D | futex.h | 23 if (cpu_has_llsc && R10000_LLSC_WAR) { \
135 if (cpu_has_llsc && R10000_LLSC_WAR) { in futex_atomic_cmpxchg_inatomic()
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| D | local.h | 33 if (kernel_uses_llsc && R10000_LLSC_WAR) { in local_add_return()
78 if (kernel_uses_llsc && R10000_LLSC_WAR) { in local_sub_return()
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| /arch/mips/include/asm/mach-pmcs-msp71xx/ |
| D | msp_regops.h | 55 #ifndef R10000_LLSC_WAR
56 #define R10000_LLSC_WAR 0 macro
59 #if R10000_LLSC_WAR == 1
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| D | war.h | 21 #define R10000_LLSC_WAR 0 macro
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| /arch/mips/include/asm/mach-malta/ |
| D | war.h | 21 #define R10000_LLSC_WAR 0 macro
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| /arch/mips/include/asm/mach-ip22/ |
| D | war.h | 25 #define R10000_LLSC_WAR 0 macro
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| /arch/mips/include/asm/mach-ip32/ |
| D | war.h | 21 #define R10000_LLSC_WAR 0 macro
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| /arch/mips/include/asm/mach-ip27/ |
| D | war.h | 21 #define R10000_LLSC_WAR 1 macro
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| /arch/mips/include/asm/mach-ip28/ |
| D | war.h | 21 #define R10000_LLSC_WAR 1 macro
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| /arch/mips/include/asm/mach-generic/ |
| D | war.h | 21 #define R10000_LLSC_WAR 0 macro
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| /arch/mips/include/asm/mach-rc32434/ |
| D | war.h | 21 #define R10000_LLSC_WAR 0 macro
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| /arch/mips/include/asm/mach-sead3/ |
| D | war.h | 21 #define R10000_LLSC_WAR 0 macro
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| /arch/mips/include/asm/mach-rm/ |
| D | war.h | 25 #define R10000_LLSC_WAR 0 macro
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| /arch/mips/include/asm/mach-tx49xx/ |
| D | war.h | 21 #define R10000_LLSC_WAR 0 macro
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| /arch/mips/include/asm/mach-cavium-octeon/ |
| D | war.h | 22 #define R10000_LLSC_WAR 0 macro
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| /arch/mips/include/asm/mach-sibyte/ |
| D | war.h | 36 #define R10000_LLSC_WAR 0 macro
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| /arch/mips/kernel/ |
| D | syscall.c | 112 if (cpu_has_llsc && R10000_LLSC_WAR) { in mips_atomic_set()
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| /arch/mips/mm/ |
| D | tlbex.c | 90 return R10000_LLSC_WAR; in r10000_llsc_war()
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