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Searched refs:R5432_CP0_INTERRUPT_WAR (Results 1 – 15 of 15) sorted by relevance

/arch/mips/include/asm/
Dwar.h140 #ifndef R5432_CP0_INTERRUPT_WAR
141 #error Check setting of R5432_CP0_INTERRUPT_WAR for your platform
/arch/mips/include/asm/mach-malta/
Dwar.h14 #define R5432_CP0_INTERRUPT_WAR 0 macro
/arch/mips/include/asm/mach-ip22/
Dwar.h18 #define R5432_CP0_INTERRUPT_WAR 0 macro
/arch/mips/include/asm/mach-ip32/
Dwar.h14 #define R5432_CP0_INTERRUPT_WAR 0 macro
/arch/mips/include/asm/mach-ip27/
Dwar.h14 #define R5432_CP0_INTERRUPT_WAR 0 macro
/arch/mips/include/asm/mach-ip28/
Dwar.h14 #define R5432_CP0_INTERRUPT_WAR 0 macro
/arch/mips/include/asm/mach-generic/
Dwar.h14 #define R5432_CP0_INTERRUPT_WAR 0 macro
/arch/mips/include/asm/mach-rc32434/
Dwar.h14 #define R5432_CP0_INTERRUPT_WAR 0 macro
/arch/mips/include/asm/mach-sead3/
Dwar.h14 #define R5432_CP0_INTERRUPT_WAR 0 macro
/arch/mips/include/asm/mach-rm/
Dwar.h18 #define R5432_CP0_INTERRUPT_WAR 0 macro
/arch/mips/include/asm/mach-tx49xx/
Dwar.h14 #define R5432_CP0_INTERRUPT_WAR 0 macro
/arch/mips/include/asm/mach-cavium-octeon/
Dwar.h15 #define R5432_CP0_INTERRUPT_WAR 0 macro
/arch/mips/include/asm/mach-pmcs-msp71xx/
Dwar.h14 #define R5432_CP0_INTERRUPT_WAR 0 macro
/arch/mips/include/asm/mach-sibyte/
Dwar.h14 #define R5432_CP0_INTERRUPT_WAR 0 macro
/arch/mips/kernel/
Dgenex.S35 #if R5432_CP0_INTERRUPT_WAR