Searched refs:SPI (Results 1 – 25 of 54) sorted by relevance
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33 bool "SSP/SPI dummy chip"34 select SPI39 SPI device to be used for loopback tests. Regularly used40 to test reference designs. If you're not testing SPI,42 SPI framework and ARM PL022 support.
193 select SPI197 # independent of MMC_SPI, so we'll keep SPI non-dependent on the199 # for the board-info file until a separate non-MMC SPI board file202 # configure non-MMC SPI ports together with MMC_SPI ports (if multiple203 # SPI ports are enabled).211 SPI master controller on Axis ETRAX FS and later. The219 This enables using GPIO pins port as a SPI master controller224 tristate "SPI using synchronous serial port 0 (sser0)"232 or for devices using the SPI protocol on that port. Say m if you237 tristate "SPI using synchronous serial port 1 (sser1)"[all …]
121 label = "SPI Flash U-Boot Image";128 label = "SPI Flash DTB Image";134 label = "SPI Flash Linux Kernel Image";140 label = "SPI Flash Compressed RFSImage";146 label = "SPI Flash JFFS2 RFS";
139 label = "SPI U-Boot Image";146 label = "SPI DTB Image";152 label = "SPI Linux Kernel Image";158 label = "SPI Compressed RFS Image";164 label = "SPI JFFS2 RFS";
165 label = "SPI (RO) U-Boot Image";172 label = "SPI (RO) DTB Image";179 label = "SPI (RO) Linux Kernel Image";186 label = "SPI (RO) Compressed RFS Image";193 label = "SPI (RW) JFFS2 RFS";
161 label = "SPI U-Boot Image";168 label = "SPI DTB Image";174 label = "SPI Linux Kernel Image";180 label = "SPI Compressed RFS Image";186 label = "SPI JFFS2 RFS";
160 label = "SPI Flash U-Boot Image";167 label = "SPI Flash DTB Image";173 label = "SPI Flash Linux Kernel Image";179 label = "SPI Flash Compressed RFSImage";185 label = "SPI Flash JFFS2 RFS";
178 label = "SPI Flash U-Boot Image";185 label = "SPI Flash DTB Image";191 label = "SPI Flash Linux Kernel Image";197 label = "SPI Flash RFS Image";
166 label = "SPI U-Boot Image";173 label = "SPI DTB Image";179 label = "SPI Linux Kernel Image";185 label = "SPI File System Image";
17 int "SPI ERROR"52 int "DMA5 (SPI)"
74 All the signals for the second SPI controller are available on76 here to configure that SPI controller.
372 SPI, enumerator446 INTC_GROUP(SPI, HSPI, RSPI, QSPI),493 SPI, /* HSPI, RSPI, QSPI */515 { VIN0, SPI, _2DG, LBSCATA } },
366 TMU, DMAC, I2S, SRC, GFX3D, SPI, SCIF, BBDMAC, enumerator425 INTC_GROUP(SPI, SPI0, SPI1),435 { 0, BBDMAC, ADC, SCIF, SPI, EXBUS_ATA, GFX3D, GFX2D,446 { 0xffe00014, 0, 32, 8, /* INT2PRI5 */ { 0, GFX3D, EXBUS_ATA, SPI } },
46 int "SPI Error Interrupt"103 int "DMA2 4 (SPI)"
17 int "IRQ_ERROR: PPI CAN MAC SPORT0 SPORT1 SPI UART0 UART1"
62 * On the first generation boards, this SSP/SPI port was connected
186 /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */197 /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
48 * A NAND flash is used instead of an SPI flash for
152 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
390 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x0b0b0 /* SPI CS0 */391 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 /* SPI CS1 */
190 SPI controller 0196 SPI controller 1202 SPI controller 2
162 bool "I2C/SPI relocation patch"167 bool "I2C/SPI/SMC1 relocation patch"
308 /* PSC4 in SPI mode */332 /* PSC5 in SPI mode */
82 printf "PSW[0x%08lX] CBR[0x%08lX] SPI[0x%08lX] SPU[0x%08lX]\n",$psw,$cbr,$spi,$spu
417 char buf[32], *_buf = REGS_STR_PFX(buf, SPI, num); in bfin_debug_mmrs_spi()426 #define SPI(num) bfin_debug_mmrs_spi(parent, SPI##num##_REGBASE, num) macro1523 SPI(0); in bfin_debug_mmrs_init()1526 SPI(1); in bfin_debug_mmrs_init()1529 SPI(2); in bfin_debug_mmrs_init()