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1 /*
2  * SH7770 Setup
3  *
4  *  Copyright (C) 2006 - 2008  Paul Mundt
5  *
6  * This file is subject to the terms and conditions of the GNU General Public
7  * License.  See the file "COPYING" in the main directory of this archive
8  * for more details.
9  */
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/serial_sci.h>
14 #include <linux/sh_timer.h>
15 #include <linux/sh_intc.h>
16 #include <linux/io.h>
17 
18 static struct plat_sci_port scif0_platform_data = {
19 	.flags		= UPF_BOOT_AUTOCONF,
20 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
21 	.type		= PORT_SCIF,
22 };
23 
24 static struct resource scif0_resources[] = {
25 	DEFINE_RES_MEM(0xff923000, 0x100),
26 	DEFINE_RES_IRQ(evt2irq(0x9a0)),
27 };
28 
29 static struct platform_device scif0_device = {
30 	.name		= "sh-sci",
31 	.id		= 0,
32 	.resource	= scif0_resources,
33 	.num_resources	= ARRAY_SIZE(scif0_resources),
34 	.dev		= {
35 		.platform_data	= &scif0_platform_data,
36 	},
37 };
38 
39 static struct plat_sci_port scif1_platform_data = {
40 	.flags		= UPF_BOOT_AUTOCONF,
41 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
42 	.type		= PORT_SCIF,
43 };
44 
45 static struct resource scif1_resources[] = {
46 	DEFINE_RES_MEM(0xff924000, 0x100),
47 	DEFINE_RES_IRQ(evt2irq(0x9c0)),
48 };
49 
50 static struct platform_device scif1_device = {
51 	.name		= "sh-sci",
52 	.id		= 1,
53 	.resource	= scif1_resources,
54 	.num_resources	= ARRAY_SIZE(scif1_resources),
55 	.dev		= {
56 		.platform_data	= &scif1_platform_data,
57 	},
58 };
59 
60 static struct plat_sci_port scif2_platform_data = {
61 	.flags		= UPF_BOOT_AUTOCONF,
62 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
63 	.type		= PORT_SCIF,
64 };
65 
66 static struct resource scif2_resources[] = {
67 	DEFINE_RES_MEM(0xff925000, 0x100),
68 	DEFINE_RES_IRQ(evt2irq(0x9e0)),
69 };
70 
71 static struct platform_device scif2_device = {
72 	.name		= "sh-sci",
73 	.id		= 2,
74 	.resource	= scif2_resources,
75 	.num_resources	= ARRAY_SIZE(scif2_resources),
76 	.dev		= {
77 		.platform_data	= &scif2_platform_data,
78 	},
79 };
80 
81 static struct plat_sci_port scif3_platform_data = {
82 	.flags		= UPF_BOOT_AUTOCONF,
83 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
84 	.type		= PORT_SCIF,
85 };
86 
87 static struct resource scif3_resources[] = {
88 	DEFINE_RES_MEM(0xff926000, 0x100),
89 	DEFINE_RES_IRQ(evt2irq(0xa00)),
90 };
91 
92 static struct platform_device scif3_device = {
93 	.name		= "sh-sci",
94 	.id		= 3,
95 	.resource	= scif3_resources,
96 	.num_resources	= ARRAY_SIZE(scif3_resources),
97 	.dev		= {
98 		.platform_data	= &scif3_platform_data,
99 	},
100 };
101 
102 static struct plat_sci_port scif4_platform_data = {
103 	.flags		= UPF_BOOT_AUTOCONF,
104 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
105 	.type		= PORT_SCIF,
106 };
107 
108 static struct resource scif4_resources[] = {
109 	DEFINE_RES_MEM(0xff927000, 0x100),
110 	DEFINE_RES_IRQ(evt2irq(0xa20)),
111 };
112 
113 static struct platform_device scif4_device = {
114 	.name		= "sh-sci",
115 	.id		= 4,
116 	.resource	= scif4_resources,
117 	.num_resources	= ARRAY_SIZE(scif4_resources),
118 	.dev		= {
119 		.platform_data	= &scif4_platform_data,
120 	},
121 };
122 
123 static struct plat_sci_port scif5_platform_data = {
124 	.flags		= UPF_BOOT_AUTOCONF,
125 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
126 	.type		= PORT_SCIF,
127 };
128 
129 static struct resource scif5_resources[] = {
130 	DEFINE_RES_MEM(0xff928000, 0x100),
131 	DEFINE_RES_IRQ(evt2irq(0xa40)),
132 };
133 
134 static struct platform_device scif5_device = {
135 	.name		= "sh-sci",
136 	.id		= 5,
137 	.resource	= scif5_resources,
138 	.num_resources	= ARRAY_SIZE(scif5_resources),
139 	.dev		= {
140 		.platform_data	= &scif5_platform_data,
141 	},
142 };
143 
144 static struct plat_sci_port scif6_platform_data = {
145 	.flags		= UPF_BOOT_AUTOCONF,
146 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
147 	.type		= PORT_SCIF,
148 };
149 
150 static struct resource scif6_resources[] = {
151 	DEFINE_RES_MEM(0xff929000, 0x100),
152 	DEFINE_RES_IRQ(evt2irq(0xa60)),
153 };
154 
155 static struct platform_device scif6_device = {
156 	.name		= "sh-sci",
157 	.id		= 6,
158 	.resource	= scif6_resources,
159 	.num_resources	= ARRAY_SIZE(scif6_resources),
160 	.dev		= {
161 		.platform_data	= &scif6_platform_data,
162 	},
163 };
164 
165 static struct plat_sci_port scif7_platform_data = {
166 	.flags		= UPF_BOOT_AUTOCONF,
167 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
168 	.type		= PORT_SCIF,
169 };
170 
171 static struct resource scif7_resources[] = {
172 	DEFINE_RES_MEM(0xff92a000, 0x100),
173 	DEFINE_RES_IRQ(evt2irq(0xa80)),
174 };
175 
176 static struct platform_device scif7_device = {
177 	.name		= "sh-sci",
178 	.id		= 7,
179 	.resource	= scif7_resources,
180 	.num_resources	= ARRAY_SIZE(scif7_resources),
181 	.dev		= {
182 		.platform_data	= &scif7_platform_data,
183 	},
184 };
185 
186 static struct plat_sci_port scif8_platform_data = {
187 	.flags		= UPF_BOOT_AUTOCONF,
188 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
189 	.type		= PORT_SCIF,
190 };
191 
192 static struct resource scif8_resources[] = {
193 	DEFINE_RES_MEM(0xff92b000, 0x100),
194 	DEFINE_RES_IRQ(evt2irq(0xaa0)),
195 };
196 
197 static struct platform_device scif8_device = {
198 	.name		= "sh-sci",
199 	.id		= 8,
200 	.resource	= scif8_resources,
201 	.num_resources	= ARRAY_SIZE(scif8_resources),
202 	.dev		= {
203 		.platform_data	= &scif8_platform_data,
204 	},
205 };
206 
207 static struct plat_sci_port scif9_platform_data = {
208 	.flags		= UPF_BOOT_AUTOCONF,
209 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
210 	.type		= PORT_SCIF,
211 };
212 
213 static struct resource scif9_resources[] = {
214 	DEFINE_RES_MEM(0xff92c000, 0x100),
215 	DEFINE_RES_IRQ(evt2irq(0xac0)),
216 };
217 
218 static struct platform_device scif9_device = {
219 	.name		= "sh-sci",
220 	.id		= 9,
221 	.resource	= scif9_resources,
222 	.num_resources	= ARRAY_SIZE(scif9_resources),
223 	.dev		= {
224 		.platform_data	= &scif9_platform_data,
225 	},
226 };
227 
228 static struct sh_timer_config tmu0_platform_data = {
229 	.channels_mask = 7,
230 };
231 
232 static struct resource tmu0_resources[] = {
233 	DEFINE_RES_MEM(0xffd80000, 0x30),
234 	DEFINE_RES_IRQ(evt2irq(0x400)),
235 	DEFINE_RES_IRQ(evt2irq(0x420)),
236 	DEFINE_RES_IRQ(evt2irq(0x440)),
237 };
238 
239 static struct platform_device tmu0_device = {
240 	.name		= "sh-tmu",
241 	.id		= 0,
242 	.dev = {
243 		.platform_data	= &tmu0_platform_data,
244 	},
245 	.resource	= tmu0_resources,
246 	.num_resources	= ARRAY_SIZE(tmu0_resources),
247 };
248 
249 static struct sh_timer_config tmu1_platform_data = {
250 	.channels_mask = 7,
251 };
252 
253 static struct resource tmu1_resources[] = {
254 	DEFINE_RES_MEM(0xffd81000, 0x30),
255 	DEFINE_RES_IRQ(evt2irq(0x460)),
256 	DEFINE_RES_IRQ(evt2irq(0x480)),
257 	DEFINE_RES_IRQ(evt2irq(0x4a0)),
258 };
259 
260 static struct platform_device tmu1_device = {
261 	.name		= "sh-tmu",
262 	.id		= 1,
263 	.dev = {
264 		.platform_data	= &tmu1_platform_data,
265 	},
266 	.resource	= tmu1_resources,
267 	.num_resources	= ARRAY_SIZE(tmu1_resources),
268 };
269 
270 static struct sh_timer_config tmu2_platform_data = {
271 	.channels_mask = 7,
272 };
273 
274 static struct resource tmu2_resources[] = {
275 	DEFINE_RES_MEM(0xffd82000, 0x2c),
276 	DEFINE_RES_IRQ(evt2irq(0x4c0)),
277 	DEFINE_RES_IRQ(evt2irq(0x4e0)),
278 	DEFINE_RES_IRQ(evt2irq(0x500)),
279 };
280 
281 static struct platform_device tmu2_device = {
282 	.name		= "sh-tmu",
283 	.id		= 2,
284 	.dev = {
285 		.platform_data	= &tmu2_platform_data,
286 	},
287 	.resource	= tmu2_resources,
288 	.num_resources	= ARRAY_SIZE(tmu2_resources),
289 };
290 
291 static struct platform_device *sh7770_devices[] __initdata = {
292 	&scif0_device,
293 	&scif1_device,
294 	&scif2_device,
295 	&scif3_device,
296 	&scif4_device,
297 	&scif5_device,
298 	&scif6_device,
299 	&scif7_device,
300 	&scif8_device,
301 	&scif9_device,
302 	&tmu0_device,
303 	&tmu1_device,
304 	&tmu2_device,
305 };
306 
sh7770_devices_setup(void)307 static int __init sh7770_devices_setup(void)
308 {
309 	return platform_add_devices(sh7770_devices,
310 				    ARRAY_SIZE(sh7770_devices));
311 }
312 arch_initcall(sh7770_devices_setup);
313 
314 static struct platform_device *sh7770_early_devices[] __initdata = {
315 	&scif0_device,
316 	&scif1_device,
317 	&scif2_device,
318 	&scif3_device,
319 	&scif4_device,
320 	&scif5_device,
321 	&scif6_device,
322 	&scif7_device,
323 	&scif8_device,
324 	&scif9_device,
325 	&tmu0_device,
326 	&tmu1_device,
327 	&tmu2_device,
328 };
329 
plat_early_device_setup(void)330 void __init plat_early_device_setup(void)
331 {
332 	early_platform_add_devices(sh7770_early_devices,
333 				   ARRAY_SIZE(sh7770_early_devices));
334 }
335 
336 enum {
337 	UNUSED = 0,
338 
339 	/* interrupt sources */
340 	IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
341 	IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
342 	IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
343 	IRL_HHLL, IRL_HHLH, IRL_HHHL,
344 
345 	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
346 
347 	GPIO,
348 	TMU0, TMU1, TMU2, TMU2_TICPI,
349 	TMU3, TMU4, TMU5, TMU5_TICPI,
350 	TMU6, TMU7, TMU8,
351 	HAC, IPI, SPDIF, HUDI, I2C,
352 	DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
353 	I2S0, I2S1, I2S2, I2S3,
354 	SRC_RX, SRC_TX, SRC_SPDIF,
355 	DU, VIDEO_IN, REMOTE, YUV, USB, ATAPI, CAN, GPS, GFX2D,
356 	GFX3D_MBX, GFX3D_DMAC,
357 	EXBUS_ATA,
358 	SPI0, SPI1,
359 	SCIF089, SCIF1234, SCIF567,
360 	ADC,
361 	BBDMAC_0_3, BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14,
362 	BBDMAC_15_18, BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27,
363 	BBDMAC_28, BBDMAC_29, BBDMAC_30, BBDMAC_31,
364 
365 	/* interrupt groups */
366 	TMU, DMAC, I2S, SRC, GFX3D, SPI, SCIF, BBDMAC,
367 };
368 
369 static struct intc_vect vectors[] __initdata = {
370 	INTC_VECT(GPIO, 0x3e0),
371 	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
372 	INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
373 	INTC_VECT(TMU3, 0x480), INTC_VECT(TMU4, 0x4a0),
374 	INTC_VECT(TMU5, 0x4c0), INTC_VECT(TMU5_TICPI, 0x4e0),
375 	INTC_VECT(TMU6, 0x500), INTC_VECT(TMU7, 0x520),
376 	INTC_VECT(TMU8, 0x540),
377 	INTC_VECT(HAC, 0x580), INTC_VECT(IPI, 0x5c0),
378 	INTC_VECT(SPDIF, 0x5e0),
379 	INTC_VECT(HUDI, 0x600), INTC_VECT(I2C, 0x620),
380 	INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660),
381 	INTC_VECT(DMAC0_DMINT2, 0x680),
382 	INTC_VECT(I2S0, 0x6a0), INTC_VECT(I2S1, 0x6c0),
383 	INTC_VECT(I2S2, 0x6e0), INTC_VECT(I2S3, 0x700),
384 	INTC_VECT(SRC_RX, 0x720), INTC_VECT(SRC_TX, 0x740),
385 	INTC_VECT(SRC_SPDIF, 0x760),
386 	INTC_VECT(DU, 0x780), INTC_VECT(VIDEO_IN, 0x7a0),
387 	INTC_VECT(REMOTE, 0x7c0), INTC_VECT(YUV, 0x7e0),
388 	INTC_VECT(USB, 0x840), INTC_VECT(ATAPI, 0x860),
389 	INTC_VECT(CAN, 0x880), INTC_VECT(GPS, 0x8a0),
390 	INTC_VECT(GFX2D, 0x8c0),
391 	INTC_VECT(GFX3D_MBX, 0x900), INTC_VECT(GFX3D_DMAC, 0x920),
392 	INTC_VECT(EXBUS_ATA, 0x940),
393 	INTC_VECT(SPI0, 0x960), INTC_VECT(SPI1, 0x980),
394 	INTC_VECT(SCIF089, 0x9a0), INTC_VECT(SCIF1234, 0x9c0),
395 	INTC_VECT(SCIF1234, 0x9e0), INTC_VECT(SCIF1234, 0xa00),
396 	INTC_VECT(SCIF1234, 0xa20), INTC_VECT(SCIF567, 0xa40),
397 	INTC_VECT(SCIF567, 0xa60), INTC_VECT(SCIF567, 0xa80),
398 	INTC_VECT(SCIF089, 0xaa0), INTC_VECT(SCIF089, 0xac0),
399 	INTC_VECT(ADC, 0xb20),
400 	INTC_VECT(BBDMAC_0_3, 0xba0), INTC_VECT(BBDMAC_0_3, 0xbc0),
401 	INTC_VECT(BBDMAC_0_3, 0xbe0), INTC_VECT(BBDMAC_0_3, 0xc00),
402 	INTC_VECT(BBDMAC_4_7, 0xc20), INTC_VECT(BBDMAC_4_7, 0xc40),
403 	INTC_VECT(BBDMAC_4_7, 0xc60), INTC_VECT(BBDMAC_4_7, 0xc80),
404 	INTC_VECT(BBDMAC_8_10, 0xca0), INTC_VECT(BBDMAC_8_10, 0xcc0),
405 	INTC_VECT(BBDMAC_8_10, 0xce0), INTC_VECT(BBDMAC_11_14, 0xd00),
406 	INTC_VECT(BBDMAC_11_14, 0xd20), INTC_VECT(BBDMAC_11_14, 0xd40),
407 	INTC_VECT(BBDMAC_11_14, 0xd60), INTC_VECT(BBDMAC_15_18, 0xd80),
408 	INTC_VECT(BBDMAC_15_18, 0xda0), INTC_VECT(BBDMAC_15_18, 0xdc0),
409 	INTC_VECT(BBDMAC_15_18, 0xde0), INTC_VECT(BBDMAC_19_22, 0xe00),
410 	INTC_VECT(BBDMAC_19_22, 0xe20), INTC_VECT(BBDMAC_19_22, 0xe40),
411 	INTC_VECT(BBDMAC_19_22, 0xe60), INTC_VECT(BBDMAC_23_26, 0xe80),
412 	INTC_VECT(BBDMAC_23_26, 0xea0), INTC_VECT(BBDMAC_23_26, 0xec0),
413 	INTC_VECT(BBDMAC_23_26, 0xee0), INTC_VECT(BBDMAC_27, 0xf00),
414 	INTC_VECT(BBDMAC_28, 0xf20), INTC_VECT(BBDMAC_29, 0xf40),
415 	INTC_VECT(BBDMAC_30, 0xf60), INTC_VECT(BBDMAC_31, 0xf80),
416 };
417 
418 static struct intc_group groups[] __initdata = {
419 	INTC_GROUP(TMU, TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,
420 		   TMU5_TICPI, TMU6, TMU7, TMU8),
421 	INTC_GROUP(DMAC, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2),
422 	INTC_GROUP(I2S, I2S0, I2S1, I2S2, I2S3),
423 	INTC_GROUP(SRC, SRC_RX, SRC_TX, SRC_SPDIF),
424 	INTC_GROUP(GFX3D, GFX3D_MBX, GFX3D_DMAC),
425 	INTC_GROUP(SPI, SPI0, SPI1),
426 	INTC_GROUP(SCIF, SCIF089, SCIF1234, SCIF567),
427 	INTC_GROUP(BBDMAC,
428 		   BBDMAC_0_3, BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14,
429 		   BBDMAC_15_18, BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27,
430 		   BBDMAC_28, BBDMAC_29, BBDMAC_30, BBDMAC_31),
431 };
432 
433 static struct intc_mask_reg mask_registers[] __initdata = {
434 	{ 0xffe00040, 0xffe00044, 32, /* INT2MSKR / INT2MSKCR */
435 	  { 0, BBDMAC, ADC, SCIF, SPI, EXBUS_ATA, GFX3D, GFX2D,
436 	    GPS, CAN, ATAPI, USB, YUV, REMOTE, VIDEO_IN, DU, SRC, I2S,
437 	    DMAC, I2C, HUDI, SPDIF, IPI, HAC, TMU, GPIO } },
438 };
439 
440 static struct intc_prio_reg prio_registers[] __initdata = {
441 	{ 0xffe00000, 0, 32, 8, /* INT2PRI0 */ { GPIO, TMU0, 0, HAC } },
442 	{ 0xffe00004, 0, 32, 8, /* INT2PRI1 */ { IPI, SPDIF, HUDI, I2C } },
443 	{ 0xffe00008, 0, 32, 8, /* INT2PRI2 */ { DMAC, I2S, SRC, DU } },
444 	{ 0xffe0000c, 0, 32, 8, /* INT2PRI3 */ { VIDEO_IN, REMOTE, YUV, USB } },
445 	{ 0xffe00010, 0, 32, 8, /* INT2PRI4 */ { ATAPI, CAN, GPS, GFX2D } },
446 	{ 0xffe00014, 0, 32, 8, /* INT2PRI5 */ { 0, GFX3D, EXBUS_ATA, SPI } },
447 	{ 0xffe00018, 0, 32, 8, /* INT2PRI6 */ { SCIF1234, SCIF567, SCIF089 } },
448 	{ 0xffe0001c, 0, 32, 8, /* INT2PRI7 */ { ADC, 0, 0, BBDMAC_0_3 } },
449 	{ 0xffe00020, 0, 32, 8, /* INT2PRI8 */
450 	  { BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14, BBDMAC_15_18 } },
451 	{ 0xffe00024, 0, 32, 8, /* INT2PRI9 */
452 	  { BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27, BBDMAC_28 } },
453 	{ 0xffe00028, 0, 32, 8, /* INT2PRI10 */
454 	  { BBDMAC_29, BBDMAC_30, BBDMAC_31 } },
455 	{ 0xffe0002c, 0, 32, 8, /* INT2PRI11 */
456 	  { TMU1, TMU2, TMU2_TICPI, TMU3 } },
457 	{ 0xffe00030, 0, 32, 8, /* INT2PRI12 */
458 	  { TMU4, TMU5, TMU5_TICPI, TMU6 } },
459 	{ 0xffe00034, 0, 32, 8, /* INT2PRI13 */
460 	  { TMU7, TMU8 } },
461 };
462 
463 static DECLARE_INTC_DESC(intc_desc, "sh7770", vectors, groups,
464 			 mask_registers, prio_registers, NULL);
465 
466 /* Support for external interrupt pins in IRQ mode */
467 static struct intc_vect irq_vectors[] __initdata = {
468 	INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
469 	INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
470 	INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
471 };
472 
473 static struct intc_mask_reg irq_mask_registers[] __initdata = {
474 	{ 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
475 	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, } },
476 };
477 
478 static struct intc_prio_reg irq_prio_registers[] __initdata = {
479 	{ 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
480 					       IRQ4, IRQ5, } },
481 };
482 
483 static struct intc_sense_reg irq_sense_registers[] __initdata = {
484 	{ 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
485 					    IRQ4, IRQ5, } },
486 };
487 
488 static DECLARE_INTC_DESC(intc_irq_desc, "sh7770-irq", irq_vectors,
489 			 NULL, irq_mask_registers, irq_prio_registers,
490 			 irq_sense_registers);
491 
492 /* External interrupt pins in IRL mode */
493 static struct intc_vect irl_vectors[] __initdata = {
494 	INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
495 	INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
496 	INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
497 	INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
498 	INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
499 	INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
500 	INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
501 	INTC_VECT(IRL_HHHL, 0x3c0),
502 };
503 
504 static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
505 	{ 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
506 	  { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
507 	    IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
508 	    IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
509 	    IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
510 };
511 
512 static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
513 	{ 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
514 	  { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
515 	    IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
516 	    IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
517 	    IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
518 	    IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
519 };
520 
521 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
522 			 NULL, irl7654_mask_registers, NULL, NULL);
523 
524 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
525 			 NULL, irl3210_mask_registers, NULL, NULL);
526 
527 #define INTC_ICR0	0xffd00000
528 #define INTC_INTMSK0	0xffd00044
529 #define INTC_INTMSK1	0xffd00048
530 #define INTC_INTMSK2	0xffd40080
531 #define INTC_INTMSKCLR1	0xffd00068
532 #define INTC_INTMSKCLR2	0xffd40084
533 
plat_irq_setup(void)534 void __init plat_irq_setup(void)
535 {
536 	/* disable IRQ7-0 */
537 	__raw_writel(0xff000000, INTC_INTMSK0);
538 
539 	/* disable IRL3-0 + IRL7-4 */
540 	__raw_writel(0xc0000000, INTC_INTMSK1);
541 	__raw_writel(0xfffefffe, INTC_INTMSK2);
542 
543 	/* select IRL mode for IRL3-0 + IRL7-4 */
544 	__raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
545 
546 	/* disable holding function, ie enable "SH-4 Mode" */
547 	__raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
548 
549 	register_intc_controller(&intc_desc);
550 }
551 
plat_irq_setup_pins(int mode)552 void __init plat_irq_setup_pins(int mode)
553 {
554 	switch (mode) {
555 	case IRQ_MODE_IRQ:
556 		/* select IRQ mode for IRL3-0 + IRL7-4 */
557 		__raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
558 		register_intc_controller(&intc_irq_desc);
559 		break;
560 	case IRQ_MODE_IRL7654:
561 		/* enable IRL7-4 but don't provide any masking */
562 		__raw_writel(0x40000000, INTC_INTMSKCLR1);
563 		__raw_writel(0x0000fffe, INTC_INTMSKCLR2);
564 		break;
565 	case IRQ_MODE_IRL3210:
566 		/* enable IRL0-3 but don't provide any masking */
567 		__raw_writel(0x80000000, INTC_INTMSKCLR1);
568 		__raw_writel(0xfffe0000, INTC_INTMSKCLR2);
569 		break;
570 	case IRQ_MODE_IRL7654_MASK:
571 		/* enable IRL7-4 and mask using cpu intc controller */
572 		__raw_writel(0x40000000, INTC_INTMSKCLR1);
573 		register_intc_controller(&intc_irl7654_desc);
574 		break;
575 	case IRQ_MODE_IRL3210_MASK:
576 		/* enable IRL0-3 and mask using cpu intc controller */
577 		__raw_writel(0x80000000, INTC_INTMSKCLR1);
578 		register_intc_controller(&intc_irl3210_desc);
579 		break;
580 	default:
581 		BUG();
582 	}
583 }
584