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Searched refs:TX49XX_ICACHE_INDEX_INV_WAR (Results 1 – 15 of 15) sorted by relevance

/arch/mips/include/asm/
Dwar.h207 #ifndef TX49XX_ICACHE_INDEX_INV_WAR
208 #error Check setting of TX49XX_ICACHE_INDEX_INV_WAR for your platform
/arch/mips/include/asm/mach-malta/
Dwar.h19 #define TX49XX_ICACHE_INDEX_INV_WAR 0 macro
/arch/mips/include/asm/mach-ip22/
Dwar.h23 #define TX49XX_ICACHE_INDEX_INV_WAR 0 macro
/arch/mips/include/asm/mach-ip32/
Dwar.h19 #define TX49XX_ICACHE_INDEX_INV_WAR 0 macro
/arch/mips/include/asm/mach-ip27/
Dwar.h19 #define TX49XX_ICACHE_INDEX_INV_WAR 0 macro
/arch/mips/include/asm/mach-ip28/
Dwar.h19 #define TX49XX_ICACHE_INDEX_INV_WAR 0 macro
/arch/mips/include/asm/mach-generic/
Dwar.h19 #define TX49XX_ICACHE_INDEX_INV_WAR 0 macro
/arch/mips/include/asm/mach-rc32434/
Dwar.h19 #define TX49XX_ICACHE_INDEX_INV_WAR 0 macro
/arch/mips/include/asm/mach-sead3/
Dwar.h19 #define TX49XX_ICACHE_INDEX_INV_WAR 0 macro
/arch/mips/include/asm/mach-rm/
Dwar.h23 #define TX49XX_ICACHE_INDEX_INV_WAR 0 macro
/arch/mips/include/asm/mach-tx49xx/
Dwar.h19 #define TX49XX_ICACHE_INDEX_INV_WAR 1 macro
/arch/mips/include/asm/mach-cavium-octeon/
Dwar.h20 #define TX49XX_ICACHE_INDEX_INV_WAR 0 macro
/arch/mips/include/asm/mach-pmcs-msp71xx/
Dwar.h19 #define TX49XX_ICACHE_INDEX_INV_WAR 0 macro
/arch/mips/include/asm/mach-sibyte/
Dwar.h34 #define TX49XX_ICACHE_INDEX_INV_WAR 0 macro
/arch/mips/mm/
Dc-r4k.c336 else if (TX49XX_ICACHE_INDEX_INV_WAR) in r4k_blast_icache_page_indexed_setup()
363 else if (TX49XX_ICACHE_INDEX_INV_WAR) in r4k_blast_icache_setup()