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Searched refs:bfin_write32 (Results 1 – 25 of 40) sorted by relevance

12

/arch/blackfin/include/asm/
Dcdef_LPBlackfin.h18 #define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val)
20 #define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val)
22 #define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS,val)
24 #define bfin_write_DCPLB_FAULT_ADDR(val) bfin_write32(DCPLB_FAULT_ADDR,val)
29 #define bfin_write_DCPLB_ADDR0(val) bfin_write32(DCPLB_ADDR0,val)
31 #define bfin_write_DCPLB_ADDR1(val) bfin_write32(DCPLB_ADDR1,val)
33 #define bfin_write_DCPLB_ADDR2(val) bfin_write32(DCPLB_ADDR2,val)
35 #define bfin_write_DCPLB_ADDR3(val) bfin_write32(DCPLB_ADDR3,val)
37 #define bfin_write_DCPLB_ADDR4(val) bfin_write32(DCPLB_ADDR4,val)
39 #define bfin_write_DCPLB_ADDR5(val) bfin_write32(DCPLB_ADDR5,val)
[all …]
Dcplb.h116 bfin_write32(mmr, ctrl); in _disable_cplb()
123 bfin_write32(mmr, ctrl); in disable_cplb()
136 bfin_write32(mmr, ctrl); in _enable_cplb()
143 bfin_write32(mmr, ctrl); in enable_cplb()
/arch/blackfin/mach-bf518/include/mach/
DcdefBF516.h16 #define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
18 #define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
20 #define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
22 #define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
24 #define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
26 #define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
28 #define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
30 #define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
32 #define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
34 #define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
[all …]
DcdefBF518.h22 #define bfin_write_EMAC_PTP_FOFF(val) bfin_write32(EMAC_PTP_FOFF, val)
24 #define bfin_write_EMAC_PTP_FV1(val) bfin_write32(EMAC_PTP_FV1, val)
26 #define bfin_write_EMAC_PTP_FV2(val) bfin_write32(EMAC_PTP_FV2, val)
28 #define bfin_write_EMAC_PTP_FV3(val) bfin_write32(EMAC_PTP_FV3, val)
30 #define bfin_write_EMAC_PTP_ADDEND(val) bfin_write32(EMAC_PTP_ADDEND, val)
32 #define bfin_write_EMAC_PTP_ACCR(val) bfin_write32(EMAC_PTP_ACCR, val)
34 #define bfin_write_EMAC_PTP_OFFSET(val) bfin_write32(EMAC_PTP_OFFSET, val)
36 #define bfin_write_EMAC_PTP_TIMELO(val) bfin_write32(EMAC_PTP_TIMELO, val)
38 #define bfin_write_EMAC_PTP_TIMEHI(val) bfin_write32(EMAC_PTP_TIMEHI, val)
44 #define bfin_write_EMAC_PTP_ALARMLO(val) bfin_write32(EMAC_PTP_ALARMLO, val)
[all …]
DcdefBF512.h20 #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
30 #define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
32 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
34 #define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
37 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
39 #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
41 #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
43 #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
46 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
48 #define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
[all …]
DcdefBF514.h20 #define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
26 #define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
28 #define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
30 #define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
32 #define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
34 #define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
42 #define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
46 #define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
48 #define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
54 #define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
/arch/blackfin/mach-bf527/include/mach/
DcdefBF527.h16 #define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
18 #define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
20 #define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
22 #define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
24 #define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
26 #define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
28 #define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
30 #define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
32 #define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
34 #define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
[all …]
DcdefBF522.h20 #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
30 #define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
32 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
34 #define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
37 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
39 #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
41 #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
43 #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
46 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
48 #define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
[all …]
/arch/blackfin/mach-bf537/include/mach/
DcdefBF537.h16 #define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE,val)
18 #define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO,val)
20 #define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI,val)
22 #define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO,val)
24 #define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI,val)
26 #define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD,val)
28 #define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT,val)
30 #define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC,val)
32 #define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1,val)
34 #define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2,val)
[all …]
DcdefBF534.h27 #define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT,val)
29 #define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val)
31 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
33 #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
35 #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
37 #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
39 #define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val)
41 #define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val)
47 #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val)
49 #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val)
[all …]
/arch/blackfin/mach-bf609/include/mach/
DcdefBF60x_base.h17 #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
23 #define bfin_write_SEC0_CCTL(val) bfin_write32(SEC0_CCTL, val)
25 #define bfin_write_SEC0_CSID(val) bfin_write32(SEC0_CSID, val)
27 #define bfin_write_SEC_GCTL(val) bfin_write32(SEC_GCTL, val)
30 #define bfin_write_SEC_FCTL(val) bfin_write32(SEC_FCTL, val)
33 #define bfin_write_SEC_SCTL(sid, val) bfin_write32((SEC_SCTL0 + (sid) * 8), val)
36 #define bfin_write_SEC_SSTAT(sid, val) bfin_write32((SEC_SSTAT0 + (sid) * 8), val)
40 #define bfin_write_RCU0_CTL(val) bfin_write32(RCU0_CTL, val)
46 #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
48 #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
[all …]
/arch/blackfin/mach-bf548/include/mach/
DcdefBF549.h21 #define bfin_write_MXVR_STATE_0(val) bfin_write32(MXVR_STATE_0, val)
23 #define bfin_write_MXVR_STATE_1(val) bfin_write32(MXVR_STATE_1, val)
25 #define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val)
27 #define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val)
29 #define bfin_write_MXVR_INT_EN_0(val) bfin_write32(MXVR_INT_EN_0, val)
31 #define bfin_write_MXVR_INT_EN_1(val) bfin_write32(MXVR_INT_EN_1, val)
41 #define bfin_write_MXVR_LADDR(val) bfin_write32(MXVR_LADDR, val)
45 #define bfin_write_MXVR_AADDR(val) bfin_write32(MXVR_AADDR, val)
50 #define bfin_write_MXVR_ALLOC_0(val) bfin_write32(MXVR_ALLOC_0, val)
52 #define bfin_write_MXVR_ALLOC_1(val) bfin_write32(MXVR_ALLOC_1, val)
[all …]
DcdefBF54x_base.h28 #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
40 #define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
42 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
44 #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
46 #define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val)
48 #define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 2)), val)
51 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
53 #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
55 #define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val)
57 #define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 2)), val)
[all …]
DcdefBF547.h20 #define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
22 #define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
24 #define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
28 #define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
30 #define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
32 #define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
36 #define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
38 #define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
40 #define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
49 #define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
[all …]
/arch/blackfin/mach-bf538/include/mach/
DcdefBF539.h16 #define bfin_write_MXVR_PLL_CTL_0(val) bfin_write32(MXVR_PLL_CTL_0, val)
18 #define bfin_write_MXVR_STATE_0(val) bfin_write32(MXVR_STATE_0, val)
20 #define bfin_write_MXVR_STATE_1(val) bfin_write32(MXVR_STATE_1, val)
22 #define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val)
24 #define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val)
26 #define bfin_write_MXVR_INT_EN_0(val) bfin_write32(MXVR_INT_EN_0, val)
28 #define bfin_write_MXVR_INT_EN_1(val) bfin_write32(MXVR_INT_EN_1, val)
38 #define bfin_write_MXVR_LADDR(val) bfin_write32(MXVR_LADDR, val)
42 #define bfin_write_MXVR_AADDR(val) bfin_write32(MXVR_AADDR, val)
44 #define bfin_write_MXVR_ALLOC_0(val) bfin_write32(MXVR_ALLOC_0, val)
[all …]
DcdefBF538.h10 #define bfin_writePTR(addr, val) bfin_write32(addr, val)
21 #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
29 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
31 #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
33 #define bfin_write_SIC_IMASK(x, val) bfin_write32(SIC_IMASK0 + x * (SIC_IMASK1 - SIC_IMASK0), val)
35 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
37 #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
39 #define bfin_write_SIC_ISR(x, val) bfin_write32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0), val)
41 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
43 #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
[all …]
/arch/blackfin/mach-bf561/include/mach/
DcdefBF561.h33 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0,val)
35 #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1,val)
37 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
39 #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
41 #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
43 #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
45 #define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4,val)
47 #define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5,val)
49 #define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6,val)
51 #define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7,val)
[all …]
Dblackfin.h33 #define bfin_write_SIC_IMASK(x, val) bfin_write32(__SIC_MUX(SIC_IMASK0, x), val)
35 #define bfin_write_SICB_IMASK(x, val) bfin_write32(__SIC_MUX(SICB_IMASK0, x), val)
37 #define bfin_write_SIC_ISR(x, val) bfin_write32(__SIC_MUX(SIC_ISR0, x), val)
39 #define bfin_write_SICB_ISR(x, val) bfin_write32(__SIC_MUX(SICB_ISR0, x), val)
Dpll.h26 bfin_write32(SIC_IWR0 + SICA_SICB_OFF, iwr0); in bfin_iwr_restore()
27 bfin_write32(SIC_IWR1 + SICA_SICB_OFF, iwr1); in bfin_iwr_restore()
/arch/blackfin/mach-bf533/include/mach/
DcdefBF532.h27 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
29 #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
31 #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
33 #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
35 #define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val)
37 #define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val)
39 #define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val)
45 #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val)
47 #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val)
51 #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val)
[all …]
/arch/blackfin/mach-bf609/
Dpm.c156 bfin_write32(DPM0_CCBF_EN, 3); in bf609_resume_ccbuf()
157 bfin_write32(DPM0_CTL, 2); in bf609_resume_ccbuf()
174 bfin_write32(DPM0_RESTORE5, bfin_read32(DPM0_RESTORE5) | 4); in bfin_hibernate_syscontrol()
182 bfin_write32(DPM0_WAKE_EN, mask); in bfin_deepsleep()
183 bfin_write32(DPM0_WAKE_POL, pol_mask); in bfin_deepsleep()
190 bfin_write32(DPM0_WAKE_EN, mask); in bfin_hibernate()
191 bfin_write32(DPM0_WAKE_POL, pol_mask); in bfin_hibernate()
192 bfin_write32(DPM0_PGCNTR, 0x0000FFFF); in bfin_hibernate()
193 bfin_write32(DPM0_HIB_DIS, 0xFFFF); in bfin_hibernate()
319 bfin_write32(DPM0_WAKE_STAT, bfin_read32(DPM0_WAKE_STAT)); in dpm0_isr()
[all …]
/arch/blackfin/mach-common/
Dcache-c.c50 bfin_write32(mem_control, ctrl); in bfin_cache_init()
56 bfin_write32(cplb_addr + i * 4, cplb_tbl[i].addr); in bfin_cache_init()
57 bfin_write32(cplb_data + i * 4, cplb_tbl[i].data); in bfin_cache_init()
Dscb-init.c20 bfin_write32(scb_mi_arbw, (i << SCB_SLOT_OFFSET) | scb_mi_prio[i]); in scb_mi_write()
30 bfin_write32(scb_mi_arbw, (0xFF << SCB_SLOT_OFFSET) | i); in scb_mi_read()
/arch/blackfin/kernel/cplb-mpu/
Dcplbmgr.c167 bfin_write32(DCPLB_DATA0 + idx * 4, d_data); in dcplb_miss()
168 bfin_write32(DCPLB_ADDR0 + idx * 4, addr); in dcplb_miss()
273 bfin_write32(ICPLB_DATA0 + idx * 4, i_data); in icplb_miss()
274 bfin_write32(ICPLB_ADDR0 + idx * 4, addr); in icplb_miss()
293 bfin_write32(DCPLB_DATA0 + idx * 4, data); in dcplb_protection_fault()
327 bfin_write32(ICPLB_DATA0 + i * 4, 0); in flush_switched_cplbs()
334 bfin_write32(DCPLB_DATA0 + i * 4, 0); in flush_switched_cplbs()
373 bfin_write32(DCPLB_DATA0 + i * 4, d_data); in set_mask_dcplbs()
374 bfin_write32(DCPLB_ADDR0 + i * 4, addr); in set_mask_dcplbs()
/arch/blackfin/kernel/cplb-nompu/
Dcplbmgr.c43 bfin_write32(DCPLB_DATA0 + idx * 4, data); in write_dcplb_data()
44 bfin_write32(DCPLB_ADDR0 + idx * 4, addr); in write_dcplb_data()
57 bfin_write32(ICPLB_DATA0 + idx * 4, data); in write_icplb_data()
58 bfin_write32(ICPLB_ADDR0 + idx * 4, addr); in write_icplb_data()

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