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Searched refs:c1 (Results 1 – 25 of 82) sorted by relevance

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/arch/arm/include/asm/hardware/
Dcp14.h54 #define RCP14_DBGDSCRint() MRC14(0, c0, c1, 0)
66 #define RCP14_DBGBVR1() MRC14(0, c0, c1, 4)
82 #define RCP14_DBGBCR1() MRC14(0, c0, c1, 5)
98 #define RCP14_DBGWVR1() MRC14(0, c0, c1, 6)
114 #define RCP14_DBGWCR1() MRC14(0, c0, c1, 7)
129 #define RCP14_DBGDRAR() MRC14(0, c1, c0, 0)
130 #define RCP14_DBGBXVR0() MRC14(0, c1, c0, 1)
131 #define RCP14_DBGBXVR1() MRC14(0, c1, c1, 1)
132 #define RCP14_DBGBXVR2() MRC14(0, c1, c2, 1)
133 #define RCP14_DBGBXVR3() MRC14(0, c1, c3, 1)
[all …]
/arch/arm/mach-iop32x/include/mach/
Dentry-macro.S13 mrc p15, 0, \tmp, c15, c1, 0
15 mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
16 mrc p15, 0, \tmp, c15, c1, 0
29 mrc p15, 0, \tmp1, c15, c1, 0
32 mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
/arch/arm/mach-iop33x/include/mach/
Dentry-macro.S13 mrc p15, 0, \tmp, c15, c1, 0
15 mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
16 mrc p15, 0, \tmp, c15, c1, 0
30 mrc p15, 0, \tmp1, c15, c1, 0
33 mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
/arch/arm/mach-iop13xx/include/mach/
Dentry-macro.S20 mrc p15, 0, \tmp, c15, c1, 0
22 mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
38 mrc p15, 0, \tmp1, c15, c1, 0
41 mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
/arch/x86/boot/
Dstring.c54 unsigned char c1, c2; in strncmp() local
57 c1 = *cs++; in strncmp()
59 if (c1 != c2) in strncmp()
60 return c1 < c2 ? -1 : 1; in strncmp()
61 if (!c1) in strncmp()
/arch/mips/include/asm/sibyte/
Dboard.h42 #define setleds(t0, t1, c0, c1, c2, c3) \
46 li t1, c1; \
53 #define setleds(t0, t1, c0, c1, c2, c3)
/arch/arm/mm/
Dproc-v6.S42 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
45 mcr p15, 0, r0, c1, c0, 0 @ disable caches
60 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
62 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
147 mrc p15, 0, r7, c1, c0, 1 @ auxiliary control register
148 mrc p15, 0, r8, c1, c0, 2 @ co-processor access control
149 mrc p15, 0, r9, c1, c0, 0 @ control register
171 mcr p15, 0, r7, c1, c0, 1 @ auxiliary control register
172 mcr p15, 0, r8, c1, c0, 2 @ co-processor access control
200 ALT_SMP(mrc p15, 0, r0, c1, c0, 1) @ Enable SMP/nAMP mode
[all …]
Dproc-v7.S34 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
37 mcr p15, 0, r0, c1, c0, 0 @ disable caches
56 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
59 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
143 mrc p15, 0, r8, c1, c0, 0 @ Control register
144 mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
145 mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
176 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
178 mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
179 mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
[all …]
Dproc-sa110.S40 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
49 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
52 mcr p15, 0, r0, c1, c0, 0 @ disable caches
73 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
76 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
105 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
173 mrc p15, 0, r0, c1, c0 @ get control register v4
Dproc-arm720.S57 mrc p15, 0, r0, c1, c0, 0
60 mcr p15, 0, r0, c1, c0, 0 @ disable caches
111 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
114 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
126 mrc p15, 0, r0, c1, c0 @ get control register
156 mrc p15, 0, r0, c1, c0 @ get control register
Dproc-fa526.S41 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
68 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
72 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
150 mcr p15, 0, r0, c1, c1, 0 @ turn-on ECR
160 mrc p15, 0, r0, c1, c0 @ get control register v4
Dproc-arm740.S41 mrc p15, 0, r0, c1, c0, 0
44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
56 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
58 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
85 mcr p15, 0, r0, c6, c1 @ set area 1, RAM
113 mrc p15, 0, r0, c1, c0 @ get control register
Dproc-sa1100.S44 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
57 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
60 mcr p15, 0, r0, c1, c0, 0 @ disable caches
81 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
84 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
115 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
180 mrc p15, 0, r6, c1, c0, 0 @ control reg
211 mrc p15, 0, r0, c1, c0 @ get control register v4
Dproc-xsc3.S92 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
95 mcr p15, 0, r0, c1, c0, 0 @ disable caches
112 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
118 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
420 mrc p15, 0, r5, c15, c1, 0 @ CP access reg
423 mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
424 mrc p15, 0, r9, c1, c0, 0 @ control reg
438 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
443 mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
[all …]
Dproc-mohawk.S54 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
57 mcr p15, 0, r0, c1, c0, 0 @ disable caches
78 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
81 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
357 mrc p15, 0, r5, c15, c1, 0 @ CP access reg
360 mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
361 mrc p15, 0, r9, c1, c0, 0 @ control reg
375 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
380 mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
/arch/arm/mach-omap2/
Dsleep44xx.S88 mrc p15, 0, r0, c1, c0, 0
90 mcr p15, 0, r0, c1, c0, 0
131 mrc p15, 0, r0, c1, c1, 2 @ Read NSACR data
133 mrcne p15, 0, r0, c1, c0, 1
135 mcrne p15, 0, r0, c1, c0, 1
194 mrc p15, 0, r0, c1, c0, 0
197 mcreq p15, 0, r0, c1, c0, 0
206 mrc p15, 0, r0, c1, c0, 1
209 mcreq p15, 0, r0, c1, c0, 1
275 mrc p15, 0, r0, c1, c0, 1
[all …]
/arch/arm/boot/compressed/
Dbig-endian.S10 mrc p15, 0, r0, c1, c0, 0 @ read control reg
12 mcr p15, 0, r0, c1, c0, 0 @ write control reg
Dstring.c92 unsigned char c1, c2; in strcmp() local
96 c1 = *cs++; in strcmp()
98 res = c1 - c2; in strcmp()
101 } while (c1); in strcmp()
/arch/arm/kernel/
Diwmmxt.S76 XSC(mrc p15, 0, r2, c15, c1, 0)
77 PJ4(mrc p15, 0, r2, c1, c0, 2)
84 XSC(mcr p15, 0, r2, c15, c1, 0)
86 PJ4(mcr p15, 0, r2, c1, c0, 2)
213 XSC(mrc p15, 0, r4, c15, c1, 0)
215 XSC(mcr p15, 0, r4, c15, c1, 0)
216 PJ4(mrc p15, 0, r4, c1, c0, 2)
218 PJ4(mcr p15, 0, r4, c1, c0, 2)
228 XSC(mcr p15, 0, r4, c15, c1, 0)
230 PJ4(mcr p15, 0, r4, c1, c0, 2)
[all …]
Dhead-nommu.S160 mcr p15, 0, r0, c1, c0, 0 @ write control reg
177 mcr p15, 0, \bar, c6, c1, (0 + \side) @ I/DRBAR
178 mcr p15, 0, \acr, c6, c1, (4 + \side) @ I/DRACR
179 mcr p15, 0, \sr, c6, c1, (2 + \side) @ I/DRSR
195 mrc p15, 0, r0, c0, c1, 4 @ Read ID_MMFR0
247 mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR
250 mcr p15, 0, r0, c1, c0, 0 @ Enable MPU
/arch/arm/mach-spear/
Dheadsmp.S35 mrc p15, 0, r0, c1, c0, 1
37 mcr p15, 0, r0, c1, c0, 1
/arch/arm/mach-tegra/
Dsleep.S53 mrc p15, 0, r2, c1, c0, 0
55 mcr p15, 0, r2, c1, c0, 0
128 mrc p15, 0, r3, c1, c0, 0
132 mcr p15, 0, r3, c1, c0, 0
/arch/arm/kvm/
Dinterrupts_head.S251 mrc p15, 0, r2, c1, c0, 0 @ SCTLR
252 mrc p15, 0, r3, c1, c0, 2 @ CPACR
283 mrc p15, 0, r8, c5, c1, 0 @ ADFSR
284 mrc p15, 0, r9, c5, c1, 1 @ AIFSR
305 mrc p15, 0, r2, c14, c1, 0 @ CNTKCTL
339 mcr p15, 0, r2, c14, c1, 0 @ CNTKCTL
366 mcr p15, 0, r8, c5, c1, 0 @ ADFSR
367 mcr p15, 0, r9, c5, c1, 1 @ AIFSR
388 mcr p15, 0, r2, c1, c0, 0 @ SCTLR
389 mcr p15, 0, r3, c1, c0, 2 @ CPACR
[all …]
Dinit.S87 mrc p15, 4, r1, c2, c1, 2 @ VTCR
93 mcr p15, 4, r1, c2, c1, 2 @ VTCR
114 mrc p15, 4, r0, c1, c0, 0 @ HSCR
117 mrc p15, 0, r1, c1, c0, 0 @ SCTLR
125 mcr p15, 4, r0, c1, c0, 0 @ HSCR
/arch/arm/include/debug/
Dicedcc.S25 mrc p14, 0, \rx, c0, c1, 0
35 mrc p14, 0, \rx, c0, c1, 0
68 mcr p14, 0, \rd, c1, c0, 0

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