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/arch/sparc/include/asm/
Dhead_32.h12 rd %psr, %l0; b label; rd %wim, %l3; nop;
15 #define SRMMU_TFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 1, %l7;
16 #define SRMMU_DFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 0, %l7;
20 rd %psr, %l0; mov num, %l7; b bad_trap_handler; rd %wim, %l3;
37 rd %psr, %l0;
41 rd %psr,%l0; \
48 rd %psr,%l0; \
58 b getcc_trap_handler; rd %psr, %l0; nop; nop;
62 b setcc_trap_handler; rd %psr, %l0; nop; nop;
72 mov int_level, %l7; rd %psr, %l0; b real_irq_entry; rd %wim, %l3;
[all …]
Dttable.h15 rdpr %cleanwin, %l0; add %l0, 1, %l0; \
16 wrpr %l0, 0x0, %cleanwin; \
19 clr %l0; clr %l1; clr %l2; clr %l3; \
235 stx %l0, [%sp + STACK_BIAS + 0x00]; \
256 stx %l0, [%sp + STACK_BIAS + 0x00]; \
282 stxa %l0, [%g1 + %g0] ASI; \
314 stxa %l0, [%sp + STACK_BIAS + 0x00] %asi; \
348 stx %l0, [%g3 + TI_REG_WINDOW + 0x00]; \
378 stwa %l0, [%sp + %g0] ASI; \
413 stwa %l0, [%sp + 0x00] %asi; \
[all …]
Dwinmacro.h16 std %l0, [%reg + RW_L0]; \
27 ldd [%reg + RW_L0], %l0; \
/arch/sparc/power/
Dhibernate_asm.S50 sethi %hi(restore_pblist), %l0
51 ldx [%l0 + %lo(restore_pblist)], %l0
70 cmp %l0, %g0
72 sub %l0, %g7, %l0
74 ldxa [%l0 ] %asi, %l1 /* address */
75 ldxa [%l0 + 8] %asi, %l2 /* orig_address */
91 ldxa [%l0 + 16] %asi, %l0
/arch/sparc/kernel/
Dentry.S157 wr %l0, 0x0, %psr
178 or %l0, PSR_PIL, %l4
198 wr %l0, PSR_ET, %psr
227 or %l0, PSR_PIL, %g2
236 or %l0, PSR_PIL, %g2 ! restore PIL after handler_irq
246 or %l0, PSR_PIL, %g2
253 wr %l0, PSR_ET, %psr
284 or %l0, PSR_PIL, %l4
329 or %l0, PSR_PIL, %l4
343 or %l0, PSR_PIL, %g2
[all …]
Dhvtramp.S46 mov %o0, %l0
48 lduw [%l0 + HVTRAMP_DESCR_CPU], %g1
52 ldx [%l0 + HVTRAMP_DESCR_FAULT_INFO_VA], %g2
56 lduw [%l0 + HVTRAMP_DESCR_NUM_MAPPINGS], %l2
57 add %l0, HVTRAMP_DESCR_MAPS, %l3
74 ldx [%l0 + HVTRAMP_DESCR_FAULT_INFO_PA], %o0
83 ldx [%l0 + HVTRAMP_DESCR_THREAD_REG], %l6
Dhead_64.S162 rd %pc, %l0
165 sub %l0, %l1, %l1
180 sub %l0, %l1, %l1
186 sub %l0, %l1, %l1
187 sub %l0, %l2, %l2
188 sub %l0, %l5, %l5
210 sub %l0, %l1, %l1
211 sub %l0, %l2, %l2
212 sub %l0, %l3, %l3
213 stw %l0, [%l3]
[all …]
Drtrap_64.S48 mov %l0, %o2
132 ldx [%g6 + TI_FLAGS], %l0
135 andcc %l0, %o0, %g0
139 andcc %l0, _TIF_NEED_RESCHED, %g0
141 andcc %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
205 661: ldxa [%l7 + %l7] ASI_DMMU, %l0
208 ldxa [%l7 + %l7] ASI_MMU, %l0
213 or %l0, %l1, %l0
215 661: stxa %l0, [%l7] ASI_DMMU
218 stxa %l0, [%l7] ASI_MMU
Dhead_32.S121 mov %o0, %l0 ! stash away romvec
360 mov %l0, %o0 ! put back romvec
373 ld [%l1], %l0
374 ld [%l0], %l0
375 call %l0
383 ld [%l1], %l0 ! 'compatible' tells
384 ld [%l0 + 0xc], %l0 ! that we want 'sun4x' where
385 call %l0 ! x is one of 'm', 'd' or 'e'.
728 mov %o4, %l0
745 call %l0
[all …]
Dsyscalls.S119 ldx [%g6 + TI_FLAGS], %l0
229 ldx [%g6 + TI_FLAGS], %l0 ! Load
233 …andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT|_TIF_SYSCALL_TRACEPOINT|_TIF_NOHZ),…
253 ldx [%g6 + TI_FLAGS], %l0 ! Load
257 …andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT|_TIF_SYSCALL_TRACEPOINT|_TIF_NOHZ),…
272 …andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT|_TIF_SYSCALL_TRACEPOINT|_TIF_NOHZ),…
Detrap_64.S129 rdpr %cwp, %l0
134 or %l7, %l0, %l7
135 sethi %hi(TSTATE_TSO | TSTATE_PEF), %l0
136 or %l7, %l0, %l7
Dwinfixup.S55 stx %l0, [%g3 + TI_REG_WINDOW + 0x00]
72 1: stw %l0, [%g3 + TI_REG_WINDOW + 0x00]
Dtrampoline_64.S97 mov %o0, %l0
310 ldx [%l0], %o0
393 ldx [%l0], %g6
/arch/sparc/lib/
Dxor.S364 ldda [%i1 + 0x30] %asi, %l0 /* %l0/%l1 = src + 0x30 */
383 xor %l2, %l0, %l2
411 ldda [%l7 + 0x10] %asi, %l0 /* %l0/%l1 = src2 + 0x10 */
423 xor %l0, %i4, %l0
425 xor %o2, %l0, %o2
430 ldda [%l7 + 0x30] %asi, %l0 /* %l0/%l1 = src2 + 0x30 */
441 xor %l0, %i4, %l0
443 xor %o2, %l0, %o2
474 ldda [%i0 + 0x00] %asi, %l0 /* %l0/%l1 = dest + 0x00 */
481 xor %l0, %g2, %l0
[all …]
Dmuldi3.S68 mov %o0, %l0
72 add %l0, %o0, %l0
74 add %l2, %l0, %i0
Dmcount.S57 mov %g2, %l0
84 mov %g2, %l0
108 mov %l0, %o0
Dmemcpy.S404 sub %g2, %g4, %l0
443 srl %g1, %l0, %g5
449 srl %i3, %l0, %g5
455 srl %i4, %l0, %g5
461 srl %i5, %l0, %g5
471 srl %g1, %l0, %g5
472 srl %l0, 3, %g3
Dudivdi3.S255 mov %o2,%l0
256 mov %l0,%i0
/arch/blackfin/include/asm/
Dcontext.S37 [--sp] = l0;
84 l0 = r0; define
109 [--sp] = l0;
144 l0 = r0; define
168 [--sp] = l0;
219 l0 = r0; define
259 l0 = [sp++]; define
329 l0 = [sp++]; define
/arch/sparc/prom/
Dcif.S18 mov %g4, %l0
23 mov %l0, %g4
/arch/blackfin/include/uapi/asm/
Dptrace.h60 long l0; member
/arch/blackfin/mach-common/
Dinterrupt.S51 [--sp] = l0;
101 l0 = r1; define
/arch/blackfin/kernel/
Dsignal.c67 RESTORE(l0); RESTORE(l1); RESTORE(l2); RESTORE(l3); in rt_restore_sigcontext()
128 SETUP(l0); SETUP(l1); SETUP(l2); SETUP(l3); in rt_setup_sigcontext()
Dpseudodbg.c61 val = &fp->l0; in fix_up_reg()
Dkgdb.c44 gdb_regs[BFIN_L0] = regs->l0; in pt_regs_to_gdb_regs()
120 regs->l0 = gdb_regs[BFIN_L0]; in gdb_regs_to_pt_regs()

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