Searched refs:loads (Results 1 – 15 of 15) sorted by relevance
| /arch/alpha/lib/ |
| D | ev6-copy_user.S | 62 EXI( ldbu $1,0($17) ) # .. .. .. L : Keep loads separate from stores
114 EXI ( ldbu $2,0($17) ) # .. .. .. L : No loads in the same quad
201 EXI ( ldbu $2,0($17) ) # .. .. .. L : No loads in the same quad
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| /arch/mips/include/asm/ |
| D | mips-r2-to-r6-emul.h | 22 u64 loads; member
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| D | fpu_emulator.h | 37 unsigned long loads; member
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| /arch/arm64/ |
| D | Makefile | 43 KBUILD_CFLAGS += $(call cc-option, -mpc-relative-literal-loads)
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| D | Kconfig | 341 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
348 instructions to Write-Back memory are mixed with Device loads.
350 The workaround is to promote device loads to use Load-Acquire
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| /arch/mips/kernel/ |
| D | mips-r2-to-r6-emul.c | 1279 MIPS_R2_STATS(loads); in mipsr2_decoder()
1353 MIPS_R2_STATS(loads); in mipsr2_decoder()
1613 MIPS_R2_STATS(loads); in mipsr2_decoder()
1732 MIPS_R2_STATS(loads); in mipsr2_decoder()
2272 (unsigned long)__this_cpu_read(mipsr2emustats.loads), in mipsr2_stats_show()
2273 (unsigned long)__this_cpu_read(mipsr2bdemustats.loads)); in mipsr2_stats_show()
2329 __this_cpu_write((mipsr2emustats).loads, 0); in mipsr2_stats_clear_show()
2330 __this_cpu_write((mipsr2bdemustats).loads, 0); in mipsr2_stats_clear_show()
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| /arch/powerpc/lib/ |
| D | memcpy_64.S | 108 ld r9,0(r4) # 3+2n loads, 2+2n stores
120 0: ld r0,0(r4) # 4+2n loads, 3+2n stores
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| /arch/mips/math-emu/ |
| D | me-debugfs.c | 54 __this_cpu_write((fpuemustats).loads, 0); in fpuemustats_clear_show()
230 FPU_STAT_CREATE(loads); in debugfs_fpuemu()
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| D | cp1emu.c | 1065 MIPS_FPU_EMU_INC_STATS(loads); in cop1Emulate()
1100 MIPS_FPU_EMU_INC_STATS(loads); in cop1Emulate()
1496 MIPS_FPU_EMU_INC_STATS(loads); in fpux_emu()
1593 MIPS_FPU_EMU_INC_STATS(loads); in fpux_emu()
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| /arch/cris/boot/rescue/ |
| D | head_v10.S | 78 ;; The length is enough for downloading code that loads the rest
80 ;; It is the same length as the on-chip ROM loads, so the same
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| /arch/m68k/fpsp040/ |
| D | x_operr.S | 222 | Store_max loads the max pos or negative for the size, sets
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| /arch/x86/kernel/cpu/ |
| D | perf_event_intel.c | 216 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
217 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
3194 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
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| /arch/sh/ |
| D | Kconfig | 792 first part of the romImage which in turn loads the rest the kernel
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| /arch/arm/mm/ |
| D | Kconfig | 887 not perform speculative loads into the D-cache. For such
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| /arch/x86/ |
| D | Kconfig | 2017 If bootloader loads the kernel at a non-aligned address and
2021 If bootloader loads the kernel at a non-aligned address and
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