1 /*
2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
22 *
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
26 *
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware FPU at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
32 *
33 * Note if you know that you won't have an FPU, then you'll get much
34 * better performance by compiling with -msoft-float!
35 */
36 #include <linux/sched.h>
37 #include <linux/debugfs.h>
38 #include <linux/kconfig.h>
39 #include <linux/percpu-defs.h>
40 #include <linux/perf_event.h>
41
42 #include <asm/branch.h>
43 #include <asm/inst.h>
44 #include <asm/ptrace.h>
45 #include <asm/signal.h>
46 #include <asm/uaccess.h>
47
48 #include <asm/cpu-info.h>
49 #include <asm/processor.h>
50 #include <asm/fpu_emulator.h>
51 #include <asm/fpu.h>
52 #include <asm/mips-r2-to-r6-emul.h>
53
54 #include "ieee754.h"
55
56 /* Function which emulates a floating point instruction. */
57
58 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
59 mips_instruction);
60
61 static int fpux_emu(struct pt_regs *,
62 struct mips_fpu_struct *, mips_instruction, void *__user *);
63
64 /* Control registers */
65
66 #define FPCREG_RID 0 /* $0 = revision id */
67 #define FPCREG_FCCR 25 /* $25 = fccr */
68 #define FPCREG_FEXR 26 /* $26 = fexr */
69 #define FPCREG_FENR 28 /* $28 = fenr */
70 #define FPCREG_CSR 31 /* $31 = csr */
71
72 /* convert condition code register number to csr bit */
73 const unsigned int fpucondbit[8] = {
74 FPU_CSR_COND,
75 FPU_CSR_COND1,
76 FPU_CSR_COND2,
77 FPU_CSR_COND3,
78 FPU_CSR_COND4,
79 FPU_CSR_COND5,
80 FPU_CSR_COND6,
81 FPU_CSR_COND7
82 };
83
84 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
85 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
86 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
87 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
88 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
89
90 /*
91 * This functions translates a 32-bit microMIPS instruction
92 * into a 32-bit MIPS32 instruction. Returns 0 on success
93 * and SIGILL otherwise.
94 */
microMIPS32_to_MIPS32(union mips_instruction * insn_ptr)95 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
96 {
97 union mips_instruction insn = *insn_ptr;
98 union mips_instruction mips32_insn = insn;
99 int func, fmt, op;
100
101 switch (insn.mm_i_format.opcode) {
102 case mm_ldc132_op:
103 mips32_insn.mm_i_format.opcode = ldc1_op;
104 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
105 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
106 break;
107 case mm_lwc132_op:
108 mips32_insn.mm_i_format.opcode = lwc1_op;
109 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
110 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
111 break;
112 case mm_sdc132_op:
113 mips32_insn.mm_i_format.opcode = sdc1_op;
114 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
115 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
116 break;
117 case mm_swc132_op:
118 mips32_insn.mm_i_format.opcode = swc1_op;
119 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
120 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
121 break;
122 case mm_pool32i_op:
123 /* NOTE: offset is << by 1 if in microMIPS mode. */
124 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
125 (insn.mm_i_format.rt == mm_bc1t_op)) {
126 mips32_insn.fb_format.opcode = cop1_op;
127 mips32_insn.fb_format.bc = bc_op;
128 mips32_insn.fb_format.flag =
129 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
130 } else
131 return SIGILL;
132 break;
133 case mm_pool32f_op:
134 switch (insn.mm_fp0_format.func) {
135 case mm_32f_01_op:
136 case mm_32f_11_op:
137 case mm_32f_02_op:
138 case mm_32f_12_op:
139 case mm_32f_41_op:
140 case mm_32f_51_op:
141 case mm_32f_42_op:
142 case mm_32f_52_op:
143 op = insn.mm_fp0_format.func;
144 if (op == mm_32f_01_op)
145 func = madd_s_op;
146 else if (op == mm_32f_11_op)
147 func = madd_d_op;
148 else if (op == mm_32f_02_op)
149 func = nmadd_s_op;
150 else if (op == mm_32f_12_op)
151 func = nmadd_d_op;
152 else if (op == mm_32f_41_op)
153 func = msub_s_op;
154 else if (op == mm_32f_51_op)
155 func = msub_d_op;
156 else if (op == mm_32f_42_op)
157 func = nmsub_s_op;
158 else
159 func = nmsub_d_op;
160 mips32_insn.fp6_format.opcode = cop1x_op;
161 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
162 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
163 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
164 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
165 mips32_insn.fp6_format.func = func;
166 break;
167 case mm_32f_10_op:
168 func = -1; /* Invalid */
169 op = insn.mm_fp5_format.op & 0x7;
170 if (op == mm_ldxc1_op)
171 func = ldxc1_op;
172 else if (op == mm_sdxc1_op)
173 func = sdxc1_op;
174 else if (op == mm_lwxc1_op)
175 func = lwxc1_op;
176 else if (op == mm_swxc1_op)
177 func = swxc1_op;
178
179 if (func != -1) {
180 mips32_insn.r_format.opcode = cop1x_op;
181 mips32_insn.r_format.rs =
182 insn.mm_fp5_format.base;
183 mips32_insn.r_format.rt =
184 insn.mm_fp5_format.index;
185 mips32_insn.r_format.rd = 0;
186 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
187 mips32_insn.r_format.func = func;
188 } else
189 return SIGILL;
190 break;
191 case mm_32f_40_op:
192 op = -1; /* Invalid */
193 if (insn.mm_fp2_format.op == mm_fmovt_op)
194 op = 1;
195 else if (insn.mm_fp2_format.op == mm_fmovf_op)
196 op = 0;
197 if (op != -1) {
198 mips32_insn.fp0_format.opcode = cop1_op;
199 mips32_insn.fp0_format.fmt =
200 sdps_format[insn.mm_fp2_format.fmt];
201 mips32_insn.fp0_format.ft =
202 (insn.mm_fp2_format.cc<<2) + op;
203 mips32_insn.fp0_format.fs =
204 insn.mm_fp2_format.fs;
205 mips32_insn.fp0_format.fd =
206 insn.mm_fp2_format.fd;
207 mips32_insn.fp0_format.func = fmovc_op;
208 } else
209 return SIGILL;
210 break;
211 case mm_32f_60_op:
212 func = -1; /* Invalid */
213 if (insn.mm_fp0_format.op == mm_fadd_op)
214 func = fadd_op;
215 else if (insn.mm_fp0_format.op == mm_fsub_op)
216 func = fsub_op;
217 else if (insn.mm_fp0_format.op == mm_fmul_op)
218 func = fmul_op;
219 else if (insn.mm_fp0_format.op == mm_fdiv_op)
220 func = fdiv_op;
221 if (func != -1) {
222 mips32_insn.fp0_format.opcode = cop1_op;
223 mips32_insn.fp0_format.fmt =
224 sdps_format[insn.mm_fp0_format.fmt];
225 mips32_insn.fp0_format.ft =
226 insn.mm_fp0_format.ft;
227 mips32_insn.fp0_format.fs =
228 insn.mm_fp0_format.fs;
229 mips32_insn.fp0_format.fd =
230 insn.mm_fp0_format.fd;
231 mips32_insn.fp0_format.func = func;
232 } else
233 return SIGILL;
234 break;
235 case mm_32f_70_op:
236 func = -1; /* Invalid */
237 if (insn.mm_fp0_format.op == mm_fmovn_op)
238 func = fmovn_op;
239 else if (insn.mm_fp0_format.op == mm_fmovz_op)
240 func = fmovz_op;
241 if (func != -1) {
242 mips32_insn.fp0_format.opcode = cop1_op;
243 mips32_insn.fp0_format.fmt =
244 sdps_format[insn.mm_fp0_format.fmt];
245 mips32_insn.fp0_format.ft =
246 insn.mm_fp0_format.ft;
247 mips32_insn.fp0_format.fs =
248 insn.mm_fp0_format.fs;
249 mips32_insn.fp0_format.fd =
250 insn.mm_fp0_format.fd;
251 mips32_insn.fp0_format.func = func;
252 } else
253 return SIGILL;
254 break;
255 case mm_32f_73_op: /* POOL32FXF */
256 switch (insn.mm_fp1_format.op) {
257 case mm_movf0_op:
258 case mm_movf1_op:
259 case mm_movt0_op:
260 case mm_movt1_op:
261 if ((insn.mm_fp1_format.op & 0x7f) ==
262 mm_movf0_op)
263 op = 0;
264 else
265 op = 1;
266 mips32_insn.r_format.opcode = spec_op;
267 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
268 mips32_insn.r_format.rt =
269 (insn.mm_fp4_format.cc << 2) + op;
270 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
271 mips32_insn.r_format.re = 0;
272 mips32_insn.r_format.func = movc_op;
273 break;
274 case mm_fcvtd0_op:
275 case mm_fcvtd1_op:
276 case mm_fcvts0_op:
277 case mm_fcvts1_op:
278 if ((insn.mm_fp1_format.op & 0x7f) ==
279 mm_fcvtd0_op) {
280 func = fcvtd_op;
281 fmt = swl_format[insn.mm_fp3_format.fmt];
282 } else {
283 func = fcvts_op;
284 fmt = dwl_format[insn.mm_fp3_format.fmt];
285 }
286 mips32_insn.fp0_format.opcode = cop1_op;
287 mips32_insn.fp0_format.fmt = fmt;
288 mips32_insn.fp0_format.ft = 0;
289 mips32_insn.fp0_format.fs =
290 insn.mm_fp3_format.fs;
291 mips32_insn.fp0_format.fd =
292 insn.mm_fp3_format.rt;
293 mips32_insn.fp0_format.func = func;
294 break;
295 case mm_fmov0_op:
296 case mm_fmov1_op:
297 case mm_fabs0_op:
298 case mm_fabs1_op:
299 case mm_fneg0_op:
300 case mm_fneg1_op:
301 if ((insn.mm_fp1_format.op & 0x7f) ==
302 mm_fmov0_op)
303 func = fmov_op;
304 else if ((insn.mm_fp1_format.op & 0x7f) ==
305 mm_fabs0_op)
306 func = fabs_op;
307 else
308 func = fneg_op;
309 mips32_insn.fp0_format.opcode = cop1_op;
310 mips32_insn.fp0_format.fmt =
311 sdps_format[insn.mm_fp3_format.fmt];
312 mips32_insn.fp0_format.ft = 0;
313 mips32_insn.fp0_format.fs =
314 insn.mm_fp3_format.fs;
315 mips32_insn.fp0_format.fd =
316 insn.mm_fp3_format.rt;
317 mips32_insn.fp0_format.func = func;
318 break;
319 case mm_ffloorl_op:
320 case mm_ffloorw_op:
321 case mm_fceill_op:
322 case mm_fceilw_op:
323 case mm_ftruncl_op:
324 case mm_ftruncw_op:
325 case mm_froundl_op:
326 case mm_froundw_op:
327 case mm_fcvtl_op:
328 case mm_fcvtw_op:
329 if (insn.mm_fp1_format.op == mm_ffloorl_op)
330 func = ffloorl_op;
331 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
332 func = ffloor_op;
333 else if (insn.mm_fp1_format.op == mm_fceill_op)
334 func = fceill_op;
335 else if (insn.mm_fp1_format.op == mm_fceilw_op)
336 func = fceil_op;
337 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
338 func = ftruncl_op;
339 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
340 func = ftrunc_op;
341 else if (insn.mm_fp1_format.op == mm_froundl_op)
342 func = froundl_op;
343 else if (insn.mm_fp1_format.op == mm_froundw_op)
344 func = fround_op;
345 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
346 func = fcvtl_op;
347 else
348 func = fcvtw_op;
349 mips32_insn.fp0_format.opcode = cop1_op;
350 mips32_insn.fp0_format.fmt =
351 sd_format[insn.mm_fp1_format.fmt];
352 mips32_insn.fp0_format.ft = 0;
353 mips32_insn.fp0_format.fs =
354 insn.mm_fp1_format.fs;
355 mips32_insn.fp0_format.fd =
356 insn.mm_fp1_format.rt;
357 mips32_insn.fp0_format.func = func;
358 break;
359 case mm_frsqrt_op:
360 case mm_fsqrt_op:
361 case mm_frecip_op:
362 if (insn.mm_fp1_format.op == mm_frsqrt_op)
363 func = frsqrt_op;
364 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
365 func = fsqrt_op;
366 else
367 func = frecip_op;
368 mips32_insn.fp0_format.opcode = cop1_op;
369 mips32_insn.fp0_format.fmt =
370 sdps_format[insn.mm_fp1_format.fmt];
371 mips32_insn.fp0_format.ft = 0;
372 mips32_insn.fp0_format.fs =
373 insn.mm_fp1_format.fs;
374 mips32_insn.fp0_format.fd =
375 insn.mm_fp1_format.rt;
376 mips32_insn.fp0_format.func = func;
377 break;
378 case mm_mfc1_op:
379 case mm_mtc1_op:
380 case mm_cfc1_op:
381 case mm_ctc1_op:
382 case mm_mfhc1_op:
383 case mm_mthc1_op:
384 if (insn.mm_fp1_format.op == mm_mfc1_op)
385 op = mfc_op;
386 else if (insn.mm_fp1_format.op == mm_mtc1_op)
387 op = mtc_op;
388 else if (insn.mm_fp1_format.op == mm_cfc1_op)
389 op = cfc_op;
390 else if (insn.mm_fp1_format.op == mm_ctc1_op)
391 op = ctc_op;
392 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
393 op = mfhc_op;
394 else
395 op = mthc_op;
396 mips32_insn.fp1_format.opcode = cop1_op;
397 mips32_insn.fp1_format.op = op;
398 mips32_insn.fp1_format.rt =
399 insn.mm_fp1_format.rt;
400 mips32_insn.fp1_format.fs =
401 insn.mm_fp1_format.fs;
402 mips32_insn.fp1_format.fd = 0;
403 mips32_insn.fp1_format.func = 0;
404 break;
405 default:
406 return SIGILL;
407 }
408 break;
409 case mm_32f_74_op: /* c.cond.fmt */
410 mips32_insn.fp0_format.opcode = cop1_op;
411 mips32_insn.fp0_format.fmt =
412 sdps_format[insn.mm_fp4_format.fmt];
413 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
414 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
415 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
416 mips32_insn.fp0_format.func =
417 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
418 break;
419 default:
420 return SIGILL;
421 }
422 break;
423 default:
424 return SIGILL;
425 }
426
427 *insn_ptr = mips32_insn;
428 return 0;
429 }
430
431 /*
432 * Redundant with logic already in kernel/branch.c,
433 * embedded in compute_return_epc. At some point,
434 * a single subroutine should be used across both
435 * modules.
436 */
isBranchInstr(struct pt_regs * regs,struct mm_decoded_insn dec_insn,unsigned long * contpc)437 int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
438 unsigned long *contpc)
439 {
440 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
441 unsigned int fcr31;
442 unsigned int bit = 0;
443 unsigned int bit0;
444 union fpureg *fpr;
445
446 switch (insn.i_format.opcode) {
447 case spec_op:
448 switch (insn.r_format.func) {
449 case jalr_op:
450 if (insn.r_format.rd != 0) {
451 regs->regs[insn.r_format.rd] =
452 regs->cp0_epc + dec_insn.pc_inc +
453 dec_insn.next_pc_inc;
454 }
455 /* fall through */
456 case jr_op:
457 /* For R6, JR already emulated in jalr_op */
458 if (NO_R6EMU && insn.r_format.func == jr_op)
459 break;
460 *contpc = regs->regs[insn.r_format.rs];
461 return 1;
462 }
463 break;
464 case bcond_op:
465 switch (insn.i_format.rt) {
466 case bltzal_op:
467 case bltzall_op:
468 if (NO_R6EMU && (insn.i_format.rs ||
469 insn.i_format.rt == bltzall_op))
470 break;
471
472 regs->regs[31] = regs->cp0_epc +
473 dec_insn.pc_inc +
474 dec_insn.next_pc_inc;
475 /* fall through */
476 case bltzl_op:
477 if (NO_R6EMU)
478 break;
479 /* fall through */
480 case bltz_op:
481 if ((long)regs->regs[insn.i_format.rs] < 0)
482 *contpc = regs->cp0_epc +
483 dec_insn.pc_inc +
484 (insn.i_format.simmediate << 2);
485 else
486 *contpc = regs->cp0_epc +
487 dec_insn.pc_inc +
488 dec_insn.next_pc_inc;
489 return 1;
490 case bgezal_op:
491 case bgezall_op:
492 if (NO_R6EMU && (insn.i_format.rs ||
493 insn.i_format.rt == bgezall_op))
494 break;
495
496 regs->regs[31] = regs->cp0_epc +
497 dec_insn.pc_inc +
498 dec_insn.next_pc_inc;
499 /* fall through */
500 case bgezl_op:
501 if (NO_R6EMU)
502 break;
503 /* fall through */
504 case bgez_op:
505 if ((long)regs->regs[insn.i_format.rs] >= 0)
506 *contpc = regs->cp0_epc +
507 dec_insn.pc_inc +
508 (insn.i_format.simmediate << 2);
509 else
510 *contpc = regs->cp0_epc +
511 dec_insn.pc_inc +
512 dec_insn.next_pc_inc;
513 return 1;
514 }
515 break;
516 case jalx_op:
517 set_isa16_mode(bit);
518 /* fall through */
519 case jal_op:
520 regs->regs[31] = regs->cp0_epc +
521 dec_insn.pc_inc +
522 dec_insn.next_pc_inc;
523 /* fall through */
524 case j_op:
525 *contpc = regs->cp0_epc + dec_insn.pc_inc;
526 *contpc >>= 28;
527 *contpc <<= 28;
528 *contpc |= (insn.j_format.target << 2);
529 /* Set microMIPS mode bit: XOR for jalx. */
530 *contpc ^= bit;
531 return 1;
532 case beql_op:
533 if (NO_R6EMU)
534 break;
535 /* fall through */
536 case beq_op:
537 if (regs->regs[insn.i_format.rs] ==
538 regs->regs[insn.i_format.rt])
539 *contpc = regs->cp0_epc +
540 dec_insn.pc_inc +
541 (insn.i_format.simmediate << 2);
542 else
543 *contpc = regs->cp0_epc +
544 dec_insn.pc_inc +
545 dec_insn.next_pc_inc;
546 return 1;
547 case bnel_op:
548 if (NO_R6EMU)
549 break;
550 /* fall through */
551 case bne_op:
552 if (regs->regs[insn.i_format.rs] !=
553 regs->regs[insn.i_format.rt])
554 *contpc = regs->cp0_epc +
555 dec_insn.pc_inc +
556 (insn.i_format.simmediate << 2);
557 else
558 *contpc = regs->cp0_epc +
559 dec_insn.pc_inc +
560 dec_insn.next_pc_inc;
561 return 1;
562 case blezl_op:
563 if (!insn.i_format.rt && NO_R6EMU)
564 break;
565 /* fall through */
566 case blez_op:
567
568 /*
569 * Compact branches for R6 for the
570 * blez and blezl opcodes.
571 * BLEZ | rs = 0 | rt != 0 == BLEZALC
572 * BLEZ | rs = rt != 0 == BGEZALC
573 * BLEZ | rs != 0 | rt != 0 == BGEUC
574 * BLEZL | rs = 0 | rt != 0 == BLEZC
575 * BLEZL | rs = rt != 0 == BGEZC
576 * BLEZL | rs != 0 | rt != 0 == BGEC
577 *
578 * For real BLEZ{,L}, rt is always 0.
579 */
580 if (cpu_has_mips_r6 && insn.i_format.rt) {
581 if ((insn.i_format.opcode == blez_op) &&
582 ((!insn.i_format.rs && insn.i_format.rt) ||
583 (insn.i_format.rs == insn.i_format.rt)))
584 regs->regs[31] = regs->cp0_epc +
585 dec_insn.pc_inc;
586 *contpc = regs->cp0_epc + dec_insn.pc_inc +
587 dec_insn.next_pc_inc;
588
589 return 1;
590 }
591 if ((long)regs->regs[insn.i_format.rs] <= 0)
592 *contpc = regs->cp0_epc +
593 dec_insn.pc_inc +
594 (insn.i_format.simmediate << 2);
595 else
596 *contpc = regs->cp0_epc +
597 dec_insn.pc_inc +
598 dec_insn.next_pc_inc;
599 return 1;
600 case bgtzl_op:
601 if (!insn.i_format.rt && NO_R6EMU)
602 break;
603 /* fall through */
604 case bgtz_op:
605 /*
606 * Compact branches for R6 for the
607 * bgtz and bgtzl opcodes.
608 * BGTZ | rs = 0 | rt != 0 == BGTZALC
609 * BGTZ | rs = rt != 0 == BLTZALC
610 * BGTZ | rs != 0 | rt != 0 == BLTUC
611 * BGTZL | rs = 0 | rt != 0 == BGTZC
612 * BGTZL | rs = rt != 0 == BLTZC
613 * BGTZL | rs != 0 | rt != 0 == BLTC
614 *
615 * *ZALC varint for BGTZ &&& rt != 0
616 * For real GTZ{,L}, rt is always 0.
617 */
618 if (cpu_has_mips_r6 && insn.i_format.rt) {
619 if ((insn.i_format.opcode == blez_op) &&
620 ((!insn.i_format.rs && insn.i_format.rt) ||
621 (insn.i_format.rs == insn.i_format.rt)))
622 regs->regs[31] = regs->cp0_epc +
623 dec_insn.pc_inc;
624 *contpc = regs->cp0_epc + dec_insn.pc_inc +
625 dec_insn.next_pc_inc;
626
627 return 1;
628 }
629
630 if ((long)regs->regs[insn.i_format.rs] > 0)
631 *contpc = regs->cp0_epc +
632 dec_insn.pc_inc +
633 (insn.i_format.simmediate << 2);
634 else
635 *contpc = regs->cp0_epc +
636 dec_insn.pc_inc +
637 dec_insn.next_pc_inc;
638 return 1;
639 case pop10_op:
640 case pop30_op:
641 if (!cpu_has_mips_r6)
642 break;
643 if (insn.i_format.rt && !insn.i_format.rs)
644 regs->regs[31] = regs->cp0_epc + 4;
645 *contpc = regs->cp0_epc + dec_insn.pc_inc +
646 dec_insn.next_pc_inc;
647
648 return 1;
649 #ifdef CONFIG_CPU_CAVIUM_OCTEON
650 case lwc2_op: /* This is bbit0 on Octeon */
651 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
652 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
653 else
654 *contpc = regs->cp0_epc + 8;
655 return 1;
656 case ldc2_op: /* This is bbit032 on Octeon */
657 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
658 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
659 else
660 *contpc = regs->cp0_epc + 8;
661 return 1;
662 case swc2_op: /* This is bbit1 on Octeon */
663 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
664 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
665 else
666 *contpc = regs->cp0_epc + 8;
667 return 1;
668 case sdc2_op: /* This is bbit132 on Octeon */
669 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
670 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
671 else
672 *contpc = regs->cp0_epc + 8;
673 return 1;
674 #else
675 case bc6_op:
676 /*
677 * Only valid for MIPS R6 but we can still end up
678 * here from a broken userland so just tell emulator
679 * this is not a branch and let it break later on.
680 */
681 if (!cpu_has_mips_r6)
682 break;
683 *contpc = regs->cp0_epc + dec_insn.pc_inc +
684 dec_insn.next_pc_inc;
685
686 return 1;
687 case balc6_op:
688 if (!cpu_has_mips_r6)
689 break;
690 regs->regs[31] = regs->cp0_epc + 4;
691 *contpc = regs->cp0_epc + dec_insn.pc_inc +
692 dec_insn.next_pc_inc;
693
694 return 1;
695 case pop66_op:
696 if (!cpu_has_mips_r6)
697 break;
698 *contpc = regs->cp0_epc + dec_insn.pc_inc +
699 dec_insn.next_pc_inc;
700
701 return 1;
702 case pop76_op:
703 if (!cpu_has_mips_r6)
704 break;
705 if (!insn.i_format.rs)
706 regs->regs[31] = regs->cp0_epc + 4;
707 *contpc = regs->cp0_epc + dec_insn.pc_inc +
708 dec_insn.next_pc_inc;
709
710 return 1;
711 #endif
712 case cop0_op:
713 case cop1_op:
714 /* Need to check for R6 bc1nez and bc1eqz branches */
715 if (cpu_has_mips_r6 &&
716 ((insn.i_format.rs == bc1eqz_op) ||
717 (insn.i_format.rs == bc1nez_op))) {
718 bit = 0;
719 fpr = ¤t->thread.fpu.fpr[insn.i_format.rt];
720 bit0 = get_fpr32(fpr, 0) & 0x1;
721 switch (insn.i_format.rs) {
722 case bc1eqz_op:
723 bit = bit0 == 0;
724 break;
725 case bc1nez_op:
726 bit = bit0 != 0;
727 break;
728 }
729 if (bit)
730 *contpc = regs->cp0_epc +
731 dec_insn.pc_inc +
732 (insn.i_format.simmediate << 2);
733 else
734 *contpc = regs->cp0_epc +
735 dec_insn.pc_inc +
736 dec_insn.next_pc_inc;
737
738 return 1;
739 }
740 /* R2/R6 compatible cop1 instruction */
741 /* fall through */
742 case cop2_op:
743 case cop1x_op:
744 if (insn.i_format.rs == bc_op) {
745 preempt_disable();
746 if (is_fpu_owner())
747 fcr31 = read_32bit_cp1_register(CP1_STATUS);
748 else
749 fcr31 = current->thread.fpu.fcr31;
750 preempt_enable();
751
752 bit = (insn.i_format.rt >> 2);
753 bit += (bit != 0);
754 bit += 23;
755 switch (insn.i_format.rt & 3) {
756 case 0: /* bc1f */
757 case 2: /* bc1fl */
758 if (~fcr31 & (1 << bit))
759 *contpc = regs->cp0_epc +
760 dec_insn.pc_inc +
761 (insn.i_format.simmediate << 2);
762 else
763 *contpc = regs->cp0_epc +
764 dec_insn.pc_inc +
765 dec_insn.next_pc_inc;
766 return 1;
767 case 1: /* bc1t */
768 case 3: /* bc1tl */
769 if (fcr31 & (1 << bit))
770 *contpc = regs->cp0_epc +
771 dec_insn.pc_inc +
772 (insn.i_format.simmediate << 2);
773 else
774 *contpc = regs->cp0_epc +
775 dec_insn.pc_inc +
776 dec_insn.next_pc_inc;
777 return 1;
778 }
779 }
780 break;
781 }
782 return 0;
783 }
784
785 /*
786 * In the Linux kernel, we support selection of FPR format on the
787 * basis of the Status.FR bit. If an FPU is not present, the FR bit
788 * is hardwired to zero, which would imply a 32-bit FPU even for
789 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
790 * FPU emu is slow and bulky and optimizing this function offers fairly
791 * sizeable benefits so we try to be clever and make this function return
792 * a constant whenever possible, that is on 64-bit kernels without O32
793 * compatibility enabled and on 32-bit without 64-bit FPU support.
794 */
cop1_64bit(struct pt_regs * xcp)795 static inline int cop1_64bit(struct pt_regs *xcp)
796 {
797 if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
798 return 1;
799 else if (config_enabled(CONFIG_32BIT) &&
800 !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
801 return 0;
802
803 return !test_thread_flag(TIF_32BIT_FPREGS);
804 }
805
hybrid_fprs(void)806 static inline bool hybrid_fprs(void)
807 {
808 return test_thread_flag(TIF_HYBRID_FPREGS);
809 }
810
811 #define SIFROMREG(si, x) \
812 do { \
813 if (cop1_64bit(xcp) && !hybrid_fprs()) \
814 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \
815 else \
816 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
817 } while (0)
818
819 #define SITOREG(si, x) \
820 do { \
821 if (cop1_64bit(xcp) && !hybrid_fprs()) { \
822 unsigned int i; \
823 set_fpr32(&ctx->fpr[x], 0, si); \
824 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
825 set_fpr32(&ctx->fpr[x], i, 0); \
826 } else { \
827 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
828 } \
829 } while (0)
830
831 #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
832
833 #define SITOHREG(si, x) \
834 do { \
835 unsigned int i; \
836 set_fpr32(&ctx->fpr[x], 1, si); \
837 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
838 set_fpr32(&ctx->fpr[x], i, 0); \
839 } while (0)
840
841 #define DIFROMREG(di, x) \
842 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) ^ 1)], 0))
843
844 #define DITOREG(di, x) \
845 do { \
846 unsigned int fpr, i; \
847 fpr = (x) & ~(cop1_64bit(xcp) ^ 1); \
848 set_fpr64(&ctx->fpr[fpr], 0, di); \
849 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
850 set_fpr64(&ctx->fpr[fpr], i, 0); \
851 } while (0)
852
853 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
854 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
855 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
856 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
857
858 /*
859 * Emulate a CFC1 instruction.
860 */
cop1_cfc(struct pt_regs * xcp,struct mips_fpu_struct * ctx,mips_instruction ir)861 static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
862 mips_instruction ir)
863 {
864 u32 fcr31 = ctx->fcr31;
865 u32 value = 0;
866
867 switch (MIPSInst_RD(ir)) {
868 case FPCREG_CSR:
869 value = fcr31;
870 pr_debug("%p gpr[%d]<-csr=%08x\n",
871 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
872 break;
873
874 case FPCREG_FENR:
875 if (!cpu_has_mips_r)
876 break;
877 value = (fcr31 >> (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
878 MIPS_FENR_FS;
879 value |= fcr31 & (FPU_CSR_ALL_E | FPU_CSR_RM);
880 pr_debug("%p gpr[%d]<-enr=%08x\n",
881 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
882 break;
883
884 case FPCREG_FEXR:
885 if (!cpu_has_mips_r)
886 break;
887 value = fcr31 & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
888 pr_debug("%p gpr[%d]<-exr=%08x\n",
889 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
890 break;
891
892 case FPCREG_FCCR:
893 if (!cpu_has_mips_r)
894 break;
895 value = (fcr31 >> (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
896 MIPS_FCCR_COND0;
897 value |= (fcr31 >> (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
898 (MIPS_FCCR_CONDX & ~MIPS_FCCR_COND0);
899 pr_debug("%p gpr[%d]<-ccr=%08x\n",
900 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
901 break;
902
903 case FPCREG_RID:
904 value = boot_cpu_data.fpu_id;
905 break;
906
907 default:
908 break;
909 }
910
911 if (MIPSInst_RT(ir))
912 xcp->regs[MIPSInst_RT(ir)] = value;
913 }
914
915 /*
916 * Emulate a CTC1 instruction.
917 */
cop1_ctc(struct pt_regs * xcp,struct mips_fpu_struct * ctx,mips_instruction ir)918 static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
919 mips_instruction ir)
920 {
921 u32 fcr31 = ctx->fcr31;
922 u32 value;
923 u32 mask;
924
925 if (MIPSInst_RT(ir) == 0)
926 value = 0;
927 else
928 value = xcp->regs[MIPSInst_RT(ir)];
929
930 switch (MIPSInst_RD(ir)) {
931 case FPCREG_CSR:
932 pr_debug("%p gpr[%d]->csr=%08x\n",
933 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
934
935 /* Preserve read-only bits. */
936 mask = boot_cpu_data.fpu_msk31;
937 fcr31 = (value & ~mask) | (fcr31 & mask);
938 break;
939
940 case FPCREG_FENR:
941 if (!cpu_has_mips_r)
942 break;
943 pr_debug("%p gpr[%d]->enr=%08x\n",
944 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
945 fcr31 &= ~(FPU_CSR_FS | FPU_CSR_ALL_E | FPU_CSR_RM);
946 fcr31 |= (value << (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
947 FPU_CSR_FS;
948 fcr31 |= value & (FPU_CSR_ALL_E | FPU_CSR_RM);
949 break;
950
951 case FPCREG_FEXR:
952 if (!cpu_has_mips_r)
953 break;
954 pr_debug("%p gpr[%d]->exr=%08x\n",
955 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
956 fcr31 &= ~(FPU_CSR_ALL_X | FPU_CSR_ALL_S);
957 fcr31 |= value & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
958 break;
959
960 case FPCREG_FCCR:
961 if (!cpu_has_mips_r)
962 break;
963 pr_debug("%p gpr[%d]->ccr=%08x\n",
964 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
965 fcr31 &= ~(FPU_CSR_CONDX | FPU_CSR_COND);
966 fcr31 |= (value << (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
967 FPU_CSR_COND;
968 fcr31 |= (value << (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
969 FPU_CSR_CONDX;
970 break;
971
972 default:
973 break;
974 }
975
976 ctx->fcr31 = fcr31;
977 }
978
979 /*
980 * Emulate the single floating point instruction pointed at by EPC.
981 * Two instructions if the instruction is in a branch delay slot.
982 */
983
cop1Emulate(struct pt_regs * xcp,struct mips_fpu_struct * ctx,struct mm_decoded_insn dec_insn,void * __user * fault_addr)984 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
985 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
986 {
987 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
988 unsigned int cond, cbit, bit0;
989 mips_instruction ir;
990 int likely, pc_inc;
991 union fpureg *fpr;
992 u32 __user *wva;
993 u64 __user *dva;
994 u32 wval;
995 u64 dval;
996 int sig;
997
998 /*
999 * These are giving gcc a gentle hint about what to expect in
1000 * dec_inst in order to do better optimization.
1001 */
1002 if (!cpu_has_mmips && dec_insn.micro_mips_mode)
1003 unreachable();
1004
1005 /* XXX NEC Vr54xx bug workaround */
1006 if (delay_slot(xcp)) {
1007 if (dec_insn.micro_mips_mode) {
1008 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
1009 clear_delay_slot(xcp);
1010 } else {
1011 if (!isBranchInstr(xcp, dec_insn, &contpc))
1012 clear_delay_slot(xcp);
1013 }
1014 }
1015
1016 if (delay_slot(xcp)) {
1017 /*
1018 * The instruction to be emulated is in a branch delay slot
1019 * which means that we have to emulate the branch instruction
1020 * BEFORE we do the cop1 instruction.
1021 *
1022 * This branch could be a COP1 branch, but in that case we
1023 * would have had a trap for that instruction, and would not
1024 * come through this route.
1025 *
1026 * Linux MIPS branch emulator operates on context, updating the
1027 * cp0_epc.
1028 */
1029 ir = dec_insn.next_insn; /* process delay slot instr */
1030 pc_inc = dec_insn.next_pc_inc;
1031 } else {
1032 ir = dec_insn.insn; /* process current instr */
1033 pc_inc = dec_insn.pc_inc;
1034 }
1035
1036 /*
1037 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
1038 * instructions, we want to convert microMIPS FPU instructions
1039 * into MIPS32 instructions so that we could reuse all of the
1040 * FPU emulation code.
1041 *
1042 * NOTE: We cannot do this for branch instructions since they
1043 * are not a subset. Example: Cannot emulate a 16-bit
1044 * aligned target address with a MIPS32 instruction.
1045 */
1046 if (dec_insn.micro_mips_mode) {
1047 /*
1048 * If next instruction is a 16-bit instruction, then it
1049 * it cannot be a FPU instruction. This could happen
1050 * since we can be called for non-FPU instructions.
1051 */
1052 if ((pc_inc == 2) ||
1053 (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
1054 == SIGILL))
1055 return SIGILL;
1056 }
1057
1058 emul:
1059 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
1060 MIPS_FPU_EMU_INC_STATS(emulated);
1061 switch (MIPSInst_OPCODE(ir)) {
1062 case ldc1_op:
1063 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1064 MIPSInst_SIMM(ir));
1065 MIPS_FPU_EMU_INC_STATS(loads);
1066
1067 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
1068 MIPS_FPU_EMU_INC_STATS(errors);
1069 *fault_addr = dva;
1070 return SIGBUS;
1071 }
1072 if (__get_user(dval, dva)) {
1073 MIPS_FPU_EMU_INC_STATS(errors);
1074 *fault_addr = dva;
1075 return SIGSEGV;
1076 }
1077 DITOREG(dval, MIPSInst_RT(ir));
1078 break;
1079
1080 case sdc1_op:
1081 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1082 MIPSInst_SIMM(ir));
1083 MIPS_FPU_EMU_INC_STATS(stores);
1084 DIFROMREG(dval, MIPSInst_RT(ir));
1085 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
1086 MIPS_FPU_EMU_INC_STATS(errors);
1087 *fault_addr = dva;
1088 return SIGBUS;
1089 }
1090 if (__put_user(dval, dva)) {
1091 MIPS_FPU_EMU_INC_STATS(errors);
1092 *fault_addr = dva;
1093 return SIGSEGV;
1094 }
1095 break;
1096
1097 case lwc1_op:
1098 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1099 MIPSInst_SIMM(ir));
1100 MIPS_FPU_EMU_INC_STATS(loads);
1101 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
1102 MIPS_FPU_EMU_INC_STATS(errors);
1103 *fault_addr = wva;
1104 return SIGBUS;
1105 }
1106 if (__get_user(wval, wva)) {
1107 MIPS_FPU_EMU_INC_STATS(errors);
1108 *fault_addr = wva;
1109 return SIGSEGV;
1110 }
1111 SITOREG(wval, MIPSInst_RT(ir));
1112 break;
1113
1114 case swc1_op:
1115 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1116 MIPSInst_SIMM(ir));
1117 MIPS_FPU_EMU_INC_STATS(stores);
1118 SIFROMREG(wval, MIPSInst_RT(ir));
1119 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
1120 MIPS_FPU_EMU_INC_STATS(errors);
1121 *fault_addr = wva;
1122 return SIGBUS;
1123 }
1124 if (__put_user(wval, wva)) {
1125 MIPS_FPU_EMU_INC_STATS(errors);
1126 *fault_addr = wva;
1127 return SIGSEGV;
1128 }
1129 break;
1130
1131 case cop1_op:
1132 switch (MIPSInst_RS(ir)) {
1133 case dmfc_op:
1134 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1135 return SIGILL;
1136
1137 /* copregister fs -> gpr[rt] */
1138 if (MIPSInst_RT(ir) != 0) {
1139 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1140 MIPSInst_RD(ir));
1141 }
1142 break;
1143
1144 case dmtc_op:
1145 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1146 return SIGILL;
1147
1148 /* copregister fs <- rt */
1149 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1150 break;
1151
1152 case mfhc_op:
1153 if (!cpu_has_mips_r2_r6)
1154 goto sigill;
1155
1156 /* copregister rd -> gpr[rt] */
1157 if (MIPSInst_RT(ir) != 0) {
1158 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1159 MIPSInst_RD(ir));
1160 }
1161 break;
1162
1163 case mthc_op:
1164 if (!cpu_has_mips_r2_r6)
1165 goto sigill;
1166
1167 /* copregister rd <- gpr[rt] */
1168 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1169 break;
1170
1171 case mfc_op:
1172 /* copregister rd -> gpr[rt] */
1173 if (MIPSInst_RT(ir) != 0) {
1174 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1175 MIPSInst_RD(ir));
1176 }
1177 break;
1178
1179 case mtc_op:
1180 /* copregister rd <- rt */
1181 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1182 break;
1183
1184 case cfc_op:
1185 /* cop control register rd -> gpr[rt] */
1186 cop1_cfc(xcp, ctx, ir);
1187 break;
1188
1189 case ctc_op:
1190 /* copregister rd <- rt */
1191 cop1_ctc(xcp, ctx, ir);
1192 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1193 return SIGFPE;
1194 }
1195 break;
1196
1197 case bc1eqz_op:
1198 case bc1nez_op:
1199 if (!cpu_has_mips_r6 || delay_slot(xcp))
1200 return SIGILL;
1201
1202 cond = likely = 0;
1203 fpr = ¤t->thread.fpu.fpr[MIPSInst_RT(ir)];
1204 bit0 = get_fpr32(fpr, 0) & 0x1;
1205 switch (MIPSInst_RS(ir)) {
1206 case bc1eqz_op:
1207 MIPS_FPU_EMU_INC_STATS(bc1eqz);
1208 cond = bit0 == 0;
1209 break;
1210 case bc1nez_op:
1211 MIPS_FPU_EMU_INC_STATS(bc1nez);
1212 cond = bit0 != 0;
1213 break;
1214 }
1215 goto branch_common;
1216
1217 case bc_op:
1218 if (delay_slot(xcp))
1219 return SIGILL;
1220
1221 if (cpu_has_mips_4_5_r)
1222 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1223 else
1224 cbit = FPU_CSR_COND;
1225 cond = ctx->fcr31 & cbit;
1226
1227 likely = 0;
1228 switch (MIPSInst_RT(ir) & 3) {
1229 case bcfl_op:
1230 if (cpu_has_mips_2_3_4_5_r)
1231 likely = 1;
1232 /* fall through */
1233 case bcf_op:
1234 cond = !cond;
1235 break;
1236 case bctl_op:
1237 if (cpu_has_mips_2_3_4_5_r)
1238 likely = 1;
1239 /* fall through */
1240 case bct_op:
1241 break;
1242 }
1243 branch_common:
1244 MIPS_FPU_EMU_INC_STATS(branches);
1245 set_delay_slot(xcp);
1246 if (cond) {
1247 /*
1248 * Branch taken: emulate dslot instruction
1249 */
1250 unsigned long bcpc;
1251
1252 /*
1253 * Remember EPC at the branch to point back
1254 * at so that any delay-slot instruction
1255 * signal is not silently ignored.
1256 */
1257 bcpc = xcp->cp0_epc;
1258 xcp->cp0_epc += dec_insn.pc_inc;
1259
1260 contpc = MIPSInst_SIMM(ir);
1261 ir = dec_insn.next_insn;
1262 if (dec_insn.micro_mips_mode) {
1263 contpc = (xcp->cp0_epc + (contpc << 1));
1264
1265 /* If 16-bit instruction, not FPU. */
1266 if ((dec_insn.next_pc_inc == 2) ||
1267 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1268
1269 /*
1270 * Since this instruction will
1271 * be put on the stack with
1272 * 32-bit words, get around
1273 * this problem by putting a
1274 * NOP16 as the second one.
1275 */
1276 if (dec_insn.next_pc_inc == 2)
1277 ir = (ir & (~0xffff)) | MM_NOP16;
1278
1279 /*
1280 * Single step the non-CP1
1281 * instruction in the dslot.
1282 */
1283 sig = mips_dsemul(xcp, ir,
1284 bcpc, contpc);
1285 if (sig < 0)
1286 break;
1287 if (sig)
1288 xcp->cp0_epc = bcpc;
1289 /*
1290 * SIGILL forces out of
1291 * the emulation loop.
1292 */
1293 return sig ? sig : SIGILL;
1294 }
1295 } else
1296 contpc = (xcp->cp0_epc + (contpc << 2));
1297
1298 switch (MIPSInst_OPCODE(ir)) {
1299 case lwc1_op:
1300 case swc1_op:
1301 goto emul;
1302
1303 case ldc1_op:
1304 case sdc1_op:
1305 if (cpu_has_mips_2_3_4_5_r)
1306 goto emul;
1307
1308 goto bc_sigill;
1309
1310 case cop1_op:
1311 goto emul;
1312
1313 case cop1x_op:
1314 if (cpu_has_mips_4_5_64_r2_r6)
1315 /* its one of ours */
1316 goto emul;
1317
1318 goto bc_sigill;
1319
1320 case spec_op:
1321 switch (MIPSInst_FUNC(ir)) {
1322 case movc_op:
1323 if (cpu_has_mips_4_5_r)
1324 goto emul;
1325
1326 goto bc_sigill;
1327 }
1328 break;
1329
1330 bc_sigill:
1331 xcp->cp0_epc = bcpc;
1332 return SIGILL;
1333 }
1334
1335 /*
1336 * Single step the non-cp1
1337 * instruction in the dslot
1338 */
1339 sig = mips_dsemul(xcp, ir, bcpc, contpc);
1340 if (sig < 0)
1341 break;
1342 if (sig)
1343 xcp->cp0_epc = bcpc;
1344 /* SIGILL forces out of the emulation loop. */
1345 return sig ? sig : SIGILL;
1346 } else if (likely) { /* branch not taken */
1347 /*
1348 * branch likely nullifies
1349 * dslot if not taken
1350 */
1351 xcp->cp0_epc += dec_insn.pc_inc;
1352 contpc += dec_insn.pc_inc;
1353 /*
1354 * else continue & execute
1355 * dslot as normal insn
1356 */
1357 }
1358 break;
1359
1360 default:
1361 if (!(MIPSInst_RS(ir) & 0x10))
1362 return SIGILL;
1363
1364 /* a real fpu computation instruction */
1365 sig = fpu_emu(xcp, ctx, ir);
1366 if (sig)
1367 return sig;
1368 }
1369 break;
1370
1371 case cop1x_op:
1372 if (!cpu_has_mips_4_5_64_r2_r6)
1373 return SIGILL;
1374
1375 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1376 if (sig)
1377 return sig;
1378 break;
1379
1380 case spec_op:
1381 if (!cpu_has_mips_4_5_r)
1382 return SIGILL;
1383
1384 if (MIPSInst_FUNC(ir) != movc_op)
1385 return SIGILL;
1386 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1387 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1388 xcp->regs[MIPSInst_RD(ir)] =
1389 xcp->regs[MIPSInst_RS(ir)];
1390 break;
1391 default:
1392 sigill:
1393 return SIGILL;
1394 }
1395
1396 /* we did it !! */
1397 xcp->cp0_epc = contpc;
1398 clear_delay_slot(xcp);
1399
1400 return 0;
1401 }
1402
1403 /*
1404 * Conversion table from MIPS compare ops 48-63
1405 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1406 */
1407 static const unsigned char cmptab[8] = {
1408 0, /* cmp_0 (sig) cmp_sf */
1409 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
1410 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
1411 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
1412 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
1413 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
1414 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
1415 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
1416 };
1417
1418 static const unsigned char negative_cmptab[8] = {
1419 0, /* Reserved */
1420 IEEE754_CLT | IEEE754_CGT | IEEE754_CEQ,
1421 IEEE754_CLT | IEEE754_CGT | IEEE754_CUN,
1422 IEEE754_CLT | IEEE754_CGT,
1423 /* Reserved */
1424 };
1425
1426
1427 /*
1428 * Additional MIPS4 instructions
1429 */
1430
1431 #define DEF3OP(name, p, f1, f2, f3) \
1432 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
1433 union ieee754##p s, union ieee754##p t) \
1434 { \
1435 struct _ieee754_csr ieee754_csr_save; \
1436 s = f1(s, t); \
1437 ieee754_csr_save = ieee754_csr; \
1438 s = f2(s, r); \
1439 ieee754_csr_save.cx |= ieee754_csr.cx; \
1440 ieee754_csr_save.sx |= ieee754_csr.sx; \
1441 s = f3(s); \
1442 ieee754_csr.cx |= ieee754_csr_save.cx; \
1443 ieee754_csr.sx |= ieee754_csr_save.sx; \
1444 return s; \
1445 }
1446
fpemu_dp_recip(union ieee754dp d)1447 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1448 {
1449 return ieee754dp_div(ieee754dp_one(0), d);
1450 }
1451
fpemu_dp_rsqrt(union ieee754dp d)1452 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1453 {
1454 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1455 }
1456
fpemu_sp_recip(union ieee754sp s)1457 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1458 {
1459 return ieee754sp_div(ieee754sp_one(0), s);
1460 }
1461
fpemu_sp_rsqrt(union ieee754sp s)1462 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1463 {
1464 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1465 }
1466
1467 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1468 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1469 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1470 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1471 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1472 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1473 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1474 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1475
fpux_emu(struct pt_regs * xcp,struct mips_fpu_struct * ctx,mips_instruction ir,void * __user * fault_addr)1476 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1477 mips_instruction ir, void *__user *fault_addr)
1478 {
1479 unsigned int rcsr = 0; /* resulting csr */
1480
1481 MIPS_FPU_EMU_INC_STATS(cp1xops);
1482
1483 switch (MIPSInst_FMA_FFMT(ir)) {
1484 case s_fmt:{ /* 0 */
1485
1486 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1487 union ieee754sp fd, fr, fs, ft;
1488 u32 __user *va;
1489 u32 val;
1490
1491 switch (MIPSInst_FUNC(ir)) {
1492 case lwxc1_op:
1493 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1494 xcp->regs[MIPSInst_FT(ir)]);
1495
1496 MIPS_FPU_EMU_INC_STATS(loads);
1497 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1498 MIPS_FPU_EMU_INC_STATS(errors);
1499 *fault_addr = va;
1500 return SIGBUS;
1501 }
1502 if (__get_user(val, va)) {
1503 MIPS_FPU_EMU_INC_STATS(errors);
1504 *fault_addr = va;
1505 return SIGSEGV;
1506 }
1507 SITOREG(val, MIPSInst_FD(ir));
1508 break;
1509
1510 case swxc1_op:
1511 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1512 xcp->regs[MIPSInst_FT(ir)]);
1513
1514 MIPS_FPU_EMU_INC_STATS(stores);
1515
1516 SIFROMREG(val, MIPSInst_FS(ir));
1517 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1518 MIPS_FPU_EMU_INC_STATS(errors);
1519 *fault_addr = va;
1520 return SIGBUS;
1521 }
1522 if (put_user(val, va)) {
1523 MIPS_FPU_EMU_INC_STATS(errors);
1524 *fault_addr = va;
1525 return SIGSEGV;
1526 }
1527 break;
1528
1529 case madd_s_op:
1530 handler = fpemu_sp_madd;
1531 goto scoptop;
1532 case msub_s_op:
1533 handler = fpemu_sp_msub;
1534 goto scoptop;
1535 case nmadd_s_op:
1536 handler = fpemu_sp_nmadd;
1537 goto scoptop;
1538 case nmsub_s_op:
1539 handler = fpemu_sp_nmsub;
1540 goto scoptop;
1541
1542 scoptop:
1543 SPFROMREG(fr, MIPSInst_FR(ir));
1544 SPFROMREG(fs, MIPSInst_FS(ir));
1545 SPFROMREG(ft, MIPSInst_FT(ir));
1546 fd = (*handler) (fr, fs, ft);
1547 SPTOREG(fd, MIPSInst_FD(ir));
1548
1549 copcsr:
1550 if (ieee754_cxtest(IEEE754_INEXACT)) {
1551 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1552 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1553 }
1554 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1555 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1556 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1557 }
1558 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1559 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1560 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1561 }
1562 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1563 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1564 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1565 }
1566
1567 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1568 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1569 /*printk ("SIGFPE: FPU csr = %08x\n",
1570 ctx->fcr31); */
1571 return SIGFPE;
1572 }
1573
1574 break;
1575
1576 default:
1577 return SIGILL;
1578 }
1579 break;
1580 }
1581
1582 case d_fmt:{ /* 1 */
1583 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1584 union ieee754dp fd, fr, fs, ft;
1585 u64 __user *va;
1586 u64 val;
1587
1588 switch (MIPSInst_FUNC(ir)) {
1589 case ldxc1_op:
1590 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1591 xcp->regs[MIPSInst_FT(ir)]);
1592
1593 MIPS_FPU_EMU_INC_STATS(loads);
1594 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1595 MIPS_FPU_EMU_INC_STATS(errors);
1596 *fault_addr = va;
1597 return SIGBUS;
1598 }
1599 if (__get_user(val, va)) {
1600 MIPS_FPU_EMU_INC_STATS(errors);
1601 *fault_addr = va;
1602 return SIGSEGV;
1603 }
1604 DITOREG(val, MIPSInst_FD(ir));
1605 break;
1606
1607 case sdxc1_op:
1608 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1609 xcp->regs[MIPSInst_FT(ir)]);
1610
1611 MIPS_FPU_EMU_INC_STATS(stores);
1612 DIFROMREG(val, MIPSInst_FS(ir));
1613 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1614 MIPS_FPU_EMU_INC_STATS(errors);
1615 *fault_addr = va;
1616 return SIGBUS;
1617 }
1618 if (__put_user(val, va)) {
1619 MIPS_FPU_EMU_INC_STATS(errors);
1620 *fault_addr = va;
1621 return SIGSEGV;
1622 }
1623 break;
1624
1625 case madd_d_op:
1626 handler = fpemu_dp_madd;
1627 goto dcoptop;
1628 case msub_d_op:
1629 handler = fpemu_dp_msub;
1630 goto dcoptop;
1631 case nmadd_d_op:
1632 handler = fpemu_dp_nmadd;
1633 goto dcoptop;
1634 case nmsub_d_op:
1635 handler = fpemu_dp_nmsub;
1636 goto dcoptop;
1637
1638 dcoptop:
1639 DPFROMREG(fr, MIPSInst_FR(ir));
1640 DPFROMREG(fs, MIPSInst_FS(ir));
1641 DPFROMREG(ft, MIPSInst_FT(ir));
1642 fd = (*handler) (fr, fs, ft);
1643 DPTOREG(fd, MIPSInst_FD(ir));
1644 goto copcsr;
1645
1646 default:
1647 return SIGILL;
1648 }
1649 break;
1650 }
1651
1652 case 0x3:
1653 if (MIPSInst_FUNC(ir) != pfetch_op)
1654 return SIGILL;
1655
1656 /* ignore prefx operation */
1657 break;
1658
1659 default:
1660 return SIGILL;
1661 }
1662
1663 return 0;
1664 }
1665
1666
1667
1668 /*
1669 * Emulate a single COP1 arithmetic instruction.
1670 */
fpu_emu(struct pt_regs * xcp,struct mips_fpu_struct * ctx,mips_instruction ir)1671 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1672 mips_instruction ir)
1673 {
1674 int rfmt; /* resulting format */
1675 unsigned int rcsr = 0; /* resulting csr */
1676 unsigned int oldrm;
1677 unsigned int cbit;
1678 unsigned int cond;
1679 union {
1680 union ieee754dp d;
1681 union ieee754sp s;
1682 int w;
1683 s64 l;
1684 } rv; /* resulting value */
1685 u64 bits;
1686
1687 MIPS_FPU_EMU_INC_STATS(cp1ops);
1688 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1689 case s_fmt: { /* 0 */
1690 union {
1691 union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1692 union ieee754sp(*u) (union ieee754sp);
1693 } handler;
1694 union ieee754sp fd, fs, ft;
1695
1696 switch (MIPSInst_FUNC(ir)) {
1697 /* binary ops */
1698 case fadd_op:
1699 MIPS_FPU_EMU_INC_STATS(add_s);
1700 handler.b = ieee754sp_add;
1701 goto scopbop;
1702 case fsub_op:
1703 MIPS_FPU_EMU_INC_STATS(sub_s);
1704 handler.b = ieee754sp_sub;
1705 goto scopbop;
1706 case fmul_op:
1707 MIPS_FPU_EMU_INC_STATS(mul_s);
1708 handler.b = ieee754sp_mul;
1709 goto scopbop;
1710 case fdiv_op:
1711 MIPS_FPU_EMU_INC_STATS(div_s);
1712 handler.b = ieee754sp_div;
1713 goto scopbop;
1714
1715 /* unary ops */
1716 case fsqrt_op:
1717 if (!cpu_has_mips_2_3_4_5_r)
1718 return SIGILL;
1719
1720 MIPS_FPU_EMU_INC_STATS(sqrt_s);
1721 handler.u = ieee754sp_sqrt;
1722 goto scopuop;
1723
1724 /*
1725 * Note that on some MIPS IV implementations such as the
1726 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1727 * achieve full IEEE-754 accuracy - however this emulator does.
1728 */
1729 case frsqrt_op:
1730 if (!cpu_has_mips_4_5_64_r2_r6)
1731 return SIGILL;
1732
1733 MIPS_FPU_EMU_INC_STATS(rsqrt_s);
1734 handler.u = fpemu_sp_rsqrt;
1735 goto scopuop;
1736
1737 case frecip_op:
1738 if (!cpu_has_mips_4_5_64_r2_r6)
1739 return SIGILL;
1740
1741 MIPS_FPU_EMU_INC_STATS(recip_s);
1742 handler.u = fpemu_sp_recip;
1743 goto scopuop;
1744
1745 case fmovc_op:
1746 if (!cpu_has_mips_4_5_r)
1747 return SIGILL;
1748
1749 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1750 if (((ctx->fcr31 & cond) != 0) !=
1751 ((MIPSInst_FT(ir) & 1) != 0))
1752 return 0;
1753 SPFROMREG(rv.s, MIPSInst_FS(ir));
1754 break;
1755
1756 case fmovz_op:
1757 if (!cpu_has_mips_4_5_r)
1758 return SIGILL;
1759
1760 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1761 return 0;
1762 SPFROMREG(rv.s, MIPSInst_FS(ir));
1763 break;
1764
1765 case fmovn_op:
1766 if (!cpu_has_mips_4_5_r)
1767 return SIGILL;
1768
1769 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1770 return 0;
1771 SPFROMREG(rv.s, MIPSInst_FS(ir));
1772 break;
1773
1774 case fseleqz_op:
1775 if (!cpu_has_mips_r6)
1776 return SIGILL;
1777
1778 MIPS_FPU_EMU_INC_STATS(seleqz_s);
1779 SPFROMREG(rv.s, MIPSInst_FT(ir));
1780 if (rv.w & 0x1)
1781 rv.w = 0;
1782 else
1783 SPFROMREG(rv.s, MIPSInst_FS(ir));
1784 break;
1785
1786 case fselnez_op:
1787 if (!cpu_has_mips_r6)
1788 return SIGILL;
1789
1790 MIPS_FPU_EMU_INC_STATS(selnez_s);
1791 SPFROMREG(rv.s, MIPSInst_FT(ir));
1792 if (rv.w & 0x1)
1793 SPFROMREG(rv.s, MIPSInst_FS(ir));
1794 else
1795 rv.w = 0;
1796 break;
1797
1798 case fmaddf_op: {
1799 union ieee754sp ft, fs, fd;
1800
1801 if (!cpu_has_mips_r6)
1802 return SIGILL;
1803
1804 MIPS_FPU_EMU_INC_STATS(maddf_s);
1805 SPFROMREG(ft, MIPSInst_FT(ir));
1806 SPFROMREG(fs, MIPSInst_FS(ir));
1807 SPFROMREG(fd, MIPSInst_FD(ir));
1808 rv.s = ieee754sp_maddf(fd, fs, ft);
1809 goto copcsr;
1810 }
1811
1812 case fmsubf_op: {
1813 union ieee754sp ft, fs, fd;
1814
1815 if (!cpu_has_mips_r6)
1816 return SIGILL;
1817
1818 MIPS_FPU_EMU_INC_STATS(msubf_s);
1819 SPFROMREG(ft, MIPSInst_FT(ir));
1820 SPFROMREG(fs, MIPSInst_FS(ir));
1821 SPFROMREG(fd, MIPSInst_FD(ir));
1822 rv.s = ieee754sp_msubf(fd, fs, ft);
1823 goto copcsr;
1824 }
1825
1826 case frint_op: {
1827 union ieee754sp fs;
1828
1829 if (!cpu_has_mips_r6)
1830 return SIGILL;
1831
1832 MIPS_FPU_EMU_INC_STATS(rint_s);
1833 SPFROMREG(fs, MIPSInst_FS(ir));
1834 rv.s = ieee754sp_rint(fs);
1835 goto copcsr;
1836 }
1837
1838 case fclass_op: {
1839 union ieee754sp fs;
1840
1841 if (!cpu_has_mips_r6)
1842 return SIGILL;
1843
1844 MIPS_FPU_EMU_INC_STATS(class_s);
1845 SPFROMREG(fs, MIPSInst_FS(ir));
1846 rv.w = ieee754sp_2008class(fs);
1847 rfmt = w_fmt;
1848 goto copcsr;
1849 }
1850
1851 case fmin_op: {
1852 union ieee754sp fs, ft;
1853
1854 if (!cpu_has_mips_r6)
1855 return SIGILL;
1856
1857 MIPS_FPU_EMU_INC_STATS(min_s);
1858 SPFROMREG(ft, MIPSInst_FT(ir));
1859 SPFROMREG(fs, MIPSInst_FS(ir));
1860 rv.s = ieee754sp_fmin(fs, ft);
1861 goto copcsr;
1862 }
1863
1864 case fmina_op: {
1865 union ieee754sp fs, ft;
1866
1867 if (!cpu_has_mips_r6)
1868 return SIGILL;
1869
1870 MIPS_FPU_EMU_INC_STATS(mina_s);
1871 SPFROMREG(ft, MIPSInst_FT(ir));
1872 SPFROMREG(fs, MIPSInst_FS(ir));
1873 rv.s = ieee754sp_fmina(fs, ft);
1874 goto copcsr;
1875 }
1876
1877 case fmax_op: {
1878 union ieee754sp fs, ft;
1879
1880 if (!cpu_has_mips_r6)
1881 return SIGILL;
1882
1883 MIPS_FPU_EMU_INC_STATS(max_s);
1884 SPFROMREG(ft, MIPSInst_FT(ir));
1885 SPFROMREG(fs, MIPSInst_FS(ir));
1886 rv.s = ieee754sp_fmax(fs, ft);
1887 goto copcsr;
1888 }
1889
1890 case fmaxa_op: {
1891 union ieee754sp fs, ft;
1892
1893 if (!cpu_has_mips_r6)
1894 return SIGILL;
1895
1896 MIPS_FPU_EMU_INC_STATS(maxa_s);
1897 SPFROMREG(ft, MIPSInst_FT(ir));
1898 SPFROMREG(fs, MIPSInst_FS(ir));
1899 rv.s = ieee754sp_fmaxa(fs, ft);
1900 goto copcsr;
1901 }
1902
1903 case fabs_op:
1904 MIPS_FPU_EMU_INC_STATS(abs_s);
1905 handler.u = ieee754sp_abs;
1906 goto scopuop;
1907
1908 case fneg_op:
1909 MIPS_FPU_EMU_INC_STATS(neg_s);
1910 handler.u = ieee754sp_neg;
1911 goto scopuop;
1912
1913 case fmov_op:
1914 /* an easy one */
1915 MIPS_FPU_EMU_INC_STATS(mov_s);
1916 SPFROMREG(rv.s, MIPSInst_FS(ir));
1917 goto copcsr;
1918
1919 /* binary op on handler */
1920 scopbop:
1921 SPFROMREG(fs, MIPSInst_FS(ir));
1922 SPFROMREG(ft, MIPSInst_FT(ir));
1923
1924 rv.s = (*handler.b) (fs, ft);
1925 goto copcsr;
1926 scopuop:
1927 SPFROMREG(fs, MIPSInst_FS(ir));
1928 rv.s = (*handler.u) (fs);
1929 goto copcsr;
1930 copcsr:
1931 if (ieee754_cxtest(IEEE754_INEXACT)) {
1932 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1933 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1934 }
1935 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1936 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1937 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1938 }
1939 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1940 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1941 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1942 }
1943 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1944 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1945 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1946 }
1947 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1948 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1949 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1950 }
1951 break;
1952
1953 /* unary conv ops */
1954 case fcvts_op:
1955 return SIGILL; /* not defined */
1956
1957 case fcvtd_op:
1958 MIPS_FPU_EMU_INC_STATS(cvt_d_s);
1959 SPFROMREG(fs, MIPSInst_FS(ir));
1960 rv.d = ieee754dp_fsp(fs);
1961 rfmt = d_fmt;
1962 goto copcsr;
1963
1964 case fcvtw_op:
1965 MIPS_FPU_EMU_INC_STATS(cvt_w_s);
1966 SPFROMREG(fs, MIPSInst_FS(ir));
1967 rv.w = ieee754sp_tint(fs);
1968 rfmt = w_fmt;
1969 goto copcsr;
1970
1971 case fround_op:
1972 case ftrunc_op:
1973 case fceil_op:
1974 case ffloor_op:
1975 if (!cpu_has_mips_2_3_4_5_r)
1976 return SIGILL;
1977
1978 if (MIPSInst_FUNC(ir) == fceil_op)
1979 MIPS_FPU_EMU_INC_STATS(ceil_w_s);
1980 if (MIPSInst_FUNC(ir) == ffloor_op)
1981 MIPS_FPU_EMU_INC_STATS(floor_w_s);
1982 if (MIPSInst_FUNC(ir) == fround_op)
1983 MIPS_FPU_EMU_INC_STATS(round_w_s);
1984 if (MIPSInst_FUNC(ir) == ftrunc_op)
1985 MIPS_FPU_EMU_INC_STATS(trunc_w_s);
1986
1987 oldrm = ieee754_csr.rm;
1988 SPFROMREG(fs, MIPSInst_FS(ir));
1989 ieee754_csr.rm = MIPSInst_FUNC(ir);
1990 rv.w = ieee754sp_tint(fs);
1991 ieee754_csr.rm = oldrm;
1992 rfmt = w_fmt;
1993 goto copcsr;
1994
1995 case fsel_op:
1996 if (!cpu_has_mips_r6)
1997 return SIGILL;
1998
1999 MIPS_FPU_EMU_INC_STATS(sel_s);
2000 SPFROMREG(fd, MIPSInst_FD(ir));
2001 if (fd.bits & 0x1)
2002 SPFROMREG(rv.s, MIPSInst_FT(ir));
2003 else
2004 SPFROMREG(rv.s, MIPSInst_FS(ir));
2005 break;
2006
2007 case fcvtl_op:
2008 if (!cpu_has_mips_3_4_5_64_r2_r6)
2009 return SIGILL;
2010
2011 MIPS_FPU_EMU_INC_STATS(cvt_l_s);
2012 SPFROMREG(fs, MIPSInst_FS(ir));
2013 rv.l = ieee754sp_tlong(fs);
2014 rfmt = l_fmt;
2015 goto copcsr;
2016
2017 case froundl_op:
2018 case ftruncl_op:
2019 case fceill_op:
2020 case ffloorl_op:
2021 if (!cpu_has_mips_3_4_5_64_r2_r6)
2022 return SIGILL;
2023
2024 if (MIPSInst_FUNC(ir) == fceill_op)
2025 MIPS_FPU_EMU_INC_STATS(ceil_l_s);
2026 if (MIPSInst_FUNC(ir) == ffloorl_op)
2027 MIPS_FPU_EMU_INC_STATS(floor_l_s);
2028 if (MIPSInst_FUNC(ir) == froundl_op)
2029 MIPS_FPU_EMU_INC_STATS(round_l_s);
2030 if (MIPSInst_FUNC(ir) == ftruncl_op)
2031 MIPS_FPU_EMU_INC_STATS(trunc_l_s);
2032
2033 oldrm = ieee754_csr.rm;
2034 SPFROMREG(fs, MIPSInst_FS(ir));
2035 ieee754_csr.rm = MIPSInst_FUNC(ir);
2036 rv.l = ieee754sp_tlong(fs);
2037 ieee754_csr.rm = oldrm;
2038 rfmt = l_fmt;
2039 goto copcsr;
2040
2041 default:
2042 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
2043 unsigned int cmpop;
2044 union ieee754sp fs, ft;
2045
2046 cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2047 SPFROMREG(fs, MIPSInst_FS(ir));
2048 SPFROMREG(ft, MIPSInst_FT(ir));
2049 rv.w = ieee754sp_cmp(fs, ft,
2050 cmptab[cmpop & 0x7], cmpop & 0x8);
2051 rfmt = -1;
2052 if ((cmpop & 0x8) && ieee754_cxtest
2053 (IEEE754_INVALID_OPERATION))
2054 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2055 else
2056 goto copcsr;
2057
2058 } else
2059 return SIGILL;
2060 break;
2061 }
2062 break;
2063 }
2064
2065 case d_fmt: {
2066 union ieee754dp fd, fs, ft;
2067 union {
2068 union ieee754dp(*b) (union ieee754dp, union ieee754dp);
2069 union ieee754dp(*u) (union ieee754dp);
2070 } handler;
2071
2072 switch (MIPSInst_FUNC(ir)) {
2073 /* binary ops */
2074 case fadd_op:
2075 MIPS_FPU_EMU_INC_STATS(add_d);
2076 handler.b = ieee754dp_add;
2077 goto dcopbop;
2078 case fsub_op:
2079 MIPS_FPU_EMU_INC_STATS(sub_d);
2080 handler.b = ieee754dp_sub;
2081 goto dcopbop;
2082 case fmul_op:
2083 MIPS_FPU_EMU_INC_STATS(mul_d);
2084 handler.b = ieee754dp_mul;
2085 goto dcopbop;
2086 case fdiv_op:
2087 MIPS_FPU_EMU_INC_STATS(div_d);
2088 handler.b = ieee754dp_div;
2089 goto dcopbop;
2090
2091 /* unary ops */
2092 case fsqrt_op:
2093 if (!cpu_has_mips_2_3_4_5_r)
2094 return SIGILL;
2095
2096 MIPS_FPU_EMU_INC_STATS(sqrt_d);
2097 handler.u = ieee754dp_sqrt;
2098 goto dcopuop;
2099 /*
2100 * Note that on some MIPS IV implementations such as the
2101 * R5000 and R8000 the FSQRT and FRECIP instructions do not
2102 * achieve full IEEE-754 accuracy - however this emulator does.
2103 */
2104 case frsqrt_op:
2105 if (!cpu_has_mips_4_5_64_r2_r6)
2106 return SIGILL;
2107
2108 MIPS_FPU_EMU_INC_STATS(rsqrt_d);
2109 handler.u = fpemu_dp_rsqrt;
2110 goto dcopuop;
2111 case frecip_op:
2112 if (!cpu_has_mips_4_5_64_r2_r6)
2113 return SIGILL;
2114
2115 MIPS_FPU_EMU_INC_STATS(recip_d);
2116 handler.u = fpemu_dp_recip;
2117 goto dcopuop;
2118 case fmovc_op:
2119 if (!cpu_has_mips_4_5_r)
2120 return SIGILL;
2121
2122 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
2123 if (((ctx->fcr31 & cond) != 0) !=
2124 ((MIPSInst_FT(ir) & 1) != 0))
2125 return 0;
2126 DPFROMREG(rv.d, MIPSInst_FS(ir));
2127 break;
2128 case fmovz_op:
2129 if (!cpu_has_mips_4_5_r)
2130 return SIGILL;
2131
2132 if (xcp->regs[MIPSInst_FT(ir)] != 0)
2133 return 0;
2134 DPFROMREG(rv.d, MIPSInst_FS(ir));
2135 break;
2136 case fmovn_op:
2137 if (!cpu_has_mips_4_5_r)
2138 return SIGILL;
2139
2140 if (xcp->regs[MIPSInst_FT(ir)] == 0)
2141 return 0;
2142 DPFROMREG(rv.d, MIPSInst_FS(ir));
2143 break;
2144
2145 case fseleqz_op:
2146 if (!cpu_has_mips_r6)
2147 return SIGILL;
2148
2149 MIPS_FPU_EMU_INC_STATS(seleqz_d);
2150 DPFROMREG(rv.d, MIPSInst_FT(ir));
2151 if (rv.l & 0x1)
2152 rv.l = 0;
2153 else
2154 DPFROMREG(rv.d, MIPSInst_FS(ir));
2155 break;
2156
2157 case fselnez_op:
2158 if (!cpu_has_mips_r6)
2159 return SIGILL;
2160
2161 MIPS_FPU_EMU_INC_STATS(selnez_d);
2162 DPFROMREG(rv.d, MIPSInst_FT(ir));
2163 if (rv.l & 0x1)
2164 DPFROMREG(rv.d, MIPSInst_FS(ir));
2165 else
2166 rv.l = 0;
2167 break;
2168
2169 case fmaddf_op: {
2170 union ieee754dp ft, fs, fd;
2171
2172 if (!cpu_has_mips_r6)
2173 return SIGILL;
2174
2175 MIPS_FPU_EMU_INC_STATS(maddf_d);
2176 DPFROMREG(ft, MIPSInst_FT(ir));
2177 DPFROMREG(fs, MIPSInst_FS(ir));
2178 DPFROMREG(fd, MIPSInst_FD(ir));
2179 rv.d = ieee754dp_maddf(fd, fs, ft);
2180 goto copcsr;
2181 }
2182
2183 case fmsubf_op: {
2184 union ieee754dp ft, fs, fd;
2185
2186 if (!cpu_has_mips_r6)
2187 return SIGILL;
2188
2189 MIPS_FPU_EMU_INC_STATS(msubf_d);
2190 DPFROMREG(ft, MIPSInst_FT(ir));
2191 DPFROMREG(fs, MIPSInst_FS(ir));
2192 DPFROMREG(fd, MIPSInst_FD(ir));
2193 rv.d = ieee754dp_msubf(fd, fs, ft);
2194 goto copcsr;
2195 }
2196
2197 case frint_op: {
2198 union ieee754dp fs;
2199
2200 if (!cpu_has_mips_r6)
2201 return SIGILL;
2202
2203 MIPS_FPU_EMU_INC_STATS(rint_d);
2204 DPFROMREG(fs, MIPSInst_FS(ir));
2205 rv.d = ieee754dp_rint(fs);
2206 goto copcsr;
2207 }
2208
2209 case fclass_op: {
2210 union ieee754dp fs;
2211
2212 if (!cpu_has_mips_r6)
2213 return SIGILL;
2214
2215 MIPS_FPU_EMU_INC_STATS(class_d);
2216 DPFROMREG(fs, MIPSInst_FS(ir));
2217 rv.l = ieee754dp_2008class(fs);
2218 rfmt = l_fmt;
2219 goto copcsr;
2220 }
2221
2222 case fmin_op: {
2223 union ieee754dp fs, ft;
2224
2225 if (!cpu_has_mips_r6)
2226 return SIGILL;
2227
2228 MIPS_FPU_EMU_INC_STATS(min_d);
2229 DPFROMREG(ft, MIPSInst_FT(ir));
2230 DPFROMREG(fs, MIPSInst_FS(ir));
2231 rv.d = ieee754dp_fmin(fs, ft);
2232 goto copcsr;
2233 }
2234
2235 case fmina_op: {
2236 union ieee754dp fs, ft;
2237
2238 if (!cpu_has_mips_r6)
2239 return SIGILL;
2240
2241 MIPS_FPU_EMU_INC_STATS(mina_d);
2242 DPFROMREG(ft, MIPSInst_FT(ir));
2243 DPFROMREG(fs, MIPSInst_FS(ir));
2244 rv.d = ieee754dp_fmina(fs, ft);
2245 goto copcsr;
2246 }
2247
2248 case fmax_op: {
2249 union ieee754dp fs, ft;
2250
2251 if (!cpu_has_mips_r6)
2252 return SIGILL;
2253
2254 MIPS_FPU_EMU_INC_STATS(max_d);
2255 DPFROMREG(ft, MIPSInst_FT(ir));
2256 DPFROMREG(fs, MIPSInst_FS(ir));
2257 rv.d = ieee754dp_fmax(fs, ft);
2258 goto copcsr;
2259 }
2260
2261 case fmaxa_op: {
2262 union ieee754dp fs, ft;
2263
2264 if (!cpu_has_mips_r6)
2265 return SIGILL;
2266
2267 MIPS_FPU_EMU_INC_STATS(maxa_d);
2268 DPFROMREG(ft, MIPSInst_FT(ir));
2269 DPFROMREG(fs, MIPSInst_FS(ir));
2270 rv.d = ieee754dp_fmaxa(fs, ft);
2271 goto copcsr;
2272 }
2273
2274 case fabs_op:
2275 MIPS_FPU_EMU_INC_STATS(abs_d);
2276 handler.u = ieee754dp_abs;
2277 goto dcopuop;
2278
2279 case fneg_op:
2280 MIPS_FPU_EMU_INC_STATS(neg_d);
2281 handler.u = ieee754dp_neg;
2282 goto dcopuop;
2283
2284 case fmov_op:
2285 /* an easy one */
2286 MIPS_FPU_EMU_INC_STATS(mov_d);
2287 DPFROMREG(rv.d, MIPSInst_FS(ir));
2288 goto copcsr;
2289
2290 /* binary op on handler */
2291 dcopbop:
2292 DPFROMREG(fs, MIPSInst_FS(ir));
2293 DPFROMREG(ft, MIPSInst_FT(ir));
2294
2295 rv.d = (*handler.b) (fs, ft);
2296 goto copcsr;
2297 dcopuop:
2298 DPFROMREG(fs, MIPSInst_FS(ir));
2299 rv.d = (*handler.u) (fs);
2300 goto copcsr;
2301
2302 /*
2303 * unary conv ops
2304 */
2305 case fcvts_op:
2306 MIPS_FPU_EMU_INC_STATS(cvt_s_d);
2307 DPFROMREG(fs, MIPSInst_FS(ir));
2308 rv.s = ieee754sp_fdp(fs);
2309 rfmt = s_fmt;
2310 goto copcsr;
2311
2312 case fcvtd_op:
2313 return SIGILL; /* not defined */
2314
2315 case fcvtw_op:
2316 MIPS_FPU_EMU_INC_STATS(cvt_w_d);
2317 DPFROMREG(fs, MIPSInst_FS(ir));
2318 rv.w = ieee754dp_tint(fs); /* wrong */
2319 rfmt = w_fmt;
2320 goto copcsr;
2321
2322 case fround_op:
2323 case ftrunc_op:
2324 case fceil_op:
2325 case ffloor_op:
2326 if (!cpu_has_mips_2_3_4_5_r)
2327 return SIGILL;
2328
2329 if (MIPSInst_FUNC(ir) == fceil_op)
2330 MIPS_FPU_EMU_INC_STATS(ceil_w_d);
2331 if (MIPSInst_FUNC(ir) == ffloor_op)
2332 MIPS_FPU_EMU_INC_STATS(floor_w_d);
2333 if (MIPSInst_FUNC(ir) == fround_op)
2334 MIPS_FPU_EMU_INC_STATS(round_w_d);
2335 if (MIPSInst_FUNC(ir) == ftrunc_op)
2336 MIPS_FPU_EMU_INC_STATS(trunc_w_d);
2337
2338 oldrm = ieee754_csr.rm;
2339 DPFROMREG(fs, MIPSInst_FS(ir));
2340 ieee754_csr.rm = MIPSInst_FUNC(ir);
2341 rv.w = ieee754dp_tint(fs);
2342 ieee754_csr.rm = oldrm;
2343 rfmt = w_fmt;
2344 goto copcsr;
2345
2346 case fsel_op:
2347 if (!cpu_has_mips_r6)
2348 return SIGILL;
2349
2350 MIPS_FPU_EMU_INC_STATS(sel_d);
2351 DPFROMREG(fd, MIPSInst_FD(ir));
2352 if (fd.bits & 0x1)
2353 DPFROMREG(rv.d, MIPSInst_FT(ir));
2354 else
2355 DPFROMREG(rv.d, MIPSInst_FS(ir));
2356 break;
2357
2358 case fcvtl_op:
2359 if (!cpu_has_mips_3_4_5_64_r2_r6)
2360 return SIGILL;
2361
2362 MIPS_FPU_EMU_INC_STATS(cvt_l_d);
2363 DPFROMREG(fs, MIPSInst_FS(ir));
2364 rv.l = ieee754dp_tlong(fs);
2365 rfmt = l_fmt;
2366 goto copcsr;
2367
2368 case froundl_op:
2369 case ftruncl_op:
2370 case fceill_op:
2371 case ffloorl_op:
2372 if (!cpu_has_mips_3_4_5_64_r2_r6)
2373 return SIGILL;
2374
2375 if (MIPSInst_FUNC(ir) == fceill_op)
2376 MIPS_FPU_EMU_INC_STATS(ceil_l_d);
2377 if (MIPSInst_FUNC(ir) == ffloorl_op)
2378 MIPS_FPU_EMU_INC_STATS(floor_l_d);
2379 if (MIPSInst_FUNC(ir) == froundl_op)
2380 MIPS_FPU_EMU_INC_STATS(round_l_d);
2381 if (MIPSInst_FUNC(ir) == ftruncl_op)
2382 MIPS_FPU_EMU_INC_STATS(trunc_l_d);
2383
2384 oldrm = ieee754_csr.rm;
2385 DPFROMREG(fs, MIPSInst_FS(ir));
2386 ieee754_csr.rm = MIPSInst_FUNC(ir);
2387 rv.l = ieee754dp_tlong(fs);
2388 ieee754_csr.rm = oldrm;
2389 rfmt = l_fmt;
2390 goto copcsr;
2391
2392 default:
2393 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
2394 unsigned int cmpop;
2395 union ieee754dp fs, ft;
2396
2397 cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2398 DPFROMREG(fs, MIPSInst_FS(ir));
2399 DPFROMREG(ft, MIPSInst_FT(ir));
2400 rv.w = ieee754dp_cmp(fs, ft,
2401 cmptab[cmpop & 0x7], cmpop & 0x8);
2402 rfmt = -1;
2403 if ((cmpop & 0x8)
2404 &&
2405 ieee754_cxtest
2406 (IEEE754_INVALID_OPERATION))
2407 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2408 else
2409 goto copcsr;
2410
2411 }
2412 else {
2413 return SIGILL;
2414 }
2415 break;
2416 }
2417 break;
2418 }
2419
2420 case w_fmt: {
2421 union ieee754dp fs;
2422
2423 switch (MIPSInst_FUNC(ir)) {
2424 case fcvts_op:
2425 /* convert word to single precision real */
2426 MIPS_FPU_EMU_INC_STATS(cvt_s_w);
2427 SPFROMREG(fs, MIPSInst_FS(ir));
2428 rv.s = ieee754sp_fint(fs.bits);
2429 rfmt = s_fmt;
2430 goto copcsr;
2431 case fcvtd_op:
2432 /* convert word to double precision real */
2433 MIPS_FPU_EMU_INC_STATS(cvt_d_w);
2434 SPFROMREG(fs, MIPSInst_FS(ir));
2435 rv.d = ieee754dp_fint(fs.bits);
2436 rfmt = d_fmt;
2437 goto copcsr;
2438 default: {
2439 /* Emulating the new CMP.condn.fmt R6 instruction */
2440 #define CMPOP_MASK 0x7
2441 #define SIGN_BIT (0x1 << 3)
2442 #define PREDICATE_BIT (0x1 << 4)
2443
2444 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2445 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2446 union ieee754sp fs, ft;
2447
2448 /* This is an R6 only instruction */
2449 if (!cpu_has_mips_r6 ||
2450 (MIPSInst_FUNC(ir) & 0x20))
2451 return SIGILL;
2452
2453 if (!sig) {
2454 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2455 switch (cmpop) {
2456 case 0:
2457 MIPS_FPU_EMU_INC_STATS(cmp_af_s);
2458 break;
2459 case 1:
2460 MIPS_FPU_EMU_INC_STATS(cmp_un_s);
2461 break;
2462 case 2:
2463 MIPS_FPU_EMU_INC_STATS(cmp_eq_s);
2464 break;
2465 case 3:
2466 MIPS_FPU_EMU_INC_STATS(cmp_ueq_s);
2467 break;
2468 case 4:
2469 MIPS_FPU_EMU_INC_STATS(cmp_lt_s);
2470 break;
2471 case 5:
2472 MIPS_FPU_EMU_INC_STATS(cmp_ult_s);
2473 break;
2474 case 6:
2475 MIPS_FPU_EMU_INC_STATS(cmp_le_s);
2476 break;
2477 case 7:
2478 MIPS_FPU_EMU_INC_STATS(cmp_ule_s);
2479 break;
2480 }
2481 } else {
2482 switch (cmpop) {
2483 case 1:
2484 MIPS_FPU_EMU_INC_STATS(cmp_or_s);
2485 break;
2486 case 2:
2487 MIPS_FPU_EMU_INC_STATS(cmp_une_s);
2488 break;
2489 case 3:
2490 MIPS_FPU_EMU_INC_STATS(cmp_ne_s);
2491 break;
2492 }
2493 }
2494 } else {
2495 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2496 switch (cmpop) {
2497 case 0:
2498 MIPS_FPU_EMU_INC_STATS(cmp_saf_s);
2499 break;
2500 case 1:
2501 MIPS_FPU_EMU_INC_STATS(cmp_sun_s);
2502 break;
2503 case 2:
2504 MIPS_FPU_EMU_INC_STATS(cmp_seq_s);
2505 break;
2506 case 3:
2507 MIPS_FPU_EMU_INC_STATS(cmp_sueq_s);
2508 break;
2509 case 4:
2510 MIPS_FPU_EMU_INC_STATS(cmp_slt_s);
2511 break;
2512 case 5:
2513 MIPS_FPU_EMU_INC_STATS(cmp_sult_s);
2514 break;
2515 case 6:
2516 MIPS_FPU_EMU_INC_STATS(cmp_sle_s);
2517 break;
2518 case 7:
2519 MIPS_FPU_EMU_INC_STATS(cmp_sule_s);
2520 break;
2521 }
2522 } else {
2523 switch (cmpop) {
2524 case 1:
2525 MIPS_FPU_EMU_INC_STATS(cmp_sor_s);
2526 break;
2527 case 2:
2528 MIPS_FPU_EMU_INC_STATS(cmp_sune_s);
2529 break;
2530 case 3:
2531 MIPS_FPU_EMU_INC_STATS(cmp_sne_s);
2532 break;
2533 }
2534 }
2535 }
2536
2537 /* fmt is w_fmt for single precision so fix it */
2538 rfmt = s_fmt;
2539 /* default to false */
2540 rv.w = 0;
2541
2542 /* CMP.condn.S */
2543 SPFROMREG(fs, MIPSInst_FS(ir));
2544 SPFROMREG(ft, MIPSInst_FT(ir));
2545
2546 /* positive predicates */
2547 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2548 if (ieee754sp_cmp(fs, ft, cmptab[cmpop],
2549 sig))
2550 rv.w = -1; /* true, all 1s */
2551 if ((sig) &&
2552 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2553 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2554 else
2555 goto copcsr;
2556 } else {
2557 /* negative predicates */
2558 switch (cmpop) {
2559 case 1:
2560 case 2:
2561 case 3:
2562 if (ieee754sp_cmp(fs, ft,
2563 negative_cmptab[cmpop],
2564 sig))
2565 rv.w = -1; /* true, all 1s */
2566 if (sig &&
2567 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2568 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2569 else
2570 goto copcsr;
2571 break;
2572 default:
2573 /* Reserved R6 ops */
2574 return SIGILL;
2575 }
2576 }
2577 break;
2578 }
2579 }
2580 break;
2581 }
2582
2583 case l_fmt:
2584
2585 if (!cpu_has_mips_3_4_5_64_r2_r6)
2586 return SIGILL;
2587
2588 DIFROMREG(bits, MIPSInst_FS(ir));
2589
2590 switch (MIPSInst_FUNC(ir)) {
2591 case fcvts_op:
2592 /* convert long to single precision real */
2593 MIPS_FPU_EMU_INC_STATS(cvt_s_l);
2594 rv.s = ieee754sp_flong(bits);
2595 rfmt = s_fmt;
2596 goto copcsr;
2597 case fcvtd_op:
2598 /* convert long to double precision real */
2599 MIPS_FPU_EMU_INC_STATS(cvt_d_l);
2600 rv.d = ieee754dp_flong(bits);
2601 rfmt = d_fmt;
2602 goto copcsr;
2603 default: {
2604 /* Emulating the new CMP.condn.fmt R6 instruction */
2605 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2606 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2607 union ieee754dp fs, ft;
2608
2609 if (!cpu_has_mips_r6 ||
2610 (MIPSInst_FUNC(ir) & 0x20))
2611 return SIGILL;
2612
2613 if (!sig) {
2614 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2615 switch (cmpop) {
2616 case 0:
2617 MIPS_FPU_EMU_INC_STATS(cmp_af_d);
2618 break;
2619 case 1:
2620 MIPS_FPU_EMU_INC_STATS(cmp_un_d);
2621 break;
2622 case 2:
2623 MIPS_FPU_EMU_INC_STATS(cmp_eq_d);
2624 break;
2625 case 3:
2626 MIPS_FPU_EMU_INC_STATS(cmp_ueq_d);
2627 break;
2628 case 4:
2629 MIPS_FPU_EMU_INC_STATS(cmp_lt_d);
2630 break;
2631 case 5:
2632 MIPS_FPU_EMU_INC_STATS(cmp_ult_d);
2633 break;
2634 case 6:
2635 MIPS_FPU_EMU_INC_STATS(cmp_le_d);
2636 break;
2637 case 7:
2638 MIPS_FPU_EMU_INC_STATS(cmp_ule_d);
2639 break;
2640 }
2641 } else {
2642 switch (cmpop) {
2643 case 1:
2644 MIPS_FPU_EMU_INC_STATS(cmp_or_d);
2645 break;
2646 case 2:
2647 MIPS_FPU_EMU_INC_STATS(cmp_une_d);
2648 break;
2649 case 3:
2650 MIPS_FPU_EMU_INC_STATS(cmp_ne_d);
2651 break;
2652 }
2653 }
2654 } else {
2655 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2656 switch (cmpop) {
2657 case 0:
2658 MIPS_FPU_EMU_INC_STATS(cmp_saf_d);
2659 break;
2660 case 1:
2661 MIPS_FPU_EMU_INC_STATS(cmp_sun_d);
2662 break;
2663 case 2:
2664 MIPS_FPU_EMU_INC_STATS(cmp_seq_d);
2665 break;
2666 case 3:
2667 MIPS_FPU_EMU_INC_STATS(cmp_sueq_d);
2668 break;
2669 case 4:
2670 MIPS_FPU_EMU_INC_STATS(cmp_slt_d);
2671 break;
2672 case 5:
2673 MIPS_FPU_EMU_INC_STATS(cmp_sult_d);
2674 break;
2675 case 6:
2676 MIPS_FPU_EMU_INC_STATS(cmp_sle_d);
2677 break;
2678 case 7:
2679 MIPS_FPU_EMU_INC_STATS(cmp_sule_d);
2680 break;
2681 }
2682 } else {
2683 switch (cmpop) {
2684 case 1:
2685 MIPS_FPU_EMU_INC_STATS(cmp_sor_d);
2686 break;
2687 case 2:
2688 MIPS_FPU_EMU_INC_STATS(cmp_sune_d);
2689 break;
2690 case 3:
2691 MIPS_FPU_EMU_INC_STATS(cmp_sne_d);
2692 break;
2693 }
2694 }
2695 }
2696
2697 /* fmt is l_fmt for double precision so fix it */
2698 rfmt = d_fmt;
2699 /* default to false */
2700 rv.l = 0;
2701
2702 /* CMP.condn.D */
2703 DPFROMREG(fs, MIPSInst_FS(ir));
2704 DPFROMREG(ft, MIPSInst_FT(ir));
2705
2706 /* positive predicates */
2707 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2708 if (ieee754dp_cmp(fs, ft,
2709 cmptab[cmpop], sig))
2710 rv.l = -1LL; /* true, all 1s */
2711 if (sig &&
2712 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2713 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2714 else
2715 goto copcsr;
2716 } else {
2717 /* negative predicates */
2718 switch (cmpop) {
2719 case 1:
2720 case 2:
2721 case 3:
2722 if (ieee754dp_cmp(fs, ft,
2723 negative_cmptab[cmpop],
2724 sig))
2725 rv.l = -1LL; /* true, all 1s */
2726 if (sig &&
2727 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2728 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2729 else
2730 goto copcsr;
2731 break;
2732 default:
2733 /* Reserved R6 ops */
2734 return SIGILL;
2735 }
2736 }
2737 break;
2738 }
2739 }
2740 break;
2741
2742 default:
2743 return SIGILL;
2744 }
2745
2746 /*
2747 * Update the fpu CSR register for this operation.
2748 * If an exception is required, generate a tidy SIGFPE exception,
2749 * without updating the result register.
2750 * Note: cause exception bits do not accumulate, they are rewritten
2751 * for each op; only the flag/sticky bits accumulate.
2752 */
2753 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
2754 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
2755 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
2756 return SIGFPE;
2757 }
2758
2759 /*
2760 * Now we can safely write the result back to the register file.
2761 */
2762 switch (rfmt) {
2763 case -1:
2764
2765 if (cpu_has_mips_4_5_r)
2766 cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
2767 else
2768 cbit = FPU_CSR_COND;
2769 if (rv.w)
2770 ctx->fcr31 |= cbit;
2771 else
2772 ctx->fcr31 &= ~cbit;
2773 break;
2774
2775 case d_fmt:
2776 DPTOREG(rv.d, MIPSInst_FD(ir));
2777 break;
2778 case s_fmt:
2779 SPTOREG(rv.s, MIPSInst_FD(ir));
2780 break;
2781 case w_fmt:
2782 SITOREG(rv.w, MIPSInst_FD(ir));
2783 break;
2784 case l_fmt:
2785 if (!cpu_has_mips_3_4_5_64_r2_r6)
2786 return SIGILL;
2787
2788 DITOREG(rv.l, MIPSInst_FD(ir));
2789 break;
2790 default:
2791 return SIGILL;
2792 }
2793
2794 return 0;
2795 }
2796
2797 /*
2798 * Emulate FPU instructions.
2799 *
2800 * If we use FPU hardware, then we have been typically called to handle
2801 * an unimplemented operation, such as where an operand is a NaN or
2802 * denormalized. In that case exit the emulation loop after a single
2803 * iteration so as to let hardware execute any subsequent instructions.
2804 *
2805 * If we have no FPU hardware or it has been disabled, then continue
2806 * emulating floating-point instructions until one of these conditions
2807 * has occurred:
2808 *
2809 * - a non-FPU instruction has been encountered,
2810 *
2811 * - an attempt to emulate has ended with a signal,
2812 *
2813 * - the ISA mode has been switched.
2814 *
2815 * We need to terminate the emulation loop if we got switched to the
2816 * MIPS16 mode, whether supported or not, so that we do not attempt
2817 * to emulate a MIPS16 instruction as a regular MIPS FPU instruction.
2818 * Similarly if we got switched to the microMIPS mode and only the
2819 * regular MIPS mode is supported, so that we do not attempt to emulate
2820 * a microMIPS instruction as a regular MIPS FPU instruction. Or if
2821 * we got switched to the regular MIPS mode and only the microMIPS mode
2822 * is supported, so that we do not attempt to emulate a regular MIPS
2823 * instruction that should cause an Address Error exception instead.
2824 * For simplicity we always terminate upon an ISA mode switch.
2825 */
fpu_emulator_cop1Handler(struct pt_regs * xcp,struct mips_fpu_struct * ctx,int has_fpu,void * __user * fault_addr)2826 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
2827 int has_fpu, void *__user *fault_addr)
2828 {
2829 unsigned long oldepc, prevepc;
2830 struct mm_decoded_insn dec_insn;
2831 u16 instr[4];
2832 u16 *instr_ptr;
2833 int sig = 0;
2834
2835 oldepc = xcp->cp0_epc;
2836 do {
2837 prevepc = xcp->cp0_epc;
2838
2839 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2840 /*
2841 * Get next 2 microMIPS instructions and convert them
2842 * into 32-bit instructions.
2843 */
2844 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2845 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2846 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2847 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2848 MIPS_FPU_EMU_INC_STATS(errors);
2849 return SIGBUS;
2850 }
2851 instr_ptr = instr;
2852
2853 /* Get first instruction. */
2854 if (mm_insn_16bit(*instr_ptr)) {
2855 /* Duplicate the half-word. */
2856 dec_insn.insn = (*instr_ptr << 16) |
2857 (*instr_ptr);
2858 /* 16-bit instruction. */
2859 dec_insn.pc_inc = 2;
2860 instr_ptr += 1;
2861 } else {
2862 dec_insn.insn = (*instr_ptr << 16) |
2863 *(instr_ptr+1);
2864 /* 32-bit instruction. */
2865 dec_insn.pc_inc = 4;
2866 instr_ptr += 2;
2867 }
2868 /* Get second instruction. */
2869 if (mm_insn_16bit(*instr_ptr)) {
2870 /* Duplicate the half-word. */
2871 dec_insn.next_insn = (*instr_ptr << 16) |
2872 (*instr_ptr);
2873 /* 16-bit instruction. */
2874 dec_insn.next_pc_inc = 2;
2875 } else {
2876 dec_insn.next_insn = (*instr_ptr << 16) |
2877 *(instr_ptr+1);
2878 /* 32-bit instruction. */
2879 dec_insn.next_pc_inc = 4;
2880 }
2881 dec_insn.micro_mips_mode = 1;
2882 } else {
2883 if ((get_user(dec_insn.insn,
2884 (mips_instruction __user *) xcp->cp0_epc)) ||
2885 (get_user(dec_insn.next_insn,
2886 (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2887 MIPS_FPU_EMU_INC_STATS(errors);
2888 return SIGBUS;
2889 }
2890 dec_insn.pc_inc = 4;
2891 dec_insn.next_pc_inc = 4;
2892 dec_insn.micro_mips_mode = 0;
2893 }
2894
2895 if ((dec_insn.insn == 0) ||
2896 ((dec_insn.pc_inc == 2) &&
2897 ((dec_insn.insn & 0xffff) == MM_NOP16)))
2898 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
2899 else {
2900 /*
2901 * The 'ieee754_csr' is an alias of ctx->fcr31.
2902 * No need to copy ctx->fcr31 to ieee754_csr.
2903 */
2904 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2905 }
2906
2907 if (has_fpu)
2908 break;
2909 if (sig)
2910 break;
2911 /*
2912 * We have to check for the ISA bit explicitly here,
2913 * because `get_isa16_mode' may return 0 if support
2914 * for code compression has been globally disabled,
2915 * or otherwise we may produce the wrong signal or
2916 * even proceed successfully where we must not.
2917 */
2918 if ((xcp->cp0_epc ^ prevepc) & 0x1)
2919 break;
2920
2921 cond_resched();
2922 } while (xcp->cp0_epc > prevepc);
2923
2924 /* SIGILL indicates a non-fpu instruction */
2925 if (sig == SIGILL && xcp->cp0_epc != oldepc)
2926 /* but if EPC has advanced, then ignore it */
2927 sig = 0;
2928
2929 return sig;
2930 }
2931