| /arch/x86/kvm/ |
| D | pmu.c | 62 struct kvm_pmc *pmc = perf_event->overflow_handler_context; in kvm_perf_overflow() local
63 struct kvm_pmu *pmu = pmc_to_pmu(pmc); in kvm_perf_overflow()
65 if (!test_and_set_bit(pmc->idx, in kvm_perf_overflow()
67 __set_bit(pmc->idx, (unsigned long *)&pmu->global_status); in kvm_perf_overflow()
68 kvm_make_request(KVM_REQ_PMU, pmc->vcpu); in kvm_perf_overflow()
76 struct kvm_pmc *pmc = perf_event->overflow_handler_context; in kvm_perf_overflow_intr() local
77 struct kvm_pmu *pmu = pmc_to_pmu(pmc); in kvm_perf_overflow_intr()
79 if (!test_and_set_bit(pmc->idx, in kvm_perf_overflow_intr()
81 __set_bit(pmc->idx, (unsigned long *)&pmu->global_status); in kvm_perf_overflow_intr()
82 kvm_make_request(KVM_REQ_PMU, pmc->vcpu); in kvm_perf_overflow_intr()
[all …]
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| D | pmu.h | 8 #define pmc_to_pmu(pmc) (&(pmc)->vcpu->arch.pmu) argument
23 bool (*pmc_is_enabled)(struct kvm_pmc *pmc);
35 static inline u64 pmc_bitmask(struct kvm_pmc *pmc) in pmc_bitmask() argument
37 struct kvm_pmu *pmu = pmc_to_pmu(pmc); in pmc_bitmask()
39 return pmu->counter_bitmask[pmc->type]; in pmc_bitmask()
42 static inline u64 pmc_read_counter(struct kvm_pmc *pmc) in pmc_read_counter() argument
46 counter = pmc->counter; in pmc_read_counter()
47 if (pmc->perf_event) in pmc_read_counter()
48 counter += perf_event_read_value(pmc->perf_event, in pmc_read_counter()
51 return counter & pmc_bitmask(pmc); in pmc_read_counter()
[all …]
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| D | pmu_amd.c | 60 static bool amd_pmc_is_enabled(struct kvm_pmc *pmc) in amd_pmc_is_enabled() argument
108 struct kvm_pmc *pmc; in amd_pmu_get_msr() local
111 pmc = get_gp_pmc(pmu, msr, MSR_K7_PERFCTR0); in amd_pmu_get_msr()
112 if (pmc) { in amd_pmu_get_msr()
113 *data = pmc_read_counter(pmc); in amd_pmu_get_msr()
117 pmc = get_gp_pmc(pmu, msr, MSR_K7_EVNTSEL0); in amd_pmu_get_msr()
118 if (pmc) { in amd_pmu_get_msr()
119 *data = pmc->eventsel; in amd_pmu_get_msr()
129 struct kvm_pmc *pmc; in amd_pmu_set_msr() local
134 pmc = get_gp_pmc(pmu, msr, MSR_K7_PERFCTR0); in amd_pmu_set_msr()
[all …]
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| D | pmu_intel.c | 45 struct kvm_pmc *pmc; in reprogram_fixed_counters() local
47 pmc = get_fixed_pmc(pmu, MSR_CORE_PERF_FIXED_CTR0 + i); in reprogram_fixed_counters()
52 reprogram_fixed_counter(pmc, new_ctrl, i); in reprogram_fixed_counters()
101 static bool intel_pmc_is_enabled(struct kvm_pmc *pmc) in intel_pmc_is_enabled() argument
103 struct kvm_pmu *pmu = pmc_to_pmu(pmc); in intel_pmc_is_enabled()
105 return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl); in intel_pmc_is_enabled()
178 struct kvm_pmc *pmc; in intel_pmu_get_msr() local
194 if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) || in intel_pmu_get_msr()
195 (pmc = get_fixed_pmc(pmu, msr))) { in intel_pmu_get_msr()
196 *data = pmc_read_counter(pmc); in intel_pmu_get_msr()
[all …]
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| /arch/powerpc/perf/ |
| D | power6-pmu.c | 141 int pmc, psel, ptype; in power6_marked_instr_event() local
145 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; in power6_marked_instr_event()
147 if (pmc >= 5) in power6_marked_instr_event()
153 if (pmc == 0 || !(ptype & (1 << (pmc - 1)))) in power6_marked_instr_event()
161 bit = ptype ^ (pmc - 1); in power6_marked_instr_event()
183 unsigned int pmc, ev, b, u, s, psel; in p6_compute_mmcr() local
190 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK; in p6_compute_mmcr()
191 if (pmc) { in p6_compute_mmcr()
192 if (pmc_inuse & (1 << (pmc - 1))) in p6_compute_mmcr()
194 pmc_inuse |= 1 << (pmc - 1); in p6_compute_mmcr()
[all …]
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| D | ppc970-pmu.c | 149 int pmc, psel, unit, byte, bit; in p970_marked_instr_event() local
152 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; in p970_marked_instr_event()
154 if (pmc) { in p970_marked_instr_event()
155 if (direct_marked_event[pmc - 1] & (1 << psel)) in p970_marked_instr_event()
158 bit = (pmc <= 4)? pmc - 1: 8 - pmc; in p970_marked_instr_event()
197 int pmc, byte, unit, sh, spcsel; in p970_get_constraint() local
201 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; in p970_get_constraint()
202 if (pmc) { in p970_get_constraint()
203 if (pmc > 8) in p970_get_constraint()
205 sh = (pmc - 1) * 2; in p970_get_constraint()
[all …]
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| D | power7-pmu.c | 88 int pmc, sh, unit; in power7_get_constraint() local
91 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; in power7_get_constraint()
92 if (pmc) { in power7_get_constraint()
93 if (pmc > 6) in power7_get_constraint()
95 sh = (pmc - 1) * 2; in power7_get_constraint()
98 if (pmc >= 5 && !(event == 0x500fa || event == 0x600f4)) in power7_get_constraint()
101 if (pmc < 5) { in power7_get_constraint()
148 int pmc, psel; in find_alternative_decode() local
151 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; in find_alternative_decode()
153 if ((pmc == 2 || pmc == 4) && (psel & ~7) == 0x40) in find_alternative_decode()
[all …]
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| D | power5-pmu.c | 143 int pmc, byte, unit, sh; in power5_get_constraint() local
148 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; in power5_get_constraint()
149 if (pmc) { in power5_get_constraint()
150 if (pmc > 6) in power5_get_constraint()
152 sh = (pmc - 1) * 2; in power5_get_constraint()
155 if (pmc <= 4) in power5_get_constraint()
156 grp = (pmc - 1) >> 1; in power5_get_constraint()
188 if (!pmc) in power5_get_constraint()
203 if (pmc < 5) { in power5_get_constraint()
255 int pmc, altpmc, pp, j; in find_alternative_bdecode() local
[all …]
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| D | power5+-pmu.c | 139 int pmc, byte, unit, sh; in power5p_get_constraint() local
143 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; in power5p_get_constraint()
144 if (pmc) { in power5p_get_constraint()
145 if (pmc > 6) in power5p_get_constraint()
147 sh = (pmc - 1) * 2; in power5p_get_constraint()
150 if (pmc >= 5 && !(event == 0x500009 || event == 0x600005)) in power5p_get_constraint()
181 if (pmc < 5) { in power5p_get_constraint()
193 int pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; in power5p_limited_pmc_event() local
195 return pmc == 5 || pmc == 6; in power5p_limited_pmc_event()
247 int pmc, altpmc, pp, j; in find_alternative_bdecode() local
[all …]
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| D | power4-pmu.c | 220 int pmc, psel, unit, byte, bit; in p4_marked_instr_event() local
223 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; in p4_marked_instr_event()
225 if (pmc) { in p4_marked_instr_event()
226 if (direct_marked_event[pmc - 1] & (1 << psel)) in p4_marked_instr_event()
229 bit = (pmc <= 4)? pmc - 1: 8 - pmc; in p4_marked_instr_event()
257 int pmc, byte, unit, lower, sh; in p4_get_constraint() local
261 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; in p4_get_constraint()
262 if (pmc) { in p4_get_constraint()
263 if (pmc > 8) in p4_get_constraint()
265 sh = (pmc - 1) * 2; in p4_get_constraint()
[all …]
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| D | mpc7450-pmu.c | 43 int pmc; in mpc7450_classify_event() local
45 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; in mpc7450_classify_event()
46 if (pmc) { in mpc7450_classify_event()
47 if (pmc > N_COUNTER) in mpc7450_classify_event()
83 int pmc, sel; in mpc7450_threshold_use() local
85 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; in mpc7450_threshold_use()
87 switch (pmc) { in mpc7450_threshold_use()
157 int pmc, class; in mpc7450_get_constraint() local
165 pmc = ((unsigned int)event >> PM_PMC_SH) & PM_PMC_MSK; in mpc7450_get_constraint()
166 mask = pmcbits[pmc - 1][0]; in mpc7450_get_constraint()
[all …]
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| D | power8-pmu.c | 243 #define CNST_PMC_SHIFT(pmc) ((pmc - 1) * 2) argument
244 #define CNST_PMC_VAL(pmc) (1 << CNST_PMC_SHIFT(pmc)) argument
245 #define CNST_PMC_MASK(pmc) (2 << CNST_PMC_SHIFT(pmc)) argument
254 #define MMCR1_UNIT_SHIFT(pmc) (60 - (4 * ((pmc) - 1))) argument
255 #define MMCR1_COMBINE_SHIFT(pmc) (35 - ((pmc) - 1)) argument
256 #define MMCR1_PMCSEL_SHIFT(pmc) (24 - (((pmc) - 1)) * 8) argument
271 #define MMCR2_FCS(pmc) (1ull << (63 - (((pmc) - 1) * 9))) argument
272 #define MMCR2_FCP(pmc) (1ull << (62 - (((pmc) - 1) * 9))) argument
273 #define MMCR2_FCH(pmc) (1ull << (57 - (((pmc) - 1) * 9))) argument
287 unsigned int unit, pmc, cache, ebb; in power8_get_constraint() local
[all …]
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| /arch/x86/platform/atom/ |
| D | pmc_atom.c | 172 static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset) in pmc_reg_read() argument
174 return readl(pmc->regmap + reg_offset); in pmc_reg_read()
177 static inline void pmc_reg_write(struct pmc_dev *pmc, int reg_offset, u32 val) in pmc_reg_write() argument
179 writel(val, pmc->regmap + reg_offset); in pmc_reg_write()
184 struct pmc_dev *pmc = &pmc_device; in pmc_atom_read() local
186 if (!pmc->init) in pmc_atom_read()
189 *value = pmc_reg_read(pmc, offset); in pmc_atom_read()
196 struct pmc_dev *pmc = &pmc_device; in pmc_atom_write() local
198 if (!pmc->init) in pmc_atom_write()
201 pmc_reg_write(pmc, offset, value); in pmc_atom_write()
[all …]
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| /arch/powerpc/oprofile/ |
| D | op_model_pa6t.c | 95 int pmc; in pa6t_reg_setup() local
104 for (pmc = 0; pmc < cur_cpu_spec->num_pmcs; pmc++) in pa6t_reg_setup()
105 if (!ctr[pmc].enabled) { in pa6t_reg_setup()
106 sys->mmcr0 &= ~(0x1UL << pmc); in pa6t_reg_setup()
107 sys->mmcr0 &= ~(0x1UL << (pmc+12)); in pa6t_reg_setup()
108 pr_debug("turned off counter %u\n", pmc); in pa6t_reg_setup()
131 for (pmc = 0; pmc < cur_cpu_spec->num_pmcs; pmc++) { in pa6t_reg_setup()
133 reset_value[pmc] = (0x1UL << 39) - ctr[pmc].count; in pa6t_reg_setup()
135 pmc, reset_value[pmc]); in pa6t_reg_setup()
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| D | op_model_power4.c | 45 int pmc, cntr_marked_events = 0; in power7_marked_instr_event() local
51 for (pmc = 0; pmc < 4; pmc++) { in power7_marked_instr_event()
53 << (OPROFILE_MAX_PMC_NUM - pmc) in power7_marked_instr_event()
55 psel = (psel >> ((OPROFILE_MAX_PMC_NUM - pmc) in power7_marked_instr_event()
59 - (pmc * OPROFILE_PMSEL_FIELD_WIDTH ))); in power7_marked_instr_event()
61 - (pmc * OPROFILE_PMSEL_FIELD_WIDTH)); in power7_marked_instr_event()
65 cntr_marked_events |= (pmc == 1 || pmc == 3) << pmc; in power7_marked_instr_event()
69 cntr_marked_events |= (pmc == 0) << pmc; in power7_marked_instr_event()
74 cntr_marked_events |= (pmc != 1) << pmc; in power7_marked_instr_event()
78 cntr_marked_events |= 1 << pmc; in power7_marked_instr_event()
[all …]
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| /arch/arm/mach-at91/ |
| D | pm_suspend.S | 21 pmc .req r0 label
29 1: ldr tmp1, [pmc, #AT91_PMC_SR]
38 1: ldr tmp1, [pmc, #AT91_PMC_SR]
47 1: ldr tmp1, [pmc, #AT91_PMC_SR]
59 str tmp1, [pmc, #AT91_PMC_SCDR]
112 ldr pmc, .pmc_base
115 ldr tmp1, [pmc, #AT91_PMC_MCKR]
122 str tmp1, [pmc, #AT91_PMC_MCKR]
127 ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
132 str tmp1, [pmc, #AT91_CKGR_PLLAR]
[all …]
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| /arch/powerpc/boot/dts/fsl/ |
| D | mpc8568si-post.dtsi | 40 sleep = <&pmc 0x08000000>;
52 sleep = <&pmc 0x80000000>;
64 sleep = <&pmc 0x20000000>;
90 sleep = <&pmc 0x00080000>;
129 sleep = <&pmc 0x00000004>;
141 sleep = <&pmc 0x00000002>;
158 sleep = <&pmc 0x00000400>;
163 sleep = <&pmc 0x00000080>;
168 sleep = <&pmc 0x00000040>;
178 sleep = <&pmc 0x01000000>;
[all …]
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| D | mpc8569si-post.dtsi | 40 sleep = <&pmc 0x08000000>;
52 sleep = <&pmc 0x20000000>;
78 sleep = <&pmc 0x00080000>;
123 sleep = <&pmc 0x00000004>;
135 sleep = <&pmc 0x00000002>;
153 sleep = <&pmc 0x00200000>;
166 sleep = <&pmc 0x01000000>;
172 sleep = <&pmc 0x00040000>;
183 pmc: power@70 { label
184 compatible = "fsl,mpc8569-pmc",
[all …]
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| /arch/powerpc/boot/dts/ |
| D | mpc8610_hpcd.dts | 38 sleep = <&pmc 0x00008000 0 // core
39 &pmc 0x00004000 0>; // timebase
65 sleep = <&pmc 0x08000000 0>;
171 sleep = <&pmc 0x00000004 0>;
183 sleep = <&pmc 0x00000002 0>;
194 sleep = <&pmc 0x00000008 0>;
207 sleep = <&pmc 0x00000800 0>;
225 sleep = <&pmc 0x04000000 0>;
261 pmc: power@70 { label
262 compatible = "fsl,mpc8610-pmc",
[all …]
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| D | mpc8379_rdb.dts | 132 sleep = <&pmc 0x0c000000>;
247 sleep = <&pmc 0x00c00000>;
265 sleep = <&pmc 0xc0000000>;
302 sleep = <&pmc 0x30000000>;
348 sleep = <&pmc 0x03000000>;
356 sleep = <&pmc 0x000000c0>;
364 sleep = <&pmc 0x00000030>;
372 sleep = <&pmc 0x0000000c>;
380 sleep = <&pmc 0x00000003>;
397 pmc: power@b00 { label
[all …]
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| D | mpc8377_wlan.dts | 124 sleep = <&pmc 0x0c000000>;
225 sleep = <&pmc 0x00c00000>;
243 sleep = <&pmc 0xc0000000>;
286 sleep = <&pmc 0x30000000>;
332 sleep = <&pmc 0x03000000>;
340 sleep = <&pmc 0x000000c0>;
348 sleep = <&pmc 0x00000030>;
365 pmc: power@b00 { label
366 compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc";
389 sleep = <&pmc 0x00010000>;
[all …]
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| D | mpc8379_mds.dts | 134 sleep = <&pmc 0x0c000000>;
234 sleep = <&pmc 0x00c00000>;
252 sleep = <&pmc 0xc0000000>;
295 sleep = <&pmc 0x30000000>;
341 sleep = <&pmc 0x03000000>;
349 sleep = <&pmc 0x000000c0>;
357 sleep = <&pmc 0x00000030>;
365 sleep = <&pmc 0x0000000c>;
373 sleep = <&pmc 0x00000003>;
390 pmc: power@b00 { label
[all …]
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| D | mpc8377_rdb.dts | 134 sleep = <&pmc 0x0c000000>;
249 sleep = <&pmc 0x00c00000>;
267 sleep = <&pmc 0xc0000000>;
304 sleep = <&pmc 0x30000000>;
350 sleep = <&pmc 0x03000000>;
358 sleep = <&pmc 0x000000c0>;
366 sleep = <&pmc 0x00000030>;
383 pmc: power@b00 { label
384 compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc";
414 sleep = <&pmc 0x00010000>;
[all …]
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| /arch/mn10300/include/asm/ |
| D | mmu_context.h | 65 unsigned long *pmc = &mmu_context_cache[smp_processor_id()]; in allocate_mmu_context() local
66 unsigned long mc = ++(*pmc); in allocate_mmu_context()
76 *pmc = mc = MMU_CONTEXT_FIRST_VERSION; in allocate_mmu_context()
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| /arch/arm/boot/dts/ |
| D | sama5d3_tcb1.dtsi | 21 pmc: pmc@fffffc00 { label
|