1 /*
2 * Intel Atom SOC Power Management Controller Driver
3 * Copyright (c) 2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 */
15
16 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
17
18 #include <linux/init.h>
19 #include <linux/pci.h>
20 #include <linux/device.h>
21 #include <linux/debugfs.h>
22 #include <linux/seq_file.h>
23 #include <linux/io.h>
24
25 #include <asm/pmc_atom.h>
26
27 struct pmc_bit_map {
28 const char *name;
29 u32 bit_mask;
30 };
31
32 struct pmc_reg_map {
33 const struct pmc_bit_map *d3_sts_0;
34 const struct pmc_bit_map *d3_sts_1;
35 const struct pmc_bit_map *func_dis;
36 const struct pmc_bit_map *func_dis_2;
37 const struct pmc_bit_map *pss;
38 };
39
40 struct pmc_dev {
41 u32 base_addr;
42 void __iomem *regmap;
43 const struct pmc_reg_map *map;
44 #ifdef CONFIG_DEBUG_FS
45 struct dentry *dbgfs_dir;
46 #endif /* CONFIG_DEBUG_FS */
47 bool init;
48 };
49
50 static struct pmc_dev pmc_device;
51 static u32 acpi_base_addr;
52
53 static const struct pmc_bit_map d3_sts_0_map[] = {
54 {"LPSS1_F0_DMA", BIT_LPSS1_F0_DMA},
55 {"LPSS1_F1_PWM1", BIT_LPSS1_F1_PWM1},
56 {"LPSS1_F2_PWM2", BIT_LPSS1_F2_PWM2},
57 {"LPSS1_F3_HSUART1", BIT_LPSS1_F3_HSUART1},
58 {"LPSS1_F4_HSUART2", BIT_LPSS1_F4_HSUART2},
59 {"LPSS1_F5_SPI", BIT_LPSS1_F5_SPI},
60 {"LPSS1_F6_Reserved", BIT_LPSS1_F6_XXX},
61 {"LPSS1_F7_Reserved", BIT_LPSS1_F7_XXX},
62 {"SCC_EMMC", BIT_SCC_EMMC},
63 {"SCC_SDIO", BIT_SCC_SDIO},
64 {"SCC_SDCARD", BIT_SCC_SDCARD},
65 {"SCC_MIPI", BIT_SCC_MIPI},
66 {"HDA", BIT_HDA},
67 {"LPE", BIT_LPE},
68 {"OTG", BIT_OTG},
69 {"USH", BIT_USH},
70 {"GBE", BIT_GBE},
71 {"SATA", BIT_SATA},
72 {"USB_EHCI", BIT_USB_EHCI},
73 {"SEC", BIT_SEC},
74 {"PCIE_PORT0", BIT_PCIE_PORT0},
75 {"PCIE_PORT1", BIT_PCIE_PORT1},
76 {"PCIE_PORT2", BIT_PCIE_PORT2},
77 {"PCIE_PORT3", BIT_PCIE_PORT3},
78 {"LPSS2_F0_DMA", BIT_LPSS2_F0_DMA},
79 {"LPSS2_F1_I2C1", BIT_LPSS2_F1_I2C1},
80 {"LPSS2_F2_I2C2", BIT_LPSS2_F2_I2C2},
81 {"LPSS2_F3_I2C3", BIT_LPSS2_F3_I2C3},
82 {"LPSS2_F3_I2C4", BIT_LPSS2_F4_I2C4},
83 {"LPSS2_F5_I2C5", BIT_LPSS2_F5_I2C5},
84 {"LPSS2_F6_I2C6", BIT_LPSS2_F6_I2C6},
85 {"LPSS2_F7_I2C7", BIT_LPSS2_F7_I2C7},
86 {},
87 };
88
89 static struct pmc_bit_map byt_d3_sts_1_map[] = {
90 {"SMB", BIT_SMB},
91 {"OTG_SS_PHY", BIT_OTG_SS_PHY},
92 {"USH_SS_PHY", BIT_USH_SS_PHY},
93 {"DFX", BIT_DFX},
94 {},
95 };
96
97 static struct pmc_bit_map cht_d3_sts_1_map[] = {
98 {"SMB", BIT_SMB},
99 {"GMM", BIT_STS_GMM},
100 {"ISH", BIT_STS_ISH},
101 {},
102 };
103
104 static struct pmc_bit_map cht_func_dis_2_map[] = {
105 {"SMB", BIT_SMB},
106 {"GMM", BIT_FD_GMM},
107 {"ISH", BIT_FD_ISH},
108 {},
109 };
110
111 static const struct pmc_bit_map byt_pss_map[] = {
112 {"GBE", PMC_PSS_BIT_GBE},
113 {"SATA", PMC_PSS_BIT_SATA},
114 {"HDA", PMC_PSS_BIT_HDA},
115 {"SEC", PMC_PSS_BIT_SEC},
116 {"PCIE", PMC_PSS_BIT_PCIE},
117 {"LPSS", PMC_PSS_BIT_LPSS},
118 {"LPE", PMC_PSS_BIT_LPE},
119 {"DFX", PMC_PSS_BIT_DFX},
120 {"USH_CTRL", PMC_PSS_BIT_USH_CTRL},
121 {"USH_SUS", PMC_PSS_BIT_USH_SUS},
122 {"USH_VCCS", PMC_PSS_BIT_USH_VCCS},
123 {"USH_VCCA", PMC_PSS_BIT_USH_VCCA},
124 {"OTG_CTRL", PMC_PSS_BIT_OTG_CTRL},
125 {"OTG_VCCS", PMC_PSS_BIT_OTG_VCCS},
126 {"OTG_VCCA_CLK", PMC_PSS_BIT_OTG_VCCA_CLK},
127 {"OTG_VCCA", PMC_PSS_BIT_OTG_VCCA},
128 {"USB", PMC_PSS_BIT_USB},
129 {"USB_SUS", PMC_PSS_BIT_USB_SUS},
130 {},
131 };
132
133 static const struct pmc_bit_map cht_pss_map[] = {
134 {"SATA", PMC_PSS_BIT_SATA},
135 {"HDA", PMC_PSS_BIT_HDA},
136 {"SEC", PMC_PSS_BIT_SEC},
137 {"PCIE", PMC_PSS_BIT_PCIE},
138 {"LPSS", PMC_PSS_BIT_LPSS},
139 {"LPE", PMC_PSS_BIT_LPE},
140 {"UFS", PMC_PSS_BIT_CHT_UFS},
141 {"UXD", PMC_PSS_BIT_CHT_UXD},
142 {"UXD_FD", PMC_PSS_BIT_CHT_UXD_FD},
143 {"UX_ENG", PMC_PSS_BIT_CHT_UX_ENG},
144 {"USB_SUS", PMC_PSS_BIT_CHT_USB_SUS},
145 {"GMM", PMC_PSS_BIT_CHT_GMM},
146 {"ISH", PMC_PSS_BIT_CHT_ISH},
147 {"DFX_MASTER", PMC_PSS_BIT_CHT_DFX_MASTER},
148 {"DFX_CLUSTER1", PMC_PSS_BIT_CHT_DFX_CLUSTER1},
149 {"DFX_CLUSTER2", PMC_PSS_BIT_CHT_DFX_CLUSTER2},
150 {"DFX_CLUSTER3", PMC_PSS_BIT_CHT_DFX_CLUSTER3},
151 {"DFX_CLUSTER4", PMC_PSS_BIT_CHT_DFX_CLUSTER4},
152 {"DFX_CLUSTER5", PMC_PSS_BIT_CHT_DFX_CLUSTER5},
153 {},
154 };
155
156 static const struct pmc_reg_map byt_reg_map = {
157 .d3_sts_0 = d3_sts_0_map,
158 .d3_sts_1 = byt_d3_sts_1_map,
159 .func_dis = d3_sts_0_map,
160 .func_dis_2 = byt_d3_sts_1_map,
161 .pss = byt_pss_map,
162 };
163
164 static const struct pmc_reg_map cht_reg_map = {
165 .d3_sts_0 = d3_sts_0_map,
166 .d3_sts_1 = cht_d3_sts_1_map,
167 .func_dis = d3_sts_0_map,
168 .func_dis_2 = cht_func_dis_2_map,
169 .pss = cht_pss_map,
170 };
171
pmc_reg_read(struct pmc_dev * pmc,int reg_offset)172 static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset)
173 {
174 return readl(pmc->regmap + reg_offset);
175 }
176
pmc_reg_write(struct pmc_dev * pmc,int reg_offset,u32 val)177 static inline void pmc_reg_write(struct pmc_dev *pmc, int reg_offset, u32 val)
178 {
179 writel(val, pmc->regmap + reg_offset);
180 }
181
pmc_atom_read(int offset,u32 * value)182 int pmc_atom_read(int offset, u32 *value)
183 {
184 struct pmc_dev *pmc = &pmc_device;
185
186 if (!pmc->init)
187 return -ENODEV;
188
189 *value = pmc_reg_read(pmc, offset);
190 return 0;
191 }
192 EXPORT_SYMBOL_GPL(pmc_atom_read);
193
pmc_atom_write(int offset,u32 value)194 int pmc_atom_write(int offset, u32 value)
195 {
196 struct pmc_dev *pmc = &pmc_device;
197
198 if (!pmc->init)
199 return -ENODEV;
200
201 pmc_reg_write(pmc, offset, value);
202 return 0;
203 }
204 EXPORT_SYMBOL_GPL(pmc_atom_write);
205
pmc_power_off(void)206 static void pmc_power_off(void)
207 {
208 u16 pm1_cnt_port;
209 u32 pm1_cnt_value;
210
211 pr_info("Preparing to enter system sleep state S5\n");
212
213 pm1_cnt_port = acpi_base_addr + PM1_CNT;
214
215 pm1_cnt_value = inl(pm1_cnt_port);
216 pm1_cnt_value &= SLEEP_TYPE_MASK;
217 pm1_cnt_value |= SLEEP_TYPE_S5;
218 pm1_cnt_value |= SLEEP_ENABLE;
219
220 outl(pm1_cnt_value, pm1_cnt_port);
221 }
222
pmc_hw_reg_setup(struct pmc_dev * pmc)223 static void pmc_hw_reg_setup(struct pmc_dev *pmc)
224 {
225 /*
226 * Disable PMC S0IX_WAKE_EN events coming from:
227 * - LPC clock run
228 * - GPIO_SUS ored dedicated IRQs
229 * - GPIO_SCORE ored dedicated IRQs
230 * - GPIO_SUS shared IRQ
231 * - GPIO_SCORE shared IRQ
232 */
233 pmc_reg_write(pmc, PMC_S0IX_WAKE_EN, (u32)PMC_WAKE_EN_SETTING);
234 }
235
236 #ifdef CONFIG_DEBUG_FS
pmc_dev_state_print(struct seq_file * s,int reg_index,u32 sts,const struct pmc_bit_map * sts_map,u32 fd,const struct pmc_bit_map * fd_map)237 static void pmc_dev_state_print(struct seq_file *s, int reg_index,
238 u32 sts, const struct pmc_bit_map *sts_map,
239 u32 fd, const struct pmc_bit_map *fd_map)
240 {
241 int offset = PMC_REG_BIT_WIDTH * reg_index;
242 int index;
243
244 for (index = 0; sts_map[index].name; index++) {
245 seq_printf(s, "Dev: %-2d - %-32s\tState: %s [%s]\n",
246 offset + index, sts_map[index].name,
247 fd_map[index].bit_mask & fd ? "Disabled" : "Enabled ",
248 sts_map[index].bit_mask & sts ? "D3" : "D0");
249 }
250 }
251
pmc_dev_state_show(struct seq_file * s,void * unused)252 static int pmc_dev_state_show(struct seq_file *s, void *unused)
253 {
254 struct pmc_dev *pmc = s->private;
255 const struct pmc_reg_map *m = pmc->map;
256 u32 func_dis, func_dis_2;
257 u32 d3_sts_0, d3_sts_1;
258
259 func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS);
260 func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2);
261 d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0);
262 d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1);
263
264 /* Low part */
265 pmc_dev_state_print(s, 0, d3_sts_0, m->d3_sts_0, func_dis, m->func_dis);
266
267 /* High part */
268 pmc_dev_state_print(s, 1, d3_sts_1, m->d3_sts_1, func_dis_2, m->func_dis_2);
269
270 return 0;
271 }
272
pmc_dev_state_open(struct inode * inode,struct file * file)273 static int pmc_dev_state_open(struct inode *inode, struct file *file)
274 {
275 return single_open(file, pmc_dev_state_show, inode->i_private);
276 }
277
278 static const struct file_operations pmc_dev_state_ops = {
279 .open = pmc_dev_state_open,
280 .read = seq_read,
281 .llseek = seq_lseek,
282 .release = single_release,
283 };
284
pmc_pss_state_show(struct seq_file * s,void * unused)285 static int pmc_pss_state_show(struct seq_file *s, void *unused)
286 {
287 struct pmc_dev *pmc = s->private;
288 const struct pmc_bit_map *map = pmc->map->pss;
289 u32 pss = pmc_reg_read(pmc, PMC_PSS);
290 int index;
291
292 for (index = 0; map[index].name; index++) {
293 seq_printf(s, "Island: %-2d - %-32s\tState: %s\n",
294 index, map[index].name,
295 map[index].bit_mask & pss ? "Off" : "On");
296 }
297 return 0;
298 }
299
pmc_pss_state_open(struct inode * inode,struct file * file)300 static int pmc_pss_state_open(struct inode *inode, struct file *file)
301 {
302 return single_open(file, pmc_pss_state_show, inode->i_private);
303 }
304
305 static const struct file_operations pmc_pss_state_ops = {
306 .open = pmc_pss_state_open,
307 .read = seq_read,
308 .llseek = seq_lseek,
309 .release = single_release,
310 };
311
pmc_sleep_tmr_show(struct seq_file * s,void * unused)312 static int pmc_sleep_tmr_show(struct seq_file *s, void *unused)
313 {
314 struct pmc_dev *pmc = s->private;
315 u64 s0ir_tmr, s0i1_tmr, s0i2_tmr, s0i3_tmr, s0_tmr;
316
317 s0ir_tmr = (u64)pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
318 s0i1_tmr = (u64)pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
319 s0i2_tmr = (u64)pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
320 s0i3_tmr = (u64)pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
321 s0_tmr = (u64)pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;
322
323 seq_printf(s, "S0IR Residency:\t%lldus\n", s0ir_tmr);
324 seq_printf(s, "S0I1 Residency:\t%lldus\n", s0i1_tmr);
325 seq_printf(s, "S0I2 Residency:\t%lldus\n", s0i2_tmr);
326 seq_printf(s, "S0I3 Residency:\t%lldus\n", s0i3_tmr);
327 seq_printf(s, "S0 Residency:\t%lldus\n", s0_tmr);
328 return 0;
329 }
330
pmc_sleep_tmr_open(struct inode * inode,struct file * file)331 static int pmc_sleep_tmr_open(struct inode *inode, struct file *file)
332 {
333 return single_open(file, pmc_sleep_tmr_show, inode->i_private);
334 }
335
336 static const struct file_operations pmc_sleep_tmr_ops = {
337 .open = pmc_sleep_tmr_open,
338 .read = seq_read,
339 .llseek = seq_lseek,
340 .release = single_release,
341 };
342
pmc_dbgfs_unregister(struct pmc_dev * pmc)343 static void pmc_dbgfs_unregister(struct pmc_dev *pmc)
344 {
345 debugfs_remove_recursive(pmc->dbgfs_dir);
346 }
347
pmc_dbgfs_register(struct pmc_dev * pmc)348 static int pmc_dbgfs_register(struct pmc_dev *pmc)
349 {
350 struct dentry *dir, *f;
351
352 dir = debugfs_create_dir("pmc_atom", NULL);
353 if (!dir)
354 return -ENOMEM;
355
356 pmc->dbgfs_dir = dir;
357
358 f = debugfs_create_file("dev_state", S_IFREG | S_IRUGO,
359 dir, pmc, &pmc_dev_state_ops);
360 if (!f)
361 goto err;
362
363 f = debugfs_create_file("pss_state", S_IFREG | S_IRUGO,
364 dir, pmc, &pmc_pss_state_ops);
365 if (!f)
366 goto err;
367
368 f = debugfs_create_file("sleep_state", S_IFREG | S_IRUGO,
369 dir, pmc, &pmc_sleep_tmr_ops);
370 if (!f)
371 goto err;
372
373 return 0;
374 err:
375 pmc_dbgfs_unregister(pmc);
376 return -ENODEV;
377 }
378 #else
pmc_dbgfs_register(struct pmc_dev * pmc)379 static int pmc_dbgfs_register(struct pmc_dev *pmc)
380 {
381 return 0;
382 }
383 #endif /* CONFIG_DEBUG_FS */
384
pmc_setup_dev(struct pci_dev * pdev,const struct pci_device_id * ent)385 static int pmc_setup_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
386 {
387 struct pmc_dev *pmc = &pmc_device;
388 const struct pmc_reg_map *map = (struct pmc_reg_map *)ent->driver_data;
389 int ret;
390
391 /* Obtain ACPI base address */
392 pci_read_config_dword(pdev, ACPI_BASE_ADDR_OFFSET, &acpi_base_addr);
393 acpi_base_addr &= ACPI_BASE_ADDR_MASK;
394
395 /* Install power off function */
396 if (acpi_base_addr != 0 && pm_power_off == NULL)
397 pm_power_off = pmc_power_off;
398
399 pci_read_config_dword(pdev, PMC_BASE_ADDR_OFFSET, &pmc->base_addr);
400 pmc->base_addr &= PMC_BASE_ADDR_MASK;
401
402 pmc->regmap = ioremap_nocache(pmc->base_addr, PMC_MMIO_REG_LEN);
403 if (!pmc->regmap) {
404 dev_err(&pdev->dev, "error: ioremap failed\n");
405 return -ENOMEM;
406 }
407
408 pmc->map = map;
409
410 /* PMC hardware registers setup */
411 pmc_hw_reg_setup(pmc);
412
413 ret = pmc_dbgfs_register(pmc);
414 if (ret)
415 dev_warn(&pdev->dev, "debugfs register failed\n");
416
417 pmc->init = true;
418 return ret;
419 }
420
421 /*
422 * Data for PCI driver interface
423 *
424 * used by pci_match_id() call below.
425 */
426 static const struct pci_device_id pmc_pci_ids[] = {
427 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_VLV_PMC), (kernel_ulong_t)&byt_reg_map },
428 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_CHT_PMC), (kernel_ulong_t)&cht_reg_map },
429 { 0, },
430 };
431
pmc_atom_init(void)432 static int __init pmc_atom_init(void)
433 {
434 struct pci_dev *pdev = NULL;
435 const struct pci_device_id *ent;
436
437 /* We look for our device - PCU PMC
438 * we assume that there is max. one device.
439 *
440 * We can't use plain pci_driver mechanism,
441 * as the device is really a multiple function device,
442 * main driver that binds to the pci_device is lpc_ich
443 * and have to find & bind to the device this way.
444 */
445 for_each_pci_dev(pdev) {
446 ent = pci_match_id(pmc_pci_ids, pdev);
447 if (ent)
448 return pmc_setup_dev(pdev, ent);
449 }
450 /* Device not found. */
451 return -ENODEV;
452 }
453
454 device_initcall(pmc_atom_init);
455
456 /*
457 MODULE_AUTHOR("Aubrey Li <aubrey.li@linux.intel.com>");
458 MODULE_DESCRIPTION("Intel Atom SOC Power Management Controller Interface");
459 MODULE_LICENSE("GPL v2");
460 */
461