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Searched refs:pstate (Results 1 – 25 of 48) sorted by relevance

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/arch/arm64/include/asm/
Dptrace.h115 u64 pstate; member
128 (((regs)->pstate & COMPAT_PSR_T_BIT))
134 (((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t)
137 (((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == \
141 ((regs)->pstate & PSR_MODE_MASK)
144 (!((regs)->pstate & PSR_I_BIT))
147 (!((regs)->pstate & PSR_F_BIT))
Dprocessor.h120 regs->pstate = PSR_MODE_EL0t; in start_thread()
129 regs->pstate = COMPAT_PSR_MODE_USR; in compat_start_thread()
131 regs->pstate |= COMPAT_PSR_T_BIT; in compat_start_thread()
134 regs->pstate |= COMPAT_PSR_E_BIT; in compat_start_thread()
Dperf_event.h33 (regs)->pstate = PSR_MODE_EL1h; \
/arch/x86/kernel/cpu/mcheck/
Dtherm_throt.c157 struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu); in therm_throt_process() local
162 state = &pstate->core_throttle; in therm_throt_process()
164 state = &pstate->core_power_limit; in therm_throt_process()
169 state = &pstate->package_throttle; in therm_throt_process()
171 state = &pstate->package_power_limit; in therm_throt_process()
214 struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu); in thresh_event_valid() local
218 state = (event == 0) ? &pstate->pkg_thresh0 : in thresh_event_valid()
219 &pstate->pkg_thresh1; in thresh_event_valid()
221 state = (event == 0) ? &pstate->core_thresh0 : in thresh_event_valid()
222 &pstate->core_thresh1; in thresh_event_valid()
/arch/sparc/kernel/
Dhelpers.S27 rdpr %pstate, %o0
28 wrpr %o0, PSTATE_IE, %pstate
43 wrpr %o0, %pstate
Dspiterrs.S157 rdpr %pstate, %g4
158 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
185 rdpr %pstate, %g4
186 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
205 rdpr %pstate, %g4
206 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
224 rdpr %pstate, %g4
225 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
Drtrap_64.S27 wrpr %g0, RTRAP_PSTATE, %pstate
29 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
33 wrpr %g0, RTRAP_PSTATE, %pstate
35 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
50 wrpr %g0, RTRAP_PSTATE, %pstate
51 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
129 to_user: wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
171 661: wrpr %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
175 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
Ddtlb_prot.S20 rdpr %pstate, %g5 ! Move into alt-globals
21 wrpr %g5, PSTATE_AG|PSTATE_MG, %pstate
Dtsb.S161 661: rdpr %pstate, %g5
162 wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
268 661: rdpr %pstate, %g5
269 wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
334 rdpr %pstate, %o5
335 wrpr %o5, PSTATE_IE, %pstate
338 wrpr %o5, %pstate
388 rdpr %pstate, %g1
389 wrpr %g1, PSTATE_IE, %pstate
471 wrpr %g1, %pstate
Dsmp_64.c390 static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu) in spitfire_xcall_helper() argument
425 : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W), in spitfire_xcall_helper()
438 : : "r" (pstate)); in spitfire_xcall_helper()
446 : : "r" (pstate)); in spitfire_xcall_helper()
460 u64 pstate; in spitfire_xcall_deliver() local
463 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate)); in spitfire_xcall_deliver()
470 spitfire_xcall_helper(data0, data1, data2, pstate, cpu_list[i]); in spitfire_xcall_deliver()
480 u64 *mondo, pstate, ver, busy_mask; in cheetah_xcall_deliver() local
494 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate)); in cheetah_xcall_deliver()
499 : : "r" (pstate), "i" (PSTATE_IE)); in cheetah_xcall_deliver()
[all …]
Dktlb.S85 661: rdpr %pstate, %g5
86 wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
243 661: rdpr %pstate, %g5
244 wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
Dhvtramp.S81 wrpr %g0, (PSTATE_PRIV | PSTATE_PEF), %pstate
124 wrpr %g0, (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE), %pstate
Dasm-offsets.c36 OFFSET(SC_REG_PSTATE, saved_context, pstate); in sparc64_foo()
/arch/arm64/kvm/
Dreset.c38 .regs.pstate = (PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT |
43 .regs.pstate = (COMPAT_PSR_MODE_SVC | COMPAT_PSR_A_BIT |
/arch/sparc/lib/
Dclear_page.S62 rdpr %pstate, %o4
63 wrpr %o4, PSTATE_IE, %pstate
68 wrpr %o4, 0x0, %pstate
/arch/arm64/kernel/
Dptrace.c702 reg = task_pt_regs(target)->pstate; in compat_gpr_get()
770 newregs.pstate = reg; in compat_gpr_set()
1297 regs->pstate &= ~SPSR_EL1_AARCH32_RES0_BITS; in valid_compat_regs()
1301 regs->pstate |= COMPAT_PSR_E_BIT; in valid_compat_regs()
1303 regs->pstate &= ~COMPAT_PSR_E_BIT; in valid_compat_regs()
1306 if (user_mode(regs) && (regs->pstate & PSR_MODE32_BIT) && in valid_compat_regs()
1307 (regs->pstate & COMPAT_PSR_A_BIT) == 0 && in valid_compat_regs()
1308 (regs->pstate & COMPAT_PSR_I_BIT) == 0 && in valid_compat_regs()
1309 (regs->pstate & COMPAT_PSR_F_BIT) == 0) { in valid_compat_regs()
1317 regs->pstate &= COMPAT_PSR_N_BIT | COMPAT_PSR_Z_BIT | in valid_compat_regs()
[all …]
Ddebug-monitors.c171 spsr = regs->pstate; in set_regs_spsr_ss()
174 regs->pstate = spsr; in set_regs_spsr_ss()
181 spsr = regs->pstate; in clear_regs_spsr_ss()
183 regs->pstate = spsr; in clear_regs_spsr_ss()
Dprocess.c255 regs->pc, lr, regs->pstate); in __show_regs()
355 childregs->pstate = PSR_MODE_EL1h; in copy_thread()
358 childregs->pstate |= PSR_UAO_BIT; in copy_thread()
Dsignal.c111 __get_user_error(regs->pstate, &sf->uc.uc_mcontext.pstate, err); in restore_sigframe()
181 __put_user_error(regs->pstate, &sf->uc.uc_mcontext.pstate, err); in setup_sigframe()
/arch/sparc/include/asm/
Dhibernate.h16 unsigned long pstate; member
/arch/sparc/mm/
Dultra.S59 rdpr %pstate, %g7
61 wrpr %g2, %pstate
76 wrpr %g7, 0x0, %pstate
86 rdpr %pstate, %g7
89 wrpr %g2, %pstate
108 wrpr %g7, 0x0, %pstate
173 rdpr %pstate, %g1
174 wrpr %g1, PSTATE_IE, %pstate
183 wrpr %g1, 0, %pstate
250 rdpr %pstate, %g7
[all …]
/arch/arm64/include/asm/xen/
Devents.h16 return raw_irqs_disabled_flags((unsigned long) regs->pstate); in xen_irqs_disabled()
/arch/arm64/include/uapi/asm/
Dsigcontext.h31 __u64 pstate; member
Dptrace.h73 __u64 pstate; member
/arch/sparc/power/
Dhibernate_asm.S30 rdpr %pstate, %g2
110 wrpr %g2, %pstate

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