| /arch/x86/kernel/cpu/mcheck/ |
| D | p5.c | 26 rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi); in pentium_machine_check()
27 rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi); in pentium_machine_check()
62 rdmsr(MSR_IA32_P5_MC_ADDR, l, h); in intel_p5_mcheck_init()
63 rdmsr(MSR_IA32_P5_MC_TYPE, l, h); in intel_p5_mcheck_init()
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| D | therm_throt.c | 486 rdmsr(MSR_IA32_MISC_ENABLE, l, h); in intel_init_thermal()
512 rdmsr(MSR_THERM2_CTL, l, h); in intel_init_thermal()
523 rdmsr(MSR_IA32_THERM_INTERRUPT, l, h); in intel_init_thermal()
537 rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); in intel_init_thermal()
556 rdmsr(MSR_IA32_MISC_ENABLE, l, h); in intel_init_thermal()
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| D | winchip.c | 35 rdmsr(MSR_IDT_FCR1, lo, hi); in winchip_mcheck_init()
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| /arch/x86/kernel/cpu/mtrr/ |
| D | generic.c | 56 rdmsr(MSR_K8_SYSCFG, lo, hi); in k8_check_syscfg_dram_mod_en()
317 rdmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi); in get_mtrr_var_range()
318 rdmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi); in get_mtrr_var_range()
342 rdmsr(MSR_MTRRfix64K_00000, p[0], p[1]); in get_fixed_ranges()
345 rdmsr(MSR_MTRRfix16K_80000 + i, p[2 + i * 2], p[3 + i * 2]); in get_fixed_ranges()
347 rdmsr(MSR_MTRRfix4K_C0000 + i, p[6 + i * 2], p[7 + i * 2]); in get_fixed_ranges()
470 rdmsr(MSR_MTRRcap, lo, dummy); in get_mtrr_state()
478 rdmsr(MSR_MTRRdefType, lo, dummy); in get_mtrr_state()
486 rdmsr(MSR_K8_TOP_MEM2, low, high); in get_mtrr_state()
543 rdmsr(msr, lo, hi); in set_fixed_range()
[all …]
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| D | amd.c | 14 rdmsr(MSR_K6_UWCCR, low, high); in amd_get_mtrr()
66 rdmsr(MSR_K6_UWCCR, regs[0], regs[1]); in amd_set_mtrr()
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| D | cleanup.c | 690 rdmsr(MSR_MTRRdefType, def, dummy); in mtrr_cleanup()
887 rdmsr(MSR_MTRRdefType, def, dummy); in mtrr_trim_uncached_memory()
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| D | main.c | 128 rdmsr(MSR_MTRRcap, config, dummy); in set_num_var_ranges()
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| /arch/x86/kernel/ |
| D | tsc_msr.c | 95 rdmsr(MSR_PLATFORM_INFO, lo, hi); in try_msr_calibrate_tsc()
98 rdmsr(MSR_IA32_PERF_STATUS, lo, hi); in try_msr_calibrate_tsc()
107 rdmsr(MSR_FSB_FREQ, lo, hi); in try_msr_calibrate_tsc()
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| D | verify_cpu.S | 96 rdmsr
128 rdmsr
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| D | process.c | 539 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); in amd_e400_idle()
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| /arch/x86/platform/intel-mid/ |
| D | mfld.c | 35 rdmsr(MSR_IA32_PERF_STATUS, lo, hi); in mfld_calibrate_tsc()
44 rdmsr(MSR_FSB_FREQ, lo, hi); in mfld_calibrate_tsc()
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| D | mrfl.c | 29 rdmsr(MSR_PLATFORM_INFO, lo, hi); in tangier_calibrate_tsc()
40 rdmsr(MSR_FSB_FREQ, lo, hi); in tangier_calibrate_tsc()
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| /arch/x86/kernel/cpu/ |
| D | centaur.c | 29 rdmsr(MSR_VIA_FCR, lo, hi); in init_c3()
37 rdmsr(MSR_VIA_RNG, lo, hi); in init_c3()
51 rdmsr(MSR_VIA_FCR, lo, hi); in init_c3()
162 rdmsr(MSR_IDT_FCR1, lo, hi); in init_centaur()
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| D | transmeta.c | 83 rdmsr(0x80860004, cap_mask, uk); in init_transmeta()
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| D | intel.c | 426 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high); in detect_vmx_virtcap()
433 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, in detect_vmx_virtcap()
522 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); in init_intel()
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| D | amd.c | 150 rdmsr(MSR_K6_WHCR, l, h); in init_amd_k6()
171 rdmsr(MSR_K6_WHCR, l, h); in init_amd_k6()
218 rdmsr(MSR_K7_CLK_CTL, l, h); in init_amd_k7()
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| /arch/x86/oprofile/ |
| D | op_model_p4.c | 534 rdmsr(ev->bindings[i].escr_address, escr, high); in pmc_setup_one_p4_counter()
548 rdmsr(p4_counters[VIRT_CTR(stag, ctr)].cccr_address, in pmc_setup_one_p4_counter()
578 rdmsr(MSR_IA32_MISC_ENABLE, low, high); in p4_setup_ctrs()
588 rdmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high); in p4_setup_ctrs()
647 rdmsr(p4_counters[real].cccr_address, low, high); in p4_check_ctrs()
648 rdmsr(p4_counters[real].counter_address, ctr, high); in p4_check_ctrs()
678 rdmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high); in p4_start()
695 rdmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high); in p4_stop()
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| /arch/x86/boot/compressed/ |
| D | efi_thunk_64.S | 131 rdmsr
158 rdmsr
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| D | head_64.S | 169 rdmsr
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| /arch/x86/lib/ |
| D | msr-reg.S | 90 op_safe_regs rdmsr
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| D | msr-smp.c | 17 rdmsr(rv->msr_no, reg->l, reg->h); in __rdmsr_on_cpu()
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| /arch/x86/xen/ |
| D | xen-head.S | 72 rdmsr
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| /arch/x86/include/asm/ |
| D | msr.h | 185 #define rdmsr(msr, low, high) \ macro
273 rdmsr(msr_no, *l, *h); in rdmsr_on_cpu()
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| /arch/x86/kernel/apic/ |
| D | apic.c | 1107 rdmsr(MSR_IA32_APICBASE, l, h); in disable_local_APIC()
1711 rdmsr(MSR_IA32_APICBASE, l, h); in apic_verify()
1733 rdmsr(MSR_IA32_APICBASE, l, h); in apic_force_enable()
2400 rdmsr(MSR_IA32_APICBASE, l, h); in lapic_resume()
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| /arch/x86/platform/olpc/ |
| D | olpc-xo1-sci.c | 318 rdmsr(0x51400020, lo, hi); in setup_sci_interrupt()
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