1 /*
2 * P5 specific Machine Check Exception Reporting
3 * (C) Copyright 2002 Alan Cox <alan@lxorguk.ukuu.org.uk>
4 */
5 #include <linux/interrupt.h>
6 #include <linux/kernel.h>
7 #include <linux/types.h>
8 #include <linux/smp.h>
9
10 #include <asm/processor.h>
11 #include <asm/traps.h>
12 #include <asm/tlbflush.h>
13 #include <asm/mce.h>
14 #include <asm/msr.h>
15
16 /* By default disabled */
17 int mce_p5_enabled __read_mostly;
18
19 /* Machine check handler for Pentium class Intel CPUs: */
pentium_machine_check(struct pt_regs * regs,long error_code)20 static void pentium_machine_check(struct pt_regs *regs, long error_code)
21 {
22 u32 loaddr, hi, lotype;
23
24 ist_enter(regs);
25
26 rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
27 rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);
28
29 printk(KERN_EMERG
30 "CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n",
31 smp_processor_id(), loaddr, lotype);
32
33 if (lotype & (1<<5)) {
34 printk(KERN_EMERG
35 "CPU#%d: Possible thermal failure (CPU on fire ?).\n",
36 smp_processor_id());
37 }
38
39 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
40
41 ist_exit(regs);
42 }
43
44 /* Set up machine check reporting for processors with Intel style MCE: */
intel_p5_mcheck_init(struct cpuinfo_x86 * c)45 void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
46 {
47 u32 l, h;
48
49 /* Default P5 to off as its often misconnected: */
50 if (!mce_p5_enabled)
51 return;
52
53 /* Check for MCE support: */
54 if (!cpu_has(c, X86_FEATURE_MCE))
55 return;
56
57 machine_check_vector = pentium_machine_check;
58 /* Make sure the vector pointer is visible before we enable MCEs: */
59 wmb();
60
61 /* Read registers before enabling: */
62 rdmsr(MSR_IA32_P5_MC_ADDR, l, h);
63 rdmsr(MSR_IA32_P5_MC_TYPE, l, h);
64 printk(KERN_INFO
65 "Intel old style machine check architecture supported.\n");
66
67 /* Enable MCE: */
68 cr4_set_bits(X86_CR4_MCE);
69 printk(KERN_INFO
70 "Intel old style machine check reporting enabled on CPU#%d.\n",
71 smp_processor_id());
72 }
73