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Searched refs:sor (Results 1 – 7 of 7) sorted by relevance

/arch/powerpc/sysdev/
Dcpm2.c330 u32 dir, par, sor, odr, dat; member
352 setbits32(&iop[port].sor, pin); in cpm2_set_pin()
354 clrbits32(&iop[port].sor, pin); in cpm2_set_pin()
Dcpm1.c303 __be32 dir, par, sor, odr, dat; member
337 setbits32(&iop->sor, pin); in cpm1_set_pin32()
339 clrbits32(&iop->sor, pin); in cpm1_set_pin32()
Dcpm_common.c227 u32 dir, par, sor, odr, dat; member
/arch/ia64/kernel/
Dunaligned.c296 rotate_reg (unsigned long sor, unsigned long rrb, unsigned long reg) in rotate_reg() argument
299 if (reg >= sor) in rotate_reg()
300 reg -= sor; in rotate_reg()
313 long sor = 8 * ((regs->cr_ifs >> 14) & 0xf); in set_rse_reg() local
323 if (ridx < sor) in set_rse_reg()
324 ridx = rotate_reg(sor, rrb_gr, ridx); in set_rse_reg()
386 long sor = 8 * ((regs->cr_ifs >> 14) & 0xf); in get_rse_reg() local
396 if (ridx < sor) in get_rse_reg()
397 ridx = rotate_reg(sor, rrb_gr, ridx); in get_rse_reg()
/arch/arm/boot/dts/
Dtegra124.dtsi140 sor@0,54540000 {
141 compatible = "nvidia,tegra124-sor";
148 clock-names = "sor", "parent", "dp", "safe";
150 reset-names = "sor";
Dtegra124-nyan.dtsi28 sor@0,54540000 {
Dtegra124-venice2.dts33 sor@0,54540000 {