1 /*
2 * Common CPM code
3 *
4 * Author: Scott Wood <scottwood@freescale.com>
5 *
6 * Copyright 2007-2008,2010 Freescale Semiconductor, Inc.
7 *
8 * Some parts derived from commproc.c/cpm2_common.c, which is:
9 * Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
10 * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
11 * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
12 * 2006 (c) MontaVista Software, Inc.
13 * Vitaly Bordug <vbordug@ru.mvista.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of version 2 of the GNU General Public License as
17 * published by the Free Software Foundation.
18 */
19
20 #include <linux/init.h>
21 #include <linux/of_device.h>
22 #include <linux/spinlock.h>
23 #include <linux/export.h>
24 #include <linux/of.h>
25 #include <linux/of_address.h>
26 #include <linux/slab.h>
27
28 #include <asm/udbg.h>
29 #include <asm/io.h>
30 #include <asm/rheap.h>
31 #include <asm/cpm.h>
32
33 #include <mm/mmu_decl.h>
34
35 #if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
36 #include <linux/of_gpio.h>
37 #endif
38
39 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
40 static u32 __iomem *cpm_udbg_txdesc =
41 (u32 __iomem __force *)CONFIG_PPC_EARLY_DEBUG_CPM_ADDR;
42
udbg_putc_cpm(char c)43 static void udbg_putc_cpm(char c)
44 {
45 u8 __iomem *txbuf = (u8 __iomem __force *)in_be32(&cpm_udbg_txdesc[1]);
46
47 if (c == '\n')
48 udbg_putc_cpm('\r');
49
50 while (in_be32(&cpm_udbg_txdesc[0]) & 0x80000000)
51 ;
52
53 out_8(txbuf, c);
54 out_be32(&cpm_udbg_txdesc[0], 0xa0000001);
55 }
56
udbg_init_cpm(void)57 void __init udbg_init_cpm(void)
58 {
59 if (cpm_udbg_txdesc) {
60 #ifdef CONFIG_CPM2
61 setbat(1, 0xf0000000, 0xf0000000, 1024*1024, PAGE_KERNEL_NCG);
62 #endif
63 udbg_putc = udbg_putc_cpm;
64 }
65 }
66 #endif
67
68 static spinlock_t cpm_muram_lock;
69 static rh_block_t cpm_boot_muram_rh_block[16];
70 static rh_info_t cpm_muram_info;
71 static u8 __iomem *muram_vbase;
72 static phys_addr_t muram_pbase;
73
74 /* Max address size we deal with */
75 #define OF_MAX_ADDR_CELLS 4
76
cpm_muram_init(void)77 int cpm_muram_init(void)
78 {
79 struct device_node *np;
80 struct resource r;
81 u32 zero[OF_MAX_ADDR_CELLS] = {};
82 resource_size_t max = 0;
83 int i = 0;
84 int ret = 0;
85
86 if (muram_pbase)
87 return 0;
88
89 spin_lock_init(&cpm_muram_lock);
90 /* initialize the info header */
91 rh_init(&cpm_muram_info, 1,
92 sizeof(cpm_boot_muram_rh_block) /
93 sizeof(cpm_boot_muram_rh_block[0]),
94 cpm_boot_muram_rh_block);
95
96 np = of_find_compatible_node(NULL, NULL, "fsl,cpm-muram-data");
97 if (!np) {
98 /* try legacy bindings */
99 np = of_find_node_by_name(NULL, "data-only");
100 if (!np) {
101 printk(KERN_ERR "Cannot find CPM muram data node");
102 ret = -ENODEV;
103 goto out;
104 }
105 }
106
107 muram_pbase = of_translate_address(np, zero);
108 if (muram_pbase == (phys_addr_t)OF_BAD_ADDR) {
109 printk(KERN_ERR "Cannot translate zero through CPM muram node");
110 ret = -ENODEV;
111 goto out;
112 }
113
114 while (of_address_to_resource(np, i++, &r) == 0) {
115 if (r.end > max)
116 max = r.end;
117
118 rh_attach_region(&cpm_muram_info, r.start - muram_pbase,
119 resource_size(&r));
120 }
121
122 muram_vbase = ioremap(muram_pbase, max - muram_pbase + 1);
123 if (!muram_vbase) {
124 printk(KERN_ERR "Cannot map CPM muram");
125 ret = -ENOMEM;
126 }
127
128 out:
129 of_node_put(np);
130 return ret;
131 }
132
133 /**
134 * cpm_muram_alloc - allocate the requested size worth of multi-user ram
135 * @size: number of bytes to allocate
136 * @align: requested alignment, in bytes
137 *
138 * This function returns an offset into the muram area.
139 * Use cpm_dpram_addr() to get the virtual address of the area.
140 * Use cpm_muram_free() to free the allocation.
141 */
cpm_muram_alloc(unsigned long size,unsigned long align)142 unsigned long cpm_muram_alloc(unsigned long size, unsigned long align)
143 {
144 unsigned long start;
145 unsigned long flags;
146
147 spin_lock_irqsave(&cpm_muram_lock, flags);
148 cpm_muram_info.alignment = align;
149 start = rh_alloc(&cpm_muram_info, size, "commproc");
150 if (!IS_ERR_VALUE(start))
151 memset_io(cpm_muram_addr(start), 0, size);
152 spin_unlock_irqrestore(&cpm_muram_lock, flags);
153
154 return start;
155 }
156 EXPORT_SYMBOL(cpm_muram_alloc);
157
158 /**
159 * cpm_muram_free - free a chunk of multi-user ram
160 * @offset: The beginning of the chunk as returned by cpm_muram_alloc().
161 */
cpm_muram_free(unsigned long offset)162 int cpm_muram_free(unsigned long offset)
163 {
164 int ret;
165 unsigned long flags;
166
167 spin_lock_irqsave(&cpm_muram_lock, flags);
168 ret = rh_free(&cpm_muram_info, offset);
169 spin_unlock_irqrestore(&cpm_muram_lock, flags);
170
171 return ret;
172 }
173 EXPORT_SYMBOL(cpm_muram_free);
174
175 /**
176 * cpm_muram_alloc_fixed - reserve a specific region of multi-user ram
177 * @offset: the offset into the muram area to reserve
178 * @size: the number of bytes to reserve
179 *
180 * This function returns "start" on success, -ENOMEM on failure.
181 * Use cpm_dpram_addr() to get the virtual address of the area.
182 * Use cpm_muram_free() to free the allocation.
183 */
cpm_muram_alloc_fixed(unsigned long offset,unsigned long size)184 unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size)
185 {
186 unsigned long start;
187 unsigned long flags;
188
189 spin_lock_irqsave(&cpm_muram_lock, flags);
190 cpm_muram_info.alignment = 1;
191 start = rh_alloc_fixed(&cpm_muram_info, offset, size, "commproc");
192 spin_unlock_irqrestore(&cpm_muram_lock, flags);
193
194 return start;
195 }
196 EXPORT_SYMBOL(cpm_muram_alloc_fixed);
197
198 /**
199 * cpm_muram_addr - turn a muram offset into a virtual address
200 * @offset: muram offset to convert
201 */
cpm_muram_addr(unsigned long offset)202 void __iomem *cpm_muram_addr(unsigned long offset)
203 {
204 return muram_vbase + offset;
205 }
206 EXPORT_SYMBOL(cpm_muram_addr);
207
cpm_muram_offset(void __iomem * addr)208 unsigned long cpm_muram_offset(void __iomem *addr)
209 {
210 return addr - (void __iomem *)muram_vbase;
211 }
212 EXPORT_SYMBOL(cpm_muram_offset);
213
214 /**
215 * cpm_muram_dma - turn a muram virtual address into a DMA address
216 * @offset: virtual address from cpm_muram_addr() to convert
217 */
cpm_muram_dma(void __iomem * addr)218 dma_addr_t cpm_muram_dma(void __iomem *addr)
219 {
220 return muram_pbase + ((u8 __iomem *)addr - muram_vbase);
221 }
222 EXPORT_SYMBOL(cpm_muram_dma);
223
224 #if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
225
226 struct cpm2_ioports {
227 u32 dir, par, sor, odr, dat;
228 u32 res[3];
229 };
230
231 struct cpm2_gpio32_chip {
232 struct of_mm_gpio_chip mm_gc;
233 spinlock_t lock;
234
235 /* shadowed data register to clear/set bits safely */
236 u32 cpdata;
237 };
238
239 static inline struct cpm2_gpio32_chip *
to_cpm2_gpio32_chip(struct of_mm_gpio_chip * mm_gc)240 to_cpm2_gpio32_chip(struct of_mm_gpio_chip *mm_gc)
241 {
242 return container_of(mm_gc, struct cpm2_gpio32_chip, mm_gc);
243 }
244
cpm2_gpio32_save_regs(struct of_mm_gpio_chip * mm_gc)245 static void cpm2_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
246 {
247 struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
248 struct cpm2_ioports __iomem *iop = mm_gc->regs;
249
250 cpm2_gc->cpdata = in_be32(&iop->dat);
251 }
252
cpm2_gpio32_get(struct gpio_chip * gc,unsigned int gpio)253 static int cpm2_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
254 {
255 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
256 struct cpm2_ioports __iomem *iop = mm_gc->regs;
257 u32 pin_mask;
258
259 pin_mask = 1 << (31 - gpio);
260
261 return !!(in_be32(&iop->dat) & pin_mask);
262 }
263
__cpm2_gpio32_set(struct of_mm_gpio_chip * mm_gc,u32 pin_mask,int value)264 static void __cpm2_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask,
265 int value)
266 {
267 struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
268 struct cpm2_ioports __iomem *iop = mm_gc->regs;
269
270 if (value)
271 cpm2_gc->cpdata |= pin_mask;
272 else
273 cpm2_gc->cpdata &= ~pin_mask;
274
275 out_be32(&iop->dat, cpm2_gc->cpdata);
276 }
277
cpm2_gpio32_set(struct gpio_chip * gc,unsigned int gpio,int value)278 static void cpm2_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
279 {
280 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
281 struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
282 unsigned long flags;
283 u32 pin_mask = 1 << (31 - gpio);
284
285 spin_lock_irqsave(&cpm2_gc->lock, flags);
286
287 __cpm2_gpio32_set(mm_gc, pin_mask, value);
288
289 spin_unlock_irqrestore(&cpm2_gc->lock, flags);
290 }
291
cpm2_gpio32_dir_out(struct gpio_chip * gc,unsigned int gpio,int val)292 static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
293 {
294 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
295 struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
296 struct cpm2_ioports __iomem *iop = mm_gc->regs;
297 unsigned long flags;
298 u32 pin_mask = 1 << (31 - gpio);
299
300 spin_lock_irqsave(&cpm2_gc->lock, flags);
301
302 setbits32(&iop->dir, pin_mask);
303 __cpm2_gpio32_set(mm_gc, pin_mask, val);
304
305 spin_unlock_irqrestore(&cpm2_gc->lock, flags);
306
307 return 0;
308 }
309
cpm2_gpio32_dir_in(struct gpio_chip * gc,unsigned int gpio)310 static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
311 {
312 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
313 struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
314 struct cpm2_ioports __iomem *iop = mm_gc->regs;
315 unsigned long flags;
316 u32 pin_mask = 1 << (31 - gpio);
317
318 spin_lock_irqsave(&cpm2_gc->lock, flags);
319
320 clrbits32(&iop->dir, pin_mask);
321
322 spin_unlock_irqrestore(&cpm2_gc->lock, flags);
323
324 return 0;
325 }
326
cpm2_gpiochip_add32(struct device_node * np)327 int cpm2_gpiochip_add32(struct device_node *np)
328 {
329 struct cpm2_gpio32_chip *cpm2_gc;
330 struct of_mm_gpio_chip *mm_gc;
331 struct gpio_chip *gc;
332
333 cpm2_gc = kzalloc(sizeof(*cpm2_gc), GFP_KERNEL);
334 if (!cpm2_gc)
335 return -ENOMEM;
336
337 spin_lock_init(&cpm2_gc->lock);
338
339 mm_gc = &cpm2_gc->mm_gc;
340 gc = &mm_gc->gc;
341
342 mm_gc->save_regs = cpm2_gpio32_save_regs;
343 gc->ngpio = 32;
344 gc->direction_input = cpm2_gpio32_dir_in;
345 gc->direction_output = cpm2_gpio32_dir_out;
346 gc->get = cpm2_gpio32_get;
347 gc->set = cpm2_gpio32_set;
348
349 return of_mm_gpiochip_add(np, mm_gc);
350 }
351 #endif /* CONFIG_CPM2 || CONFIG_8xx_GPIO */
352