| /arch/arm64/include/asm/ |
| D | sysreg.h | 37 #define sys_reg(op0, op1, crn, crm, op2) \ macro
40 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
41 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
42 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
44 #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0)
45 #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1)
46 #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
47 #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4)
48 #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5)
49 #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6)
[all …]
|
| D | arch_gicv3.h | 23 #define ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
24 #define ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
25 #define ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
26 #define ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
27 #define ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
28 #define ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
29 #define ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
30 #define ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
32 #define ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
37 #define ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
[all …]
|
| D | cpufeature.h | 95 u32 sys_reg; member
|
| /arch/arm64/kernel/ |
| D | cpufeature.c | 397 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new) in init_cpu_ftr_reg() argument
402 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); in init_cpu_ftr_reg()
628 val = read_system_reg(entry->sys_reg); in has_cpuid_feature()
697 .sys_reg = SYS_ID_AA64PFR0_EL1,
707 .sys_reg = SYS_ID_AA64MMFR1_EL1,
719 .sys_reg = SYS_ID_AA64ISAR0_EL1,
735 .sys_reg = SYS_ID_AA64MMFR2_EL1,
757 .sys_reg = SYS_ID_AA64PFR0_EL1,
769 .sys_reg = reg, \
989 if (!cpus_have_cap(caps[i].capability) || !caps[i].sys_reg) in verify_local_cpu_capabilities()
[all …]
|
| /arch/arm/boot/dts/ |
| D | tegra20-tamonten.dtsi | 340 vin-sm0-supply = <&sys_reg>;
341 vin-sm1-supply = <&sys_reg>;
342 vin-sm2-supply = <&sys_reg>;
350 sys_reg: sys { label
|
| D | tegra20-colibri-512.dtsi | 242 vin-sm0-supply = <&sys_reg>;
243 vin-sm1-supply = <&sys_reg>;
244 vin-sm2-supply = <&sys_reg>;
255 sys_reg: regulator@0 { label
|
| D | tegra20-paz00.dts | 320 vin-sm0-supply = <&sys_reg>;
321 vin-sm1-supply = <&sys_reg>;
322 vin-sm2-supply = <&sys_reg>;
330 sys_reg: sys { label
|
| D | exynos4.dtsi | 148 sys_reg: syscon@10010000 { label
191 samsung,sysreg = <&sys_reg>;
203 samsung,sysreg = <&sys_reg>;
215 samsung,sysreg = <&sys_reg>;
227 samsung,sysreg = <&sys_reg>;
698 samsung,sysreg = <&sys_reg>;
|
| D | tegra20-ventana.dts | 402 vin-sm0-supply = <&sys_reg>;
403 vin-sm1-supply = <&sys_reg>;
404 vin-sm2-supply = <&sys_reg>;
412 sys_reg: sys { label
|
| D | tegra20-harmony.dts | 322 vin-sm0-supply = <&sys_reg>;
323 vin-sm1-supply = <&sys_reg>;
324 vin-sm2-supply = <&sys_reg>;
332 sys_reg: sys { label
|
| D | tegra20-seaboard.dts | 427 vin-sm0-supply = <&sys_reg>;
428 vin-sm1-supply = <&sys_reg>;
429 vin-sm2-supply = <&sys_reg>;
437 sys_reg: sys { label
|
| D | exynos3250.dtsi | 142 sys_reg: syscon@10010000 { label
298 samsung,sysreg = <&sys_reg>;
|
| D | exynos4x12.dtsi | 297 samsung,sysreg-phandle = <&sys_reg>;
|