1/* 2 * Samsung's Exynos3250 SoC device tree source 3 * 4 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * 7 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250 8 * based board files can include this file and provide values for board specfic 9 * bindings. 10 * 11 * Note: This file does not include device nodes for all the controllers in 12 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional 13 * nodes can be added to this file. 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License version 2 as 17 * published by the Free Software Foundation. 18 */ 19 20#include "skeleton.dtsi" 21#include "exynos4-cpu-thermal.dtsi" 22#include <dt-bindings/clock/exynos3250.h> 23 24/ { 25 compatible = "samsung,exynos3250"; 26 interrupt-parent = <&gic>; 27 28 aliases { 29 pinctrl0 = &pinctrl_0; 30 pinctrl1 = &pinctrl_1; 31 mshc0 = &mshc_0; 32 mshc1 = &mshc_1; 33 spi0 = &spi_0; 34 spi1 = &spi_1; 35 i2c0 = &i2c_0; 36 i2c1 = &i2c_1; 37 i2c2 = &i2c_2; 38 i2c3 = &i2c_3; 39 i2c4 = &i2c_4; 40 i2c5 = &i2c_5; 41 i2c6 = &i2c_6; 42 i2c7 = &i2c_7; 43 serial0 = &serial_0; 44 serial1 = &serial_1; 45 }; 46 47 cpus { 48 #address-cells = <1>; 49 #size-cells = <0>; 50 51 cpu0: cpu@0 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a7"; 54 reg = <0>; 55 clock-frequency = <1000000000>; 56 clocks = <&cmu CLK_ARM_CLK>; 57 clock-names = "cpu"; 58 #cooling-cells = <2>; 59 60 operating-points = < 61 1000000 1150000 62 900000 1112500 63 800000 1075000 64 700000 1037500 65 600000 1000000 66 500000 962500 67 400000 925000 68 300000 887500 69 200000 850000 70 100000 850000 71 >; 72 }; 73 74 cpu1: cpu@1 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a7"; 77 reg = <1>; 78 clock-frequency = <1000000000>; 79 }; 80 }; 81 82 soc: soc { 83 compatible = "simple-bus"; 84 #address-cells = <1>; 85 #size-cells = <1>; 86 ranges; 87 88 fixed-rate-clocks { 89 #address-cells = <1>; 90 #size-cells = <0>; 91 92 xusbxti: clock@0 { 93 compatible = "fixed-clock"; 94 #address-cells = <1>; 95 #size-cells = <0>; 96 reg = <0>; 97 clock-frequency = <0>; 98 #clock-cells = <0>; 99 clock-output-names = "xusbxti"; 100 }; 101 102 xxti: clock@1 { 103 compatible = "fixed-clock"; 104 reg = <1>; 105 clock-frequency = <0>; 106 #clock-cells = <0>; 107 clock-output-names = "xxti"; 108 }; 109 110 xtcxo: clock@2 { 111 compatible = "fixed-clock"; 112 reg = <2>; 113 clock-frequency = <0>; 114 #clock-cells = <0>; 115 clock-output-names = "xtcxo"; 116 }; 117 }; 118 119 sysram@02020000 { 120 compatible = "mmio-sram"; 121 reg = <0x02020000 0x40000>; 122 #address-cells = <1>; 123 #size-cells = <1>; 124 ranges = <0 0x02020000 0x40000>; 125 126 smp-sysram@0 { 127 compatible = "samsung,exynos4210-sysram"; 128 reg = <0x0 0x1000>; 129 }; 130 131 smp-sysram@3f000 { 132 compatible = "samsung,exynos4210-sysram-ns"; 133 reg = <0x3f000 0x1000>; 134 }; 135 }; 136 137 chipid@10000000 { 138 compatible = "samsung,exynos4210-chipid"; 139 reg = <0x10000000 0x100>; 140 }; 141 142 sys_reg: syscon@10010000 { 143 compatible = "samsung,exynos3-sysreg", "syscon"; 144 reg = <0x10010000 0x400>; 145 }; 146 147 pmu_system_controller: system-controller@10020000 { 148 compatible = "samsung,exynos3250-pmu", "syscon"; 149 reg = <0x10020000 0x4000>; 150 interrupt-controller; 151 #interrupt-cells = <3>; 152 interrupt-parent = <&gic>; 153 clock-names = "clkout8"; 154 clocks = <&cmu CLK_FIN_PLL>; 155 #clock-cells = <1>; 156 }; 157 158 mipi_phy: video-phy@10020710 { 159 compatible = "samsung,s5pv210-mipi-video-phy"; 160 #phy-cells = <1>; 161 syscon = <&pmu_system_controller>; 162 }; 163 164 pd_cam: cam-power-domain@10023C00 { 165 compatible = "samsung,exynos4210-pd"; 166 reg = <0x10023C00 0x20>; 167 #power-domain-cells = <0>; 168 }; 169 170 pd_mfc: mfc-power-domain@10023C40 { 171 compatible = "samsung,exynos4210-pd"; 172 reg = <0x10023C40 0x20>; 173 #power-domain-cells = <0>; 174 }; 175 176 pd_g3d: g3d-power-domain@10023C60 { 177 compatible = "samsung,exynos4210-pd"; 178 reg = <0x10023C60 0x20>; 179 #power-domain-cells = <0>; 180 }; 181 182 pd_lcd0: lcd0-power-domain@10023C80 { 183 compatible = "samsung,exynos4210-pd"; 184 reg = <0x10023C80 0x20>; 185 #power-domain-cells = <0>; 186 }; 187 188 pd_isp: isp-power-domain@10023CA0 { 189 compatible = "samsung,exynos4210-pd"; 190 reg = <0x10023CA0 0x20>; 191 #power-domain-cells = <0>; 192 }; 193 194 cmu: clock-controller@10030000 { 195 compatible = "samsung,exynos3250-cmu"; 196 reg = <0x10030000 0x20000>; 197 #clock-cells = <1>; 198 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>, 199 <&cmu CLK_MOUT_ACLK_266_SUB>; 200 assigned-clock-parents = <&cmu CLK_FIN_PLL>, 201 <&cmu CLK_FIN_PLL>; 202 }; 203 204 cmu_dmc: clock-controller@105C0000 { 205 compatible = "samsung,exynos3250-cmu-dmc"; 206 reg = <0x105C0000 0x2000>; 207 #clock-cells = <1>; 208 }; 209 210 rtc: rtc@10070000 { 211 compatible = "samsung,s3c6410-rtc"; 212 reg = <0x10070000 0x100>; 213 interrupts = <0 73 0>, <0 74 0>; 214 interrupt-parent = <&pmu_system_controller>; 215 status = "disabled"; 216 }; 217 218 tmu: tmu@100C0000 { 219 compatible = "samsung,exynos3250-tmu"; 220 reg = <0x100C0000 0x100>; 221 interrupts = <0 216 0>; 222 clocks = <&cmu CLK_TMU_APBIF>; 223 clock-names = "tmu_apbif"; 224 #include "exynos4412-tmu-sensor-conf.dtsi" 225 status = "disabled"; 226 }; 227 228 gic: interrupt-controller@10481000 { 229 compatible = "arm,cortex-a15-gic"; 230 #interrupt-cells = <3>; 231 interrupt-controller; 232 reg = <0x10481000 0x1000>, 233 <0x10482000 0x1000>, 234 <0x10484000 0x2000>, 235 <0x10486000 0x2000>; 236 interrupts = <1 9 0xf04>; 237 }; 238 239 mct@10050000 { 240 compatible = "samsung,exynos4210-mct"; 241 reg = <0x10050000 0x800>; 242 interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>, 243 <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>; 244 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>; 245 clock-names = "fin_pll", "mct"; 246 }; 247 248 pinctrl_1: pinctrl@11000000 { 249 compatible = "samsung,exynos3250-pinctrl"; 250 reg = <0x11000000 0x1000>; 251 interrupts = <0 225 0>; 252 253 wakeup-interrupt-controller { 254 compatible = "samsung,exynos4210-wakeup-eint"; 255 interrupts = <0 48 0>; 256 }; 257 }; 258 259 pinctrl_0: pinctrl@11400000 { 260 compatible = "samsung,exynos3250-pinctrl"; 261 reg = <0x11400000 0x1000>; 262 interrupts = <0 240 0>; 263 }; 264 265 jpeg: codec@11830000 { 266 compatible = "samsung,exynos3250-jpeg"; 267 reg = <0x11830000 0x1000>; 268 interrupts = <0 171 0>; 269 clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>; 270 clock-names = "jpeg", "sclk"; 271 power-domains = <&pd_cam>; 272 assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>; 273 assigned-clock-rates = <0>, <150000000>; 274 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>; 275 iommus = <&sysmmu_jpeg>; 276 status = "disabled"; 277 }; 278 279 sysmmu_jpeg: sysmmu@11A60000 { 280 compatible = "samsung,exynos-sysmmu"; 281 reg = <0x11a60000 0x1000>; 282 interrupts = <0 156 0>, <0 161 0>; 283 clock-names = "sysmmu", "master"; 284 clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>; 285 power-domains = <&pd_cam>; 286 #iommu-cells = <0>; 287 }; 288 289 fimd: fimd@11c00000 { 290 compatible = "samsung,exynos3250-fimd"; 291 reg = <0x11c00000 0x30000>; 292 interrupt-names = "fifo", "vsync", "lcd_sys"; 293 interrupts = <0 84 0>, <0 85 0>, <0 86 0>; 294 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; 295 clock-names = "sclk_fimd", "fimd"; 296 power-domains = <&pd_lcd0>; 297 iommus = <&sysmmu_fimd0>; 298 samsung,sysreg = <&sys_reg>; 299 status = "disabled"; 300 }; 301 302 dsi_0: dsi@11C80000 { 303 compatible = "samsung,exynos3250-mipi-dsi"; 304 reg = <0x11C80000 0x10000>; 305 interrupts = <0 83 0>; 306 samsung,phy-type = <0>; 307 power-domains = <&pd_lcd0>; 308 phys = <&mipi_phy 1>; 309 phy-names = "dsim"; 310 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>; 311 clock-names = "bus_clk", "pll_clk"; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 status = "disabled"; 315 }; 316 317 sysmmu_fimd0: sysmmu@11E20000 { 318 compatible = "samsung,exynos-sysmmu"; 319 reg = <0x11e20000 0x1000>; 320 interrupts = <0 80 0>, <0 81 0>; 321 clock-names = "sysmmu", "master"; 322 clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>; 323 power-domains = <&pd_lcd0>; 324 #iommu-cells = <0>; 325 }; 326 327 hsotg: hsotg@12480000 { 328 compatible = "samsung,s3c6400-hsotg", "snps,dwc2"; 329 reg = <0x12480000 0x20000>; 330 interrupts = <0 141 0>; 331 clocks = <&cmu CLK_USBOTG>; 332 clock-names = "otg"; 333 phys = <&exynos_usbphy 0>; 334 phy-names = "usb2-phy"; 335 status = "disabled"; 336 }; 337 338 mshc_0: mshc@12510000 { 339 compatible = "samsung,exynos5420-dw-mshc"; 340 reg = <0x12510000 0x1000>; 341 interrupts = <0 142 0>; 342 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>; 343 clock-names = "biu", "ciu"; 344 fifo-depth = <0x80>; 345 #address-cells = <1>; 346 #size-cells = <0>; 347 status = "disabled"; 348 }; 349 350 mshc_1: mshc@12520000 { 351 compatible = "samsung,exynos5420-dw-mshc"; 352 reg = <0x12520000 0x1000>; 353 interrupts = <0 143 0>; 354 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>; 355 clock-names = "biu", "ciu"; 356 fifo-depth = <0x80>; 357 #address-cells = <1>; 358 #size-cells = <0>; 359 status = "disabled"; 360 }; 361 362 exynos_usbphy: exynos-usbphy@125B0000 { 363 compatible = "samsung,exynos3250-usb2-phy"; 364 reg = <0x125B0000 0x100>; 365 samsung,pmureg-phandle = <&pmu_system_controller>; 366 clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>; 367 clock-names = "phy", "ref"; 368 #phy-cells = <1>; 369 status = "disabled"; 370 }; 371 372 amba { 373 compatible = "arm,amba-bus"; 374 #address-cells = <1>; 375 #size-cells = <1>; 376 ranges; 377 378 pdma0: pdma@12680000 { 379 compatible = "arm,pl330", "arm,primecell"; 380 reg = <0x12680000 0x1000>; 381 interrupts = <0 138 0>; 382 clocks = <&cmu CLK_PDMA0>; 383 clock-names = "apb_pclk"; 384 #dma-cells = <1>; 385 #dma-channels = <8>; 386 #dma-requests = <32>; 387 }; 388 389 pdma1: pdma@12690000 { 390 compatible = "arm,pl330", "arm,primecell"; 391 reg = <0x12690000 0x1000>; 392 interrupts = <0 139 0>; 393 clocks = <&cmu CLK_PDMA1>; 394 clock-names = "apb_pclk"; 395 #dma-cells = <1>; 396 #dma-channels = <8>; 397 #dma-requests = <32>; 398 }; 399 }; 400 401 adc: adc@126C0000 { 402 compatible = "samsung,exynos3250-adc", 403 "samsung,exynos-adc-v2"; 404 reg = <0x126C0000 0x100>; 405 interrupts = <0 137 0>; 406 clock-names = "adc", "sclk"; 407 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; 408 #io-channel-cells = <1>; 409 io-channel-ranges; 410 samsung,syscon-phandle = <&pmu_system_controller>; 411 status = "disabled"; 412 }; 413 414 mfc: codec@13400000 { 415 compatible = "samsung,mfc-v7"; 416 reg = <0x13400000 0x10000>; 417 interrupts = <0 102 0>; 418 clock-names = "mfc", "sclk_mfc"; 419 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>; 420 power-domains = <&pd_mfc>; 421 iommus = <&sysmmu_mfc>; 422 status = "disabled"; 423 }; 424 425 sysmmu_mfc: sysmmu@13620000 { 426 compatible = "samsung,exynos-sysmmu"; 427 reg = <0x13620000 0x1000>; 428 interrupts = <0 96 0>, <0 98 0>; 429 clock-names = "sysmmu", "master"; 430 clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>; 431 power-domains = <&pd_mfc>; 432 #iommu-cells = <0>; 433 }; 434 435 serial_0: serial@13800000 { 436 compatible = "samsung,exynos4210-uart"; 437 reg = <0x13800000 0x100>; 438 interrupts = <0 109 0>; 439 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; 440 clock-names = "uart", "clk_uart_baud0"; 441 pinctrl-names = "default"; 442 pinctrl-0 = <&uart0_data &uart0_fctl>; 443 status = "disabled"; 444 }; 445 446 serial_1: serial@13810000 { 447 compatible = "samsung,exynos4210-uart"; 448 reg = <0x13810000 0x100>; 449 interrupts = <0 110 0>; 450 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; 451 clock-names = "uart", "clk_uart_baud0"; 452 pinctrl-names = "default"; 453 pinctrl-0 = <&uart1_data>; 454 status = "disabled"; 455 }; 456 457 i2c_0: i2c@13860000 { 458 #address-cells = <1>; 459 #size-cells = <0>; 460 compatible = "samsung,s3c2440-i2c"; 461 reg = <0x13860000 0x100>; 462 interrupts = <0 113 0>; 463 clocks = <&cmu CLK_I2C0>; 464 clock-names = "i2c"; 465 pinctrl-names = "default"; 466 pinctrl-0 = <&i2c0_bus>; 467 status = "disabled"; 468 }; 469 470 i2c_1: i2c@13870000 { 471 #address-cells = <1>; 472 #size-cells = <0>; 473 compatible = "samsung,s3c2440-i2c"; 474 reg = <0x13870000 0x100>; 475 interrupts = <0 114 0>; 476 clocks = <&cmu CLK_I2C1>; 477 clock-names = "i2c"; 478 pinctrl-names = "default"; 479 pinctrl-0 = <&i2c1_bus>; 480 status = "disabled"; 481 }; 482 483 i2c_2: i2c@13880000 { 484 #address-cells = <1>; 485 #size-cells = <0>; 486 compatible = "samsung,s3c2440-i2c"; 487 reg = <0x13880000 0x100>; 488 interrupts = <0 115 0>; 489 clocks = <&cmu CLK_I2C2>; 490 clock-names = "i2c"; 491 pinctrl-names = "default"; 492 pinctrl-0 = <&i2c2_bus>; 493 status = "disabled"; 494 }; 495 496 i2c_3: i2c@13890000 { 497 #address-cells = <1>; 498 #size-cells = <0>; 499 compatible = "samsung,s3c2440-i2c"; 500 reg = <0x13890000 0x100>; 501 interrupts = <0 116 0>; 502 clocks = <&cmu CLK_I2C3>; 503 clock-names = "i2c"; 504 pinctrl-names = "default"; 505 pinctrl-0 = <&i2c3_bus>; 506 status = "disabled"; 507 }; 508 509 i2c_4: i2c@138A0000 { 510 #address-cells = <1>; 511 #size-cells = <0>; 512 compatible = "samsung,s3c2440-i2c"; 513 reg = <0x138A0000 0x100>; 514 interrupts = <0 117 0>; 515 clocks = <&cmu CLK_I2C4>; 516 clock-names = "i2c"; 517 pinctrl-names = "default"; 518 pinctrl-0 = <&i2c4_bus>; 519 status = "disabled"; 520 }; 521 522 i2c_5: i2c@138B0000 { 523 #address-cells = <1>; 524 #size-cells = <0>; 525 compatible = "samsung,s3c2440-i2c"; 526 reg = <0x138B0000 0x100>; 527 interrupts = <0 118 0>; 528 clocks = <&cmu CLK_I2C5>; 529 clock-names = "i2c"; 530 pinctrl-names = "default"; 531 pinctrl-0 = <&i2c5_bus>; 532 status = "disabled"; 533 }; 534 535 i2c_6: i2c@138C0000 { 536 #address-cells = <1>; 537 #size-cells = <0>; 538 compatible = "samsung,s3c2440-i2c"; 539 reg = <0x138C0000 0x100>; 540 interrupts = <0 119 0>; 541 clocks = <&cmu CLK_I2C6>; 542 clock-names = "i2c"; 543 pinctrl-names = "default"; 544 pinctrl-0 = <&i2c6_bus>; 545 status = "disabled"; 546 }; 547 548 i2c_7: i2c@138D0000 { 549 #address-cells = <1>; 550 #size-cells = <0>; 551 compatible = "samsung,s3c2440-i2c"; 552 reg = <0x138D0000 0x100>; 553 interrupts = <0 120 0>; 554 clocks = <&cmu CLK_I2C7>; 555 clock-names = "i2c"; 556 pinctrl-names = "default"; 557 pinctrl-0 = <&i2c7_bus>; 558 status = "disabled"; 559 }; 560 561 spi_0: spi@13920000 { 562 compatible = "samsung,exynos4210-spi"; 563 reg = <0x13920000 0x100>; 564 interrupts = <0 121 0>; 565 dmas = <&pdma0 7>, <&pdma0 6>; 566 dma-names = "tx", "rx"; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>; 570 clock-names = "spi", "spi_busclk0"; 571 samsung,spi-src-clk = <0>; 572 pinctrl-names = "default"; 573 pinctrl-0 = <&spi0_bus>; 574 status = "disabled"; 575 }; 576 577 spi_1: spi@13930000 { 578 compatible = "samsung,exynos4210-spi"; 579 reg = <0x13930000 0x100>; 580 interrupts = <0 122 0>; 581 dmas = <&pdma1 7>, <&pdma1 6>; 582 dma-names = "tx", "rx"; 583 #address-cells = <1>; 584 #size-cells = <0>; 585 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>; 586 clock-names = "spi", "spi_busclk0"; 587 samsung,spi-src-clk = <0>; 588 pinctrl-names = "default"; 589 pinctrl-0 = <&spi1_bus>; 590 status = "disabled"; 591 }; 592 593 i2s2: i2s@13970000 { 594 compatible = "samsung,s3c6410-i2s"; 595 reg = <0x13970000 0x100>; 596 interrupts = <0 126 0>; 597 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>; 598 clock-names = "iis", "i2s_opclk0"; 599 dmas = <&pdma0 14>, <&pdma0 13>; 600 dma-names = "tx", "rx"; 601 pinctrl-0 = <&i2s2_bus>; 602 pinctrl-names = "default"; 603 status = "disabled"; 604 }; 605 606 pwm: pwm@139D0000 { 607 compatible = "samsung,exynos4210-pwm"; 608 reg = <0x139D0000 0x1000>; 609 interrupts = <0 104 0>, <0 105 0>, <0 106 0>, 610 <0 107 0>, <0 108 0>; 611 #pwm-cells = <3>; 612 status = "disabled"; 613 }; 614 615 pmu { 616 compatible = "arm,cortex-a7-pmu"; 617 interrupts = <0 18 0>, <0 19 0>; 618 }; 619 620 ppmu_dmc0: ppmu_dmc0@106a0000 { 621 compatible = "samsung,exynos-ppmu"; 622 reg = <0x106a0000 0x2000>; 623 status = "disabled"; 624 }; 625 626 ppmu_dmc1: ppmu_dmc1@106b0000 { 627 compatible = "samsung,exynos-ppmu"; 628 reg = <0x106b0000 0x2000>; 629 status = "disabled"; 630 }; 631 632 ppmu_cpu: ppmu_cpu@106c0000 { 633 compatible = "samsung,exynos-ppmu"; 634 reg = <0x106c0000 0x2000>; 635 status = "disabled"; 636 }; 637 638 ppmu_rightbus: ppmu_rightbus@112a0000 { 639 compatible = "samsung,exynos-ppmu"; 640 reg = <0x112a0000 0x2000>; 641 clocks = <&cmu CLK_PPMURIGHT>; 642 clock-names = "ppmu"; 643 status = "disabled"; 644 }; 645 646 ppmu_leftbus: ppmu_leftbus0@116a0000 { 647 compatible = "samsung,exynos-ppmu"; 648 reg = <0x116a0000 0x2000>; 649 clocks = <&cmu CLK_PPMULEFT>; 650 clock-names = "ppmu"; 651 status = "disabled"; 652 }; 653 654 ppmu_camif: ppmu_camif@11ac0000 { 655 compatible = "samsung,exynos-ppmu"; 656 reg = <0x11ac0000 0x2000>; 657 clocks = <&cmu CLK_PPMUCAMIF>; 658 clock-names = "ppmu"; 659 status = "disabled"; 660 }; 661 662 ppmu_lcd0: ppmu_lcd0@11e40000 { 663 compatible = "samsung,exynos-ppmu"; 664 reg = <0x11e40000 0x2000>; 665 clocks = <&cmu CLK_PPMULCD0>; 666 clock-names = "ppmu"; 667 status = "disabled"; 668 }; 669 670 ppmu_fsys: ppmu_fsys@12630000 { 671 compatible = "samsung,exynos-ppmu"; 672 reg = <0x12630000 0x2000>; 673 clocks = <&cmu CLK_PPMUFILE>; 674 clock-names = "ppmu"; 675 status = "disabled"; 676 }; 677 678 ppmu_g3d: ppmu_g3d@13220000 { 679 compatible = "samsung,exynos-ppmu"; 680 reg = <0x13220000 0x2000>; 681 clocks = <&cmu CLK_PPMUG3D>; 682 clock-names = "ppmu"; 683 status = "disabled"; 684 }; 685 686 ppmu_mfc: ppmu_mfc@13660000 { 687 compatible = "samsung,exynos-ppmu"; 688 reg = <0x13660000 0x2000>; 689 clocks = <&cmu CLK_PPMUMFC_L>; 690 clock-names = "ppmu"; 691 status = "disabled"; 692 }; 693 }; 694}; 695 696#include "exynos3250-pinctrl.dtsi" 697