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Searched refs:BIT5 (Results 1 – 22 of 22) sorted by relevance

/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h110 #define EPROM_CMD_RESERVED_MASK BIT5
140 #define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \
155 #define RCR_ACRC32 BIT5
192 #define CAM_USEDK BIT5
216 #define SCR_NoSKMC BIT5
233 #define IMR_HCCADOK BIT5
246 #define TPPoll_CQ BIT5
286 #define AcmHw_ViqStatus BIT5
376 #define RRSR_9M BIT5
/drivers/scsi/
Ddc395x.h70 #define BIT5 0x00000020 macro
133 #define SRB_ERROR BIT5
138 #define RESIDUAL_VALID BIT5
178 #define EN_TAG_QUEUEING BIT5
634 #define LUN_CHECK BIT5
/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
Dpwrseq.h284 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
405 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0 \
438 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4) \
488 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
641 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
/drivers/video/fbdev/via/
Ddvi.c76 BIT5 + BIT6 + BIT7); in viafb_tmds_trasmitter_identify()
80 viafb_write_reg_mask(SR3E, VIASR, 0x0, BIT5); in viafb_tmds_trasmitter_identify()
410 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5); in viafb_dvi_enable()
422 viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5); in viafb_dvi_enable()
Dhw.c1711 viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5); in device_screen_off()
1717 viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5); in device_screen_on()
1728 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); in set_display_channel()
1732 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5); in set_display_channel()
1735 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5); in set_display_channel()
1740 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); in set_display_channel()
1743 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5); in set_display_channel()
2080 p_gfx_dpa_setting->DVP0DataDri_S1, BIT5); in viafb_set_dpa_gfx()
Dshare.h33 #define BIT5 0x20 macro
Dviafbdev.c1128 (viafb_read_reg(VIASR, SR2A) & BIT5) >> 4 | in viafb_dvp0_proc_show()
1170 reg_val << 4, BIT5); in viafb_dvp0_proc_write()
/drivers/net/wireless/realtek/rtlwifi/btcoexist/
Dhalbt_precomp.h53 #define BIT5 0x00000020 macro
Dhalbtc8723b2ant.h35 #define BT_INFO_8723B_2ANT_B_HID BIT5
Dhalbtc8821a2ant.h32 #define BT_INFO_8821A_2ANT_B_HID BIT5
Dhalbtc8723b1ant.h32 #define BT_INFO_8723B_1ANT_B_HID BIT5
Dhalbtc8192e2ant.h32 #define BT_INFO_8192E_2ANT_B_HID BIT5
Dhalbtc8821a1ant.h34 #define BT_INFO_8821A_1ANT_B_HID BIT5
Dhalbtcoutsrc.h106 #define ALGO_TRACE_FW_DETAIL BIT5
Dhalbtc8723b1ant.c884 if ((byte1 & BIT4) && !(byte1 & BIT5)) { in halbtc8723b1ant_set_fw_ps_tdma()
888 real_byte1 |= BIT5; in halbtc8723b1ant_set_fw_ps_tdma()
890 real_byte5 |= BIT5; in halbtc8723b1ant_set_fw_ps_tdma()
/drivers/staging/rtl8192e/
Drtl819x_Qos.h23 #define BIT5 0x00000020 macro
/drivers/tty/
Dsynclinkmp.c437 #define PE BIT5
438 #define ABT BIT5
2598 if (timerstatus0 & (BIT5 | BIT4)) in synclinkmp_interrupt()
2602 if (timerstatus1 & (BIT5 | BIT4)) in synclinkmp_interrupt()
4411 case 6: RegValue |= BIT5 + BIT3; break; in async_mode()
4412 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break; in async_mode()
4574 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break; in hdlc_mode()
4575 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */ in hdlc_mode()
4606 RegValue |= BIT6 + BIT5; in hdlc_mode()
4619 RegValue |= BIT6 + BIT5; in hdlc_mode()
[all …]
Dsynclink_gt.c422 #define IRQ_DCD BIT5
2220 if (status & (BIT5 + BIT4)) { in isr_rdma()
2245 if (status & (BIT5 + BIT4 + BIT3)) { in isr_tdma()
4159 case 7: val |= BIT5; break; in async_mode()
4160 case 8: val |= BIT5 + BIT4; break; in async_mode()
4199 case 7: val |= BIT5; break; in async_mode()
4200 case 8: val |= BIT5 + BIT4; break; in async_mode()
4323 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break; in sync_mode()
4325 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break; in sync_mode()
4411 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */ in sync_mode()
[all …]
Dsynclink.c491 #define RECEIVE_STATUS BIT5
507 #define RXSTATUS_BREAK_RECEIVED BIT5
508 #define RXSTATUS_ABORT_RECEIVED BIT5
547 #define TXSTATUS_ABORT_SENT BIT5
568 #define MISCSTATUS_CTS_LATCHED BIT5
593 #define SICR_CTS_ACTIVE BIT5
595 #define SICR_CTS (BIT5|BIT4)
628 #define TXSTATUS_ABORT_SENT BIT5
5918 RegValue |= BIT5; in usc_set_async_mode()
5975 RegValue |= BIT5; in usc_set_async_mode()
[all …]
/drivers/char/pcmcia/
Dsynclink_cs.c680 #define CMD_RXFIFO_READ BIT5
908 if (!fifo_count && (read_reg(info,CHA+STAR) & BIT5)) in rx_ready_async()
3027 val = read_reg(info, CHA + CCR2) | (BIT4 | BIT5); in loopback_enable()
3154 val |= BIT5; in hdlc_mode()
3179 val |= BIT5; in hdlc_mode()
3242 val |= BIT5; in hdlc_mode()
3516 val |= BIT5; in async_mode()
3559 val |= BIT5; in async_mode()
3684 else if (!(status & BIT5)) { in rx_get_frame()
3715 if (status & BIT5) in rx_get_frame()
[all …]
/drivers/net/wireless/realtek/rtlwifi/rtl8192de/
Dreg.h389 #define RRSR_9M BIT5
/drivers/scsi/lpfc/
Dlpfc_hw4.h679 #define LPFC_SLI4_INTR5 BIT5