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Searched refs:IS_GEN2 (Results 1 – 16 of 16) sorted by relevance

/drivers/gpu/drm/i915/
Di915_suspend.c125 if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) { in i915_save_state()
132 } else if (IS_GEN2(dev_priv)) { in i915_save_state()
172 if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) { in i915_restore_state()
179 } else if (IS_GEN2(dev_priv)) { in i915_restore_state()
Dintel_crt.c227 if (IS_GEN2(dev)) in intel_crt_mode_valid()
521 if (!IS_GEN2(dev)) { in intel_crt_load_detect()
823 if (IS_GEN2(dev)) in intel_crt_init()
Di915_gem_fence.c208 if (IS_GEN2(dev)) in i915_gem_write_fence()
601 } else if (IS_GEN2(dev)) { in i915_gem_detect_bit_6_swizzle()
Dintel_fbc.c102 if (IS_GEN2(dev_priv)) in i8xx_fbc_enable()
767 if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv)) in stride_is_valid()
791 if (IS_GEN2(dev)) in pixel_format_is_valid()
Di915_gem_tiling.c71 if (IS_GEN2(dev) || in i915_tiling_ok()
Dintel_overlay.c540 if (IS_GEN2(dev)) { in calc_swidthsw()
548 if (!IS_GEN2(dev)) in calc_swidthsw()
1309 if (!IS_GEN2(dev)) { in intel_overlay_attrs()
1341 if (IS_GEN2(dev)) in intel_overlay_attrs()
Di915_gpu_error.c794 if (IS_GEN3(dev) || IS_GEN2(dev)) { in i915_gem_record_fences()
1228 } else if (IS_GEN2(dev)) { in i915_capture_reg_state()
1390 if (IS_GEN2(dev) || IS_GEN3(dev)) in i915_get_extra_instdone()
Di915_irq.c735 if (IS_GEN2(dev)) in __intel_get_crtc_scanline()
820 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { in i915_get_crtc_scanoutpos()
882 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { in i915_get_crtc_scanoutpos()
2503 if (!IS_GEN2(dev)) { in i915_report_and_clear_eir()
2891 if (IS_GEN2(dev)) in ring_stuck()
4385 if (IS_GEN2(dev_priv)) { in intel_irq_init()
4401 if (!IS_GEN2(dev_priv)) in intel_irq_init()
Di915_dma.c918 mmio_bar = IS_GEN2(dev) ? 1 : 0; in i915_driver_load()
967 if (IS_GEN2(dev)) in i915_driver_load()
Dintel_ringbuffer.c548 if (!IS_GEN2(ring->dev)) { in stop_ring()
565 if (!IS_GEN2(ring->dev)) { in stop_ring()
2190 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0); in intel_cleanup_ring_buffer()
2742 if (IS_GEN2(dev)) { in intel_init_render_ring_buffer()
Dintel_display.c620 } else if (!IS_GEN2(dev)) { in intel_limit()
1103 if (IS_GEN2(dev)) in pipe_dsl_stopped()
2230 tile_height = IS_GEN2(dev) ? 16 : 8; in intel_tile_height()
3245 if (IS_GEN2(dev)) in intel_prepare_reset()
3272 if (IS_GEN2(dev)) in intel_finish_reset()
4748 if (IS_GEN2(dev)) in intel_post_enable_primary()
4780 if (IS_GEN2(dev)) in intel_pre_disable_primary()
6231 if (!IS_GEN2(dev)) in i9xx_crtc_enable()
6312 if (!IS_GEN2(dev)) in i9xx_crtc_disable()
7155 } else if (!IS_GEN2(dev)) { in i9xx_get_refclk()
[all …]
Dintel_panel.c975 if (IS_GEN2(dev)) in i9xx_enable_backlight()
1508 if (IS_GEN2(dev) || IS_I915GM(dev) || IS_I945GM(dev)) in i9xx_setup_backlight()
Dintel_pm.c1510 else if (!IS_GEN2(dev)) in i9xx_update_wm()
1520 if (IS_GEN2(dev)) in i9xx_update_wm()
1534 if (IS_GEN2(dev)) in i9xx_update_wm()
1542 if (IS_GEN2(dev)) in i9xx_update_wm()
7303 } else if (IS_GEN2(dev)) { in intel_init_pm()
Di915_drv.h2536 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) macro
2595 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
Di915_gem.c4793 } else if (IS_GEN2(dev)) { in init_unused_rings()
Di915_debugfs.c3891 if (IS_GEN2(dev)) in pipe_crc_set_source()