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Searched refs:NCHAN (Results 1 – 8 of 8) sorted by relevance

/drivers/net/ethernet/chelsio/cxgb4/
Dcxgb4.h259 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
402 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
403 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */
405 MAX_ISCSI_QUEUES = NCHAN, /* # of streaming iSCSI Rx queues */
727 u8 chan_map[NCHAN]; /* channel -> port map */
Dt4_hw.h41 NCHAN = 4, /* # of HW channels */ enumerator
Dcxgb4_uld.h261 unsigned short tx_modq[NCHAN]; /* maps each tx channel to a */
Dt4_hw.c5117 if (adap->params.arch.nchan == NCHAN) { in t4_get_chan_txrate()
5125 if (adap->params.arch.nchan == NCHAN) { in t4_get_chan_txrate()
7077 adapter->params.arch.nchan = NCHAN; in t4_prep_adapter()
7086 adapter->params.arch.nchan = NCHAN; in t4_prep_adapter()
7310 for (chan = 0; chan < NCHAN; chan++) in t4_init_tp_params()
Dcxgb4_debugfs.c804 u64 nrate[NCHAN], orate[NCHAN]; in tx_rate_show()
808 if (adap->params.arch.nchan == NCHAN) { in tx_rate_show()
Dcxgb4_main.c2466 for (i = 0; i < NCHAN; i++) in uld_attach()
/drivers/staging/dgap/
Ddgap.h220 #define NCHAN 0x0C02L /* number of ports FEP sees */ macro
Ddgap.c6673 true_count = readw((vaddr + NCHAN)); in dgap_tty_init()