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Searched refs:POSTING_READ (Results 1 – 25 of 28) sorted by relevance

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/drivers/gpu/drm/i915/
Di915_irq.c121 POSTING_READ(GEN8_##type##_IMR(which)); \
124 POSTING_READ(GEN8_##type##_IIR(which)); \
126 POSTING_READ(GEN8_##type##_IIR(which)); \
131 POSTING_READ(type##IMR); \
134 POSTING_READ(type##IIR); \
136 POSTING_READ(type##IIR); \
152 POSTING_READ(reg); in gen5_assert_iir_is_zero()
154 POSTING_READ(reg); in gen5_assert_iir_is_zero()
161 POSTING_READ(GEN8_##type##_IMR(which)); \
168 POSTING_READ(type##IMR); \
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Dintel_hdmi.c168 POSTING_READ(VIDEO_DIP_CTL); in g4x_write_infoframe()
223 POSTING_READ(reg); in ibx_write_infoframe()
284 POSTING_READ(reg); in cpt_write_infoframe()
338 POSTING_READ(reg); in vlv_write_infoframe()
396 POSTING_READ(ctl_reg); in hsw_write_infoframe()
544 POSTING_READ(reg); in g4x_set_infoframes()
563 POSTING_READ(reg); in g4x_set_infoframes()
685 POSTING_READ(reg); in ibx_set_infoframes()
706 POSTING_READ(reg); in ibx_set_infoframes()
735 POSTING_READ(reg); in cpt_set_infoframes()
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Di915_gem_fence.c85 POSTING_READ(fence_reg_lo); in i965_write_fence_reg()
107 POSTING_READ(fence_reg_hi); in i965_write_fence_reg()
110 POSTING_READ(fence_reg_lo); in i965_write_fence_reg()
113 POSTING_READ(fence_reg_hi); in i965_write_fence_reg()
153 POSTING_READ(FENCE_REG(reg)); in i915_write_fence_reg()
185 POSTING_READ(FENCE_REG(reg)); in i830_write_fence_reg()
Dintel_ddi.c630 POSTING_READ(FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
659 POSTING_READ(DDI_BUF_CTL(PORT_E)); in hsw_fdi_link_train()
669 POSTING_READ(FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
678 POSTING_READ(FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
700 POSTING_READ(DDI_BUF_CTL(PORT_E)); in hsw_fdi_link_train()
707 POSTING_READ(DP_TP_CTL(PORT_E)); in hsw_fdi_link_train()
713 POSTING_READ(FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
720 POSTING_READ(FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
2317 POSTING_READ(DPLL_CTRL1); in intel_ddi_pre_enable()
2465 POSTING_READ(WRPLL_CTL(pll->id)); in hsw_ddi_wrpll_enable()
[all …]
Dintel_fifo_underrun.c113 POSTING_READ(reg); in i9xx_check_fifo_underruns()
133 POSTING_READ(reg); in i9xx_set_fifo_underrun_reporting()
188 POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); in broadwell_set_fifo_underrun_reporting()
Dintel_sprite.c284 POSTING_READ(PLANE_SURF(pipe, plane)); in skl_update_plane()
299 POSTING_READ(PLANE_SURF(pipe, plane)); in skl_disable_plane()
465 POSTING_READ(SPSURF(pipe, plane)); in vlv_update_plane()
480 POSTING_READ(SPSURF(pipe, plane)); in vlv_disable_plane()
605 POSTING_READ(SPRSURF(pipe)); in ivb_update_plane()
622 POSTING_READ(SPRSURF(pipe)); in ivb_disable_plane()
734 POSTING_READ(DVSSURF(pipe)); in ilk_update_plane()
750 POSTING_READ(DVSSURF(pipe)); in ilk_disable_plane()
Dintel_runtime_pm.c281 POSTING_READ(HSW_PWR_WELL_DRIVER); in hsw_set_power_well()
431 POSTING_READ(DC_STATE_EN); in bxt_enable_dc9()
445 POSTING_READ(DC_STATE_EN); in bxt_disable_dc9()
458 POSTING_READ(DC_STATE_DEBUG); in gen9_set_dc_state_debugmask_memory_up()
510 POSTING_READ(DC_STATE_EN); in gen9_enable_dc5()
524 POSTING_READ(DC_STATE_EN); in gen9_disable_dc5()
569 POSTING_READ(DC_STATE_EN); in skl_enable_dc6()
583 POSTING_READ(DC_STATE_EN); in skl_disable_dc6()
667 POSTING_READ(HSW_PWR_WELL_DRIVER); in skl_set_power_well()
Dintel_display.c1616 POSTING_READ(reg); in vlv_enable_pll()
1623 POSTING_READ(DPLL_MD(crtc->pipe)); in vlv_enable_pll()
1627 POSTING_READ(reg); in vlv_enable_pll()
1630 POSTING_READ(reg); in vlv_enable_pll()
1633 POSTING_READ(reg); in vlv_enable_pll()
1673 POSTING_READ(DPLL_MD(pipe)); in chv_enable_pll()
1727 POSTING_READ(reg); in i9xx_enable_pll()
1744 POSTING_READ(reg); in i9xx_enable_pll()
1747 POSTING_READ(reg); in i9xx_enable_pll()
1750 POSTING_READ(reg); in i9xx_enable_pll()
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Dintel_dp.c354 POSTING_READ(intel_dp->output_reg); in vlv_power_sequencer_kick()
357 POSTING_READ(intel_dp->output_reg); in vlv_power_sequencer_kick()
360 POSTING_READ(intel_dp->output_reg); in vlv_power_sequencer_kick()
1569 POSTING_READ(DP_A); in ironlake_set_pll_cpu_edp()
1800 POSTING_READ(pp_ctrl_reg); in edp_panel_vdd_on()
1865 POSTING_READ(pp_ctrl_reg); in edp_panel_vdd_off_sync()
1956 POSTING_READ(pp_ctrl_reg); in edp_panel_on()
1964 POSTING_READ(pp_ctrl_reg); in edp_panel_on()
1972 POSTING_READ(pp_ctrl_reg); in edp_panel_on()
2019 POSTING_READ(pp_ctrl_reg); in edp_panel_off()
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Dintel_crt.c303 POSTING_READ(crt->adpa_reg); in intel_ironlake_crt_detect_hotplug()
524 POSTING_READ(pipeconf_reg); in intel_crt_load_detect()
725 POSTING_READ(crt->adpa_reg); in intel_crt_reset()
Dintel_panel.c887 POSTING_READ(BLC_PWM_PCH_CTL1); in lpt_enable_backlight()
923 POSTING_READ(BLC_PWM_CPU_CTL2); in pch_enable_backlight()
937 POSTING_READ(BLC_PWM_PCH_CTL1); in pch_enable_backlight()
965 POSTING_READ(BLC_PWM_CTL); in i9xx_enable_backlight()
1007 POSTING_READ(BLC_PWM_CTL2); in i965_enable_backlight()
1041 POSTING_READ(VLV_BLC_PWM_CTL2(pipe)); in vlv_enable_backlight()
1090 POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller)); in bxt_enable_backlight()
Dintel_i2c.c186 POSTING_READ(bus->gpio_reg); in set_clock()
203 POSTING_READ(bus->gpio_reg); in set_data()
Dintel_psr.c91 POSTING_READ(ctl_reg); in intel_psr_write_vsc()
103 POSTING_READ(ctl_reg); in intel_psr_write_vsc()
Dintel_ringbuffer.c519 POSTING_READ(mmio); in intel_ring_setup_status_page()
1519 POSTING_READ(RING_ACTHD(ring->mmio_base)); in gen6_ring_get_seqno()
1594 POSTING_READ(IMR); in i9xx_ring_get_irq()
1612 POSTING_READ(IMR); in i9xx_ring_put_irq()
1788 POSTING_READ(RING_IMR(ring->mmio_base)); in gen8_ring_get_irq()
1810 POSTING_READ(RING_IMR(ring->mmio_base)); in gen8_ring_put_irq()
2476 POSTING_READ(RING_TAIL(ring->mmio_base)); in gen6_bsd_ring_write_tail()
Dintel_lrc.c1492 POSTING_READ(RING_HWS_PGA(ring->mmio_base)); in gen8_init_common_ring()
1498 POSTING_READ(RING_MODE_GEN7(ring)); in gen8_init_common_ring()
1645 POSTING_READ(RING_IMR(ring->mmio_base)); in gen8_logical_ring_get_irq()
1661 POSTING_READ(RING_IMR(ring->mmio_base)); in gen8_logical_ring_put_irq()
2453 POSTING_READ(RING_HWS_PGA(ring->mmio_base)); in lrc_setup_hardware_status_page()
Dintel_lvds.c226 POSTING_READ(lvds_encoder->reg); in intel_enable_lvds()
253 POSTING_READ(lvds_encoder->reg); in intel_disable_lvds()
Dintel_pm.c296 POSTING_READ(FW_BLC_SELF_VLV); in intel_set_memory_cxsr()
300 POSTING_READ(FW_BLC_SELF); in intel_set_memory_cxsr()
305 POSTING_READ(DSPFW3); in intel_set_memory_cxsr()
310 POSTING_READ(FW_BLC_SELF); in intel_set_memory_cxsr()
315 POSTING_READ(INSTPM); in intel_set_memory_cxsr()
892 POSTING_READ(DSPFW1); in vlv_write_wm_values()
4247 POSTING_READ(VIDSTART); in ironlake_enable_drps()
4473 POSTING_READ(GEN6_RPNSWREQ); in gen6_set_rps()
6091 POSTING_READ(ECR); in intel_init_emon()
6455 POSTING_READ(DSPSURF(pipe)); in g4x_disable_trickle_feed()
[all …]
Dintel_sdvo.c250 POSTING_READ(intel_sdvo->sdvo_reg); in intel_sdvo_write_sdvox()
257 POSTING_READ(intel_sdvo->sdvo_reg); in intel_sdvo_write_sdvox()
275 POSTING_READ(GEN3_SDVOB); in intel_sdvo_write_sdvox()
277 POSTING_READ(GEN3_SDVOC); in intel_sdvo_write_sdvox()
Dintel_dsi.c409 POSTING_READ(port_ctrl); in intel_dsi_port_enable()
428 POSTING_READ(port_ctrl); in intel_dsi_port_disable()
Dintel_dsi_pll.c514 POSTING_READ(BXT_DSI_PLL_CTL); in bxt_configure_dsi_pll()
Dintel_tv.c1231 POSTING_READ(TV_DAC); in intel_tv_detect_type()
1261 POSTING_READ(TV_CTL); in intel_tv_detect_type()
Di915_gem_gtt.c1745 POSTING_READ(RING_PP_DIR_DCLV(ring)); in gen6_mm_switch()
2305 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); in i915_check_and_clear_faults()
2314 POSTING_READ(GFX_FLSH_CNTL_GEN6); in i915_ggtt_flush()
2395 POSTING_READ(GFX_FLSH_CNTL_GEN6); in gen8_ggtt_insert_entries()
2439 POSTING_READ(GFX_FLSH_CNTL_GEN6); in gen6_ggtt_insert_entries()
Dintel_uncore.c1415 POSTING_READ(VDECCLK_GATE_D); in g4x_do_reset()
1425 POSTING_READ(VDECCLK_GATE_D); in g4x_do_reset()
Di915_guc_submission.c97 POSTING_READ(SOFT_SCRATCH(i - 1)); in host2guc_action()
Dintel_fbc.c188 POSTING_READ(MSG_FBC_REND_STATE); in intel_fbc_nuke()

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