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Searched refs:RCS (Results 1 – 16 of 16) sorted by relevance

/drivers/gpu/drm/i915/
Di915_gem_context.c342 if (lctx->legacy_hw_ctx.rcs_state && i == RCS) in i915_gem_context_reset()
363 if (WARN_ON(dev_priv->ring[RCS].default_context)) in i915_gem_context_init()
409 struct intel_context *dctx = dev_priv->ring[RCS].default_context; in i915_gem_context_fini()
424 WARN_ON(!dev_priv->ring[RCS].last_context); in i915_gem_context_fini()
425 if (dev_priv->ring[RCS].last_context == dctx) { in i915_gem_context_fini()
430 dev_priv->ring[RCS].last_context = NULL; in i915_gem_context_fini()
628 if (ring != &dev_priv->ring[RCS]) in needs_pd_load_pre()
646 if (ring != &dev_priv->ring[RCS]) in needs_pd_load_post()
665 if (from != NULL && ring == &dev_priv->ring[RCS]) { in do_switch()
674 if (ring == &dev_priv->ring[RCS]) { in do_switch()
[all …]
Dintel_ringbuffer.c493 case RCS: in intel_ring_setup_status_page()
1140 WARN_ON(ring->id != RCS); in init_workarounds_ring()
1703 if (HAS_L3_DPF(dev) && ring->id == RCS) in gen6_ring_get_irq()
1725 if (HAS_L3_DPF(dev) && ring->id == RCS) in gen6_ring_put_irq()
1781 if (HAS_L3_DPF(dev) && ring->id == RCS) { in gen8_ring_get_irq()
1804 if (HAS_L3_DPF(dev) && ring->id == RCS) { in gen8_ring_put_irq()
2154 WARN_ON(ring->id != RCS); in intel_init_ring_buffer()
2202 WARN_ON(ring->id != RCS); in intel_cleanup_ring_buffer()
2653 struct intel_engine_cs *ring = &dev_priv->ring[RCS]; in intel_init_render_ring_buffer()
2658 ring->id = RCS; in intel_init_render_ring_buffer()
[all …]
Dintel_ringbuffer.h70 ring->semaphore.signal_ggtt[RCS] = GEN8_SIGNAL_OFFSET(ring, RCS); \
149 RCS = 0x0, enumerator
Di915_guc_submission.c887 struct intel_context *ctx = dev_priv->ring[RCS].default_context; in i915_guc_submission_enable()
941 ctx = dev_priv->ring[RCS].default_context; in intel_guc_suspend()
947 data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state); in intel_guc_suspend()
967 ctx = dev_priv->ring[RCS].default_context; in intel_guc_resume()
972 data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state); in intel_guc_resume()
Dintel_lrc.c887 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) { in intel_execlists_submission()
916 if (ring == &dev_priv->ring[RCS] && in intel_execlists_submission()
1414 WARN_ON(ring->id != RCS); in intel_init_workaround_bb()
1971 struct intel_engine_cs *ring = &dev_priv->ring[RCS]; in logical_render_ring_init()
1975 ring->id = RCS; in logical_render_ring_init()
2195 intel_logical_ring_cleanup(&dev_priv->ring[RCS]); in intel_logical_rings_init()
2281 if (ring->id == RCS) in populate_lr_context()
2314 if (ring->id == RCS) { in populate_lr_context()
2368 if (ring->id == RCS) { in populate_lr_context()
2421 case RCS: in get_lr_context_size()
Di915_gem_execbuffer.c1023 if (ring->id != RCS && ctx_id != DEFAULT_CONTEXT_HANDLE) in i915_gem_validate_context()
1106 if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) { in i915_reset_gen7_sol_offsets()
1261 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) { in i915_gem_ringbuffer_submission()
1288 if (ring == &dev_priv->ring[RCS] && in i915_gem_ringbuffer_submission()
1439 ring = &dev_priv->ring[RCS]; in i915_gem_do_execbuffer()
1481 if (ring->id != RCS) { in i915_gem_do_execbuffer()
Di915_gem_render_state.c177 if (WARN_ON(ring->id != RCS)) in i915_gem_render_state_prepare()
Dintel_overlay.c236 struct intel_engine_cs *ring = &dev_priv->ring[RCS]; in intel_overlay_on()
270 struct intel_engine_cs *ring = &dev_priv->ring[RCS]; in intel_overlay_continue()
339 struct intel_engine_cs *ring = &dev_priv->ring[RCS]; in intel_overlay_off()
411 struct intel_engine_cs *ring = &dev_priv->ring[RCS]; in intel_overlay_release_old_vid()
Di915_gpu_error.c36 case RCS: return "render"; in ring_str()
907 case RCS: in i915_record_ring_state()
964 if (ring->id != RCS || !error->ccid) in i915_gem_record_active_context()
Di915_irq.c1249 notify_ring(&dev_priv->ring[RCS]); in ilk_gt_irq_handler()
1261 notify_ring(&dev_priv->ring[RCS]); in snb_gt_irq_handler()
1288 intel_lrc_irq_handler(&dev_priv->ring[RCS]); in gen8_gt_irq_handler()
1290 notify_ring(&dev_priv->ring[RCS]); in gen8_gt_irq_handler()
3874 notify_ring(&dev_priv->ring[RCS]); in i8xx_irq_handler()
4063 notify_ring(&dev_priv->ring[RCS]); in i915_irq_handler()
4288 notify_ring(&dev_priv->ring[RCS]); in i965_irq_handler()
Di915_gem.c2252 [RCS] = GEN8_RTCR, in invalidate_tlbs()
4844 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); in i915_gem_init_rings()
4891 BUG_ON(!dev_priv->ring[RCS].default_context); in i915_gem_init_hw()
4945 if (ring->id == RCS) { in i915_gem_init_hw()
Di915_cmd_parser.c774 case RCS: in i915_cmd_parser_init_ring()
Di915_gem_gtt.c1725 if (ring->id != RCS) { in gen7_mm_switch()
2305 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); in i915_check_and_clear_faults()
Di915_drv.h2545 #define RENDER_RING (1<<RCS)
Dintel_display.c11120 if (ring->id == RCS) { in intel_gen7_queue_flip()
11158 if (ring->id == RCS) { in intel_gen7_queue_flip()
11538 if (ring == NULL || ring->id != RCS) in intel_crtc_page_flip()
11541 ring = &dev_priv->ring[RCS]; in intel_crtc_page_flip()
Di915_debugfs.c5210 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},