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Searched refs:RREG32_SMC (Results 1 – 24 of 24) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dtonga_smc.c130 uint32_t val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); in tonga_is_smc_ram_running()
133 return ((0 == val) && (0x20100 <= RREG32_SMC(ixSMC_PC_C))); in tonga_is_smc_ram_running()
248 val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
349 uint32_t val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
353 val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
550 if (fw_mask == (RREG32_SMC(ixSOFT_REGISTERS_TABLE_28) & fw_mask)) in tonga_smu_check_fw_load_finish()
570 val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); in tonga_smu_start_in_protection_mode()
582 val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); in tonga_smu_start_in_protection_mode()
587 val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); in tonga_smu_start_in_protection_mode()
592 val = RREG32_SMC(ixSMU_INPUT_DATA); in tonga_smu_start_in_protection_mode()
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Dfiji_smc.c130 uint32_t val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); in fiji_is_smc_ram_running()
133 return ((0 == val) && (0x20100 <= RREG32_SMC(ixSMC_PC_C))); in fiji_is_smc_ram_running()
248 val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
349 uint32_t val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
353 val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
548 if (fw_mask == (RREG32_SMC(ixSOFT_REGISTERS_TABLE_28) & fw_mask)) in fiji_smu_check_fw_load_finish()
568 val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); in fiji_smu_start_in_protection_mode()
580 val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); in fiji_smu_start_in_protection_mode()
585 val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); in fiji_smu_start_in_protection_mode()
590 val = RREG32_SMC(ixSMU_INPUT_DATA); in fiji_smu_start_in_protection_mode()
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Dci_smc.c119 u32 tmp = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); in amdgpu_ci_start_smc()
127 u32 tmp = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); in amdgpu_ci_reset_smc()
142 u32 tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); in amdgpu_ci_stop_smc_clock()
151 u32 tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); in amdgpu_ci_start_smc_clock()
160 u32 clk = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); in amdgpu_ci_is_smc_running()
161 u32 pc_c = RREG32_SMC(ixSMC_PC_C); in amdgpu_ci_is_smc_running()
199 tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); in amdgpu_ci_wait_for_smc_inactive()
Diceland_smc.c126 uint32_t val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); in iceland_start_smc()
134 uint32_t val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); in iceland_reset_smc()
150 uint32_t val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); in iceland_stop_smc_clock()
158 uint32_t val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); in iceland_start_smc_clock()
166 uint32_t val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); in iceland_is_smc_ram_running()
169 return ((0 == val) && (0x20100 <= RREG32_SMC(ixSMC_PC_C))); in iceland_is_smc_ram_running()
254 val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
302 val = RREG32_SMC(ixRCU_UC_EVENTS); in iceland_smu_upload_firmware_image()
307 val = RREG32_SMC(ixSMC_SYSCON_MISC_CNTL); in iceland_smu_upload_firmware_image()
387 val = RREG32_SMC(ixFIRMWARE_FLAGS); in iceland_smu_start_smc()
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Dci_dpm.c699 data = RREG32_SMC(config_regs->offset); in ci_program_pt_config_registers()
1000 tmp = RREG32_SMC(ixCG_THERMAL_INT); in ci_thermal_set_temperature_range()
1008 tmp = RREG32_SMC(ixCG_THERMAL_CTRL); in ci_thermal_set_temperature_range()
1022 u32 thermal_int = RREG32_SMC(ixCG_THERMAL_INT); in ci_thermal_enable_alert()
1054 tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK) in ci_fan_ctrl_set_static_mode()
1057 tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__TMIN_MASK) in ci_fan_ctrl_set_static_mode()
1063 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK; in ci_fan_ctrl_set_static_mode()
1067 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK; in ci_fan_ctrl_set_static_mode()
1088 duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) in ci_thermal_setup_fan_table()
1133 tmp = (RREG32_SMC(ixCG_MULT_THERMAL_CTRL) & CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK) in ci_thermal_setup_fan_table()
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Dkv_dpm.c431 data = RREG32_SMC(config_regs->offset); in kv_program_pt_config_registers()
732 u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT); in kv_start_dpm()
747 u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL); in kv_start_am()
758 u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL); in kv_reset_am()
2534 nbdpmconfig1 = RREG32_SMC(ixNB_DPM_CONFIG_1); in kv_program_nbps_index_settings()
2563 tmp = RREG32_SMC(ixCG_THERMAL_INT_CTRL); in kv_set_thermal_temperature_range()
2891 (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) & in kv_dpm_debugfs_print_current_performance_level()
2901 tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) & in kv_dpm_debugfs_print_current_performance_level()
2972 temp = RREG32_SMC(0xC0300E0C); in kv_dpm_get_temp()
3164 RREG32_SMC(ixLCAC_SX0_OVR_SEL)); in kv_dpm_print_status()
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Dcik.c842 if (RREG32_SMC(ixGENERAL_PWRMGT) & GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK) in cik_get_xclk()
845 if (RREG32_SMC(ixCG_CLKPIN_CNTL) & CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK) in cik_get_xclk()
902 rom_cntl = RREG32_SMC(ixROM_CNTL); in cik_read_disabled_bios()
1496 tmp = RREG32_SMC(cntl_reg); in cik_set_uvd_clock()
1503 if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK) in cik_set_uvd_clock()
1538 if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK) in cik_set_vce_clocks()
1545 tmp = RREG32_SMC(ixCG_ECLK_CNTL); in cik_set_vce_clocks()
1552 if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK) in cik_set_vce_clocks()
1829 orig = data = RREG32_SMC(ixTHM_CLK_CNTL); in cik_program_aspm()
1837 orig = data = RREG32_SMC(ixMISC_CLK_CTRL); in cik_program_aspm()
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Dvi.c296 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2); in vi_get_xclk()
300 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL); in vi_get_xclk()
351 rom_cntl = RREG32_SMC(ixROM_CNTL); in vi_read_disabled_bios()
984 tmp = RREG32_SMC(cntl_reg); in vi_set_uvd_clock()
991 if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK) in vi_set_uvd_clock()
1362 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK) in vi_get_rev_id()
Dkv_smc.c64 *enable_mask = RREG32_SMC(ixSMC_SYSCON_MSG_ARG_0); in amdgpu_kv_dpm_get_enable_mask()
Dvce_v3_0.c222 tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS) & in vce_v3_0_get_harvest_config()
226 tmp = (RREG32_SMC(ixCC_HARVEST_FUSES) & in vce_v3_0_get_harvest_config()
Dcz_dpm.c515 u32 sclk_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX), in cz_dpm_debugfs_print_current_performance_level()
517 u32 uvd_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_2), in cz_dpm_debugfs_print_current_performance_level()
519 u32 vce_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_2), in cz_dpm_debugfs_print_current_performance_level()
531 tmp = (RREG32_SMC(ixSMUSVI_NB_CURRENTVID) & in cz_dpm_debugfs_print_current_performance_level()
534 tmp = (RREG32_SMC(ixSMUSVI_GFX_CURRENTVID) & in cz_dpm_debugfs_print_current_performance_level()
1487 uint32_t temp = RREG32_SMC(0xC0300E0C); in cz_dpm_get_temperature()
Damdgpu_cgs.c310 return RREG32_SMC(index); in amdgpu_cgs_read_ind_register()
Damdgpu.h2151 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) macro
/drivers/gpu/drm/radeon/
Dci_smc.c116 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in ci_start_smc()
124 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in ci_reset_smc()
139 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in ci_stop_smc_clock()
148 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in ci_start_smc_clock()
157 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in ci_is_smc_running()
158 u32 pc_c = RREG32_SMC(SMC_PC_C); in ci_is_smc_running()
197 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
Dsi_smc.c115 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in si_start_smc()
131 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in si_reset_smc()
145 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in si_stop_smc_clock()
154 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in si_start_smc_clock()
163 u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in si_is_smc_running()
164 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in si_is_smc_running()
202 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in si_wait_for_smc_inactive()
Dtrinity_dpm.c377 value = RREG32_SMC(GFX_POWER_GATING_CNTL); in trinity_gfx_powergating_initialize()
505 if (RREG32_SMC(CC_SMU_TST_EFUSE1_MISC) & RB_BACKEND_DISABLE_MASK) in trinity_gfx_powergating_enable()
506 WREG32_SMC(SMU_SCRATCH_A, (RREG32_SMC(SMU_SCRATCH_A) | 0x01)); in trinity_gfx_powergating_enable()
521 value = RREG32_SMC(PM_I_CNTL_1); in trinity_gfx_dynamic_mgpg_enable()
526 value = RREG32_SMC(SMU_S_PG_CNTL); in trinity_gfx_dynamic_mgpg_enable()
531 value = RREG32_SMC(SMU_S_PG_CNTL); in trinity_gfx_dynamic_mgpg_enable()
535 value = RREG32_SMC(PM_I_CNTL_1); in trinity_gfx_dynamic_mgpg_enable()
595 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix); in trinity_set_divider_value()
605 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix); in trinity_set_divider_value()
617 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); in trinity_set_ds_dividers()
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Dci_dpm.c581 data = RREG32_SMC(config_regs->offset); in ci_program_pt_config_registers()
883 tmp = RREG32_SMC(CG_THERMAL_INT); in ci_thermal_set_temperature_range()
891 tmp = RREG32_SMC(CG_THERMAL_CTRL); in ci_thermal_set_temperature_range()
906 u32 thermal_int = RREG32_SMC(CG_THERMAL_INT); in ci_thermal_enable_alert()
938 tmp = (RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; in ci_fan_ctrl_set_static_mode()
940 tmp = (RREG32_SMC(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; in ci_fan_ctrl_set_static_mode()
945 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK; in ci_fan_ctrl_set_static_mode()
949 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; in ci_fan_ctrl_set_static_mode()
970 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; in ci_thermal_setup_fan_table()
1014 tmp = (RREG32_SMC(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; in ci_thermal_setup_fan_table()
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Dkv_smc.c61 *enable_mask = RREG32_SMC(SMC_SYSCON_MSG_ARG_0); in kv_dpm_get_enable_mask()
Dkv_dpm.c298 data = RREG32_SMC(config_regs->offset); in kv_program_pt_config_registers()
645 u32 tmp = RREG32_SMC(GENERAL_PWRMGT); in kv_start_dpm()
660 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); in kv_start_am()
670 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); in kv_reset_am()
1176 thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL); in kv_enable_thermal_int()
2440 nbdpmconfig1 = RREG32_SMC(NB_DPM_CONFIG_1); in kv_program_nbps_index_settings()
2467 tmp = RREG32_SMC(CG_THERMAL_INT_CTRL); in kv_set_thermal_temperature_range()
2804 (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >> in kv_dpm_debugfs_print_current_performance_level()
2813 tmp = (RREG32_SMC(SMU_VOLTAGE_STATUS) & SMU_VOLTAGE_CURRENT_LEVEL_MASK) >> in kv_dpm_debugfs_print_current_performance_level()
2827 (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >> in kv_dpm_get_current_sclk()
Dcik.c208 temp = (RREG32_SMC(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >> in ci_get_temp()
227 temp = RREG32_SMC(0xC0300E0C); in kv_get_temp()
1718 if (RREG32_SMC(GENERAL_PWRMGT) & GPU_COUNTER_CLK) in cik_get_xclk()
1721 if (RREG32_SMC(CG_CLKPIN_CNTL) & XTALIN_DIVIDE) in cik_get_xclk()
9695 tmp = RREG32_SMC(cntl_reg); in cik_set_uvd_clock()
9701 if (RREG32_SMC(status_reg) & DCLK_STATUS) in cik_set_uvd_clock()
9735 if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS) in cik_set_vce_clocks()
9742 tmp = RREG32_SMC(CG_ECLK_CNTL); in cik_set_vce_clocks()
9748 if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS) in cik_set_vce_clocks()
10014 orig = data = RREG32_SMC(THM_CLK_CNTL); in cik_program_aspm()
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Dradeon.h2541 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) macro
2573 uint32_t tmp_ = RREG32_SMC(reg); \
Dni.c887 u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff; in tn_get_temp()
Dsi.c7791 if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask) in si_vce_send_vcepll_ctlreq()
Dsi_dpm.c2750 data = RREG32_SMC(offset); in si_program_cac_config_registers()