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Searched refs:RXS (Results 1 – 9 of 9) sorted by relevance

/drivers/net/wan/
Dhd64570.h67 #define RXS 0x16 /* RX Clock Source */ macro
Dhd64572.h70 #define RXS 0x13c /* RX clock source */ macro
Dhd64572.c411 sca_out(port->rxs, msci + RXS, card); in sca_set_port()
471 sca_out(port->rxs, msci + RXS, card); in sca_open()
Dhd64570.c447 sca_out(port->rxs, msci + RXS, card); in sca_set_port()
515 sca_out(port->rxs, msci + RXS, card); in sca_open()
Dc101.c181 sca_out(rxs, MSCI1_OFFSET + RXS, port); in c101_set_iface()
Dpci200syn.c153 sca_out(rxs, msci + RXS, card); in pci200_set_iface()
Dpc300too.c154 sca_out(rxs, msci + RXS, card); in pc300_set_iface()
Dn2.c204 sca_out(rxs, msci + RXS, card); in n2_set_iface()
/drivers/tty/
Dsynclinkmp.c331 #define RXS 0x36 macro
4040 write_reg(info, RXS, 0x40); in enable_loopback()
4054 write_reg(info, RXS, 0x00); in enable_loopback()
4103 write_reg(info, RXS, in set_rate()
4104 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue)); in set_rate()
4109 write_reg(info, RXS,0); in set_rate()
4440 write_reg(info, RXS, RegValue); in async_mode()
4607 write_reg(info, RXS, RegValue); in hdlc_mode()