Searched refs:arm_lpae_s1_cfg (Results 1 – 5 of 5) sorted by relevance
715 cfg->arm_lpae_s1_cfg.tcr = reg; in arm_64_lpae_alloc_pgtable_s1()725 cfg->arm_lpae_s1_cfg.mair[0] = reg; in arm_64_lpae_alloc_pgtable_s1()726 cfg->arm_lpae_s1_cfg.mair[1] = 0; in arm_64_lpae_alloc_pgtable_s1()737 cfg->arm_lpae_s1_cfg.ttbr[0] = virt_to_phys(data->pgd); in arm_64_lpae_alloc_pgtable_s1()738 cfg->arm_lpae_s1_cfg.ttbr[1] = 0; in arm_64_lpae_alloc_pgtable_s1()845 cfg->arm_lpae_s1_cfg.tcr |= ARM_32_LPAE_TCR_EAE; in arm_32_lpae_alloc_pgtable_s1()846 cfg->arm_lpae_s1_cfg.tcr &= 0xffffffff; in arm_32_lpae_alloc_pgtable_s1()
62 } arm_lpae_s1_cfg; member
751 reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; in arm_smmu_init_context_bank()756 reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1]; in arm_smmu_init_context_bank()766 reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr; in arm_smmu_init_context_bank()769 reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32; in arm_smmu_init_context_bank()780 reg = pgtbl_cfg->arm_lpae_s1_cfg.mair[0]; in arm_smmu_init_context_bank()782 reg = pgtbl_cfg->arm_lpae_s1_cfg.mair[1]; in arm_smmu_init_context_bank()
334 ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr[0]; in ipmmu_domain_init_context()348 ipmmu_ctx_write(domain, IMMAIR0, domain->cfg.arm_lpae_s1_cfg.mair[0]); in ipmmu_domain_init_context()
1474 cfg->cd.ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; in arm_smmu_domain_finalise_s1()1475 cfg->cd.tcr = pgtbl_cfg->arm_lpae_s1_cfg.tcr; in arm_smmu_domain_finalise_s1()1476 cfg->cd.mair = pgtbl_cfg->arm_lpae_s1_cfg.mair[0]; in arm_smmu_domain_finalise_s1()