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Searched refs:cfgcr1 (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/i915/
Dintel_ddi.c1566 uint32_t ctrl1, cfgcr1, cfgcr2; in skl_ddi_pll_select() local
1584 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE | in skl_ddi_pll_select()
1607 cfgcr1 = cfgcr2 = 0; in skl_ddi_pll_select()
1615 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; in skl_ddi_pll_select()
2565 u32 ctl, cfgcr1, cfgcr2; member
2573 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
2579 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
2585 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
2609 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1); in skl_ddi_pll_enable()
2611 POSTING_READ(regs[pll->id].cfgcr1); in skl_ddi_pll_enable()
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Di915_drv.h384 uint32_t cfgcr1, cfgcr2; member
Dintel_dp.c1120 pipe_config->dpll_hw_state.cfgcr1 = 0; in skl_edp_set_pll_config()
Dintel_display.c12105 pipe_config->dpll_hw_state.cfgcr1, in intel_dump_pipe_config()
12639 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); in intel_pipe_config_compare()