Searched refs:clksel (Results 1 – 5 of 5) sorted by relevance
| /drivers/mmc/host/ |
| D | dw_mmc-exynos.c | 133 u32 clksel; in dw_mci_exynos_set_clksel_timing() local
137 clksel = mci_readl(host, CLKSEL64); in dw_mci_exynos_set_clksel_timing()
139 clksel = mci_readl(host, CLKSEL); in dw_mci_exynos_set_clksel_timing()
141 clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing; in dw_mci_exynos_set_clksel_timing()
145 mci_writel(host, CLKSEL64, clksel); in dw_mci_exynos_set_clksel_timing()
147 mci_writel(host, CLKSEL, clksel); in dw_mci_exynos_set_clksel_timing()
181 u32 clksel; in dw_mci_exynos_resume_noirq() local
185 clksel = mci_readl(host, CLKSEL64); in dw_mci_exynos_resume_noirq()
187 clksel = mci_readl(host, CLKSEL); in dw_mci_exynos_resume_noirq()
189 if (clksel & SDMMC_CLKSEL_WAKEUP_INT) { in dw_mci_exynos_resume_noirq()
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| /drivers/clocksource/ |
| D | cadence_ttc_timer.c | 475 int clksel; in ttc_timer_init() local
502 clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET); in ttc_timer_init()
503 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); in ttc_timer_init()
504 clk_cs = of_clk_get(timer, clksel); in ttc_timer_init()
510 clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET); in ttc_timer_init()
511 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); in ttc_timer_init()
512 clk_ce = of_clk_get(timer, clksel); in ttc_timer_init()
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| /drivers/clk/rockchip/ |
| D | clk-cpu.c | 112 const struct rockchip_cpuclk_clksel *clksel = &rate->divs[i]; in rockchip_cpuclk_set_dividers() local
114 if (!clksel->reg) in rockchip_cpuclk_set_dividers()
118 __func__, clksel->reg, clksel->val); in rockchip_cpuclk_set_dividers()
119 writel(clksel->val , cpuclk->reg_base + clksel->reg); in rockchip_cpuclk_set_dividers()
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| /drivers/clk/ |
| D | clk-qoriq.c | 58 struct clockgen_sourceinfo clksel[NUM_MUX_PARENTS]; member
643 u32 clksel; in mux_set_parent() local
648 clksel = hwc->parent_to_clksel[idx]; in mux_set_parent()
649 cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg); in mux_set_parent()
657 u32 clksel; in mux_get_parent() local
660 clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; in mux_get_parent()
662 ret = hwc->clksel_to_parent[clksel]; in mux_get_parent()
690 if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID)) in get_pll_div()
693 pll = hwc->info->clksel[idx].pll; in get_pll_div()
694 div = hwc->info->clksel[idx].div; in get_pll_div()
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| /drivers/mfd/ |
| D | asic3.c | 390 unsigned long clksel = 0; in asic3_irq_probe() local
400 clksel |= CLOCK_SEL_CX; in asic3_irq_probe()
402 clksel); in asic3_irq_probe()
960 unsigned long clksel; in asic3_probe() local
991 clksel = 0; in asic3_probe()
992 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel); in asic3_probe()
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