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Searched refs:con0 (Results 1 – 3 of 3) sorted by relevance

/drivers/clk/samsung/
Dclk-pll.c401 u32 con0, con1; in samsung_pll45xx_set_rate() local
412 con0 = __raw_readl(pll->con_reg); in samsung_pll45xx_set_rate()
415 if (!(samsung_pll45xx_mp_change(con0, con1, rate))) { in samsung_pll45xx_set_rate()
417 con0 &= ~(PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT); in samsung_pll45xx_set_rate()
418 con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT; in samsung_pll45xx_set_rate()
419 __raw_writel(con0, pll->con_reg); in samsung_pll45xx_set_rate()
425 con0 &= ~((PLL45XX_MDIV_MASK << PLL45XX_MDIV_SHIFT) | in samsung_pll45xx_set_rate()
428 con0 |= (rate->mdiv << PLL45XX_MDIV_SHIFT) | in samsung_pll45xx_set_rate()
451 __raw_writel(con0, pll->con_reg); in samsung_pll45xx_set_rate()
552 u32 con0, con1, lock; in samsung_pll46xx_set_rate() local
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/drivers/video/fbdev/
Dpxa168fb.h356 #define CFG_COS0(con0) (con0) argument
/drivers/video/fbdev/mmp/hw/
Dmmp_ctrl.h599 #define CFG_COS0(con0) (con0) argument