/drivers/clk/tegra/ |
D | clk-divider.c | 32 static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate, in get_div() argument 36 u8 flags = divider->flags; in get_div() 42 mul = get_mul(divider); in get_div() 60 if (divider_ux1 > get_max_div(divider)) in get_div() 61 return get_max_div(divider); in get_div() 69 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); in clk_frac_div_recalc_rate() local 74 reg = readl_relaxed(divider->reg) >> divider->shift; in clk_frac_div_recalc_rate() 75 div = reg & div_mask(divider); in clk_frac_div_recalc_rate() 77 mul = get_mul(divider); in clk_frac_div_recalc_rate() 90 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); in clk_frac_div_round_rate() local [all …]
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D | clk-periph.c | 51 struct clk_hw *div_hw = &periph->divider.hw; in clk_periph_recalc_rate() 63 struct clk_hw *div_hw = &periph->divider.hw; in clk_periph_round_rate() 75 struct clk_hw *div_hw = &periph->divider.hw; in clk_periph_set_rate() 172 periph->divider.reg = div ? (clk_base + offset) : NULL; in _tegra_clk_register_periph() 182 periph->divider.hw.clk = div ? clk : NULL; in _tegra_clk_register_periph()
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/drivers/clk/ti/ |
D | divider.c | 44 static unsigned int _get_maxdiv(struct clk_divider *divider) in _get_maxdiv() argument 46 if (divider->flags & CLK_DIVIDER_ONE_BASED) in _get_maxdiv() 47 return div_mask(divider); in _get_maxdiv() 48 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in _get_maxdiv() 49 return 1 << div_mask(divider); in _get_maxdiv() 50 if (divider->table) in _get_maxdiv() 51 return _get_table_maxdiv(divider->table); in _get_maxdiv() 52 return div_mask(divider) + 1; in _get_maxdiv() 66 static unsigned int _get_div(struct clk_divider *divider, unsigned int val) in _get_div() argument 68 if (divider->flags & CLK_DIVIDER_ONE_BASED) in _get_div() [all …]
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D | clk-dra7-atl.c | 54 u32 divider; /* Cached divider value */ member 90 cdesc->divider - 1); in atl_clk_enable() 125 return parent_rate / cdesc->divider; in atl_clk_recalc_rate() 131 unsigned divider; in atl_clk_round_rate() local 133 divider = (*parent_rate + rate / 2) / rate; in atl_clk_round_rate() 134 if (divider > DRA7_ATL_DIVIDER_MASK + 1) in atl_clk_round_rate() 135 divider = DRA7_ATL_DIVIDER_MASK + 1; in atl_clk_round_rate() 137 return *parent_rate / divider; in atl_clk_round_rate() 144 u32 divider; in atl_clk_set_rate() local 150 divider = ((parent_rate + rate / 2) / rate) - 1; in atl_clk_set_rate() [all …]
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/drivers/clk/qcom/ |
D | clk-regmap-divider.c | 29 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_round_rate() local 31 return divider_round_rate(hw, rate, prate, NULL, divider->width, in div_round_rate() 38 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_set_rate() local 39 struct clk_regmap *clkr = ÷r->clkr; in div_set_rate() 42 div = divider_get_val(rate, parent_rate, NULL, divider->width, in div_set_rate() 45 return regmap_update_bits(clkr->regmap, divider->reg, in div_set_rate() 46 (BIT(divider->width) - 1) << divider->shift, in div_set_rate() 47 div << divider->shift); in div_set_rate() 53 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_recalc_rate() local 54 struct clk_regmap *clkr = ÷r->clkr; in div_recalc_rate() [all …]
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/drivers/clk/ |
D | clk-divider.c | 124 struct clk_divider *divider = to_clk_divider(hw); in divider_recalc_rate() local 127 div = _get_div(table, val, flags, divider->width); in divider_recalc_rate() 142 struct clk_divider *divider = to_clk_divider(hw); in clk_divider_recalc_rate() local 145 val = clk_readl(divider->reg) >> divider->shift; in clk_divider_recalc_rate() 146 val &= div_mask(divider->width); in clk_divider_recalc_rate() 148 return divider_recalc_rate(hw, parent_rate, val, divider->table, in clk_divider_recalc_rate() 149 divider->flags); in clk_divider_recalc_rate() 352 struct clk_divider *divider = to_clk_divider(hw); in clk_divider_round_rate() local 356 if (divider->flags & CLK_DIVIDER_READ_ONLY) { in clk_divider_round_rate() 357 bestdiv = clk_readl(divider->reg) >> divider->shift; in clk_divider_round_rate() [all …]
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D | clk-cdce925.c | 340 unsigned long divider; in cdce925_calc_divider() local 347 divider = DIV_ROUND_CLOSEST(parent_rate, rate); in cdce925_calc_divider() 348 if (divider > 0x7F) in cdce925_calc_divider() 349 divider = 0x7F; in cdce925_calc_divider() 351 return (u16)divider; in cdce925_calc_divider() 401 u16 divider = cdce925_calc_divider(rate, l_parent_rate); in cdce925_clk_round_rate() local 403 if (l_parent_rate / divider != rate) { in cdce925_clk_round_rate() 405 divider = cdce925_calc_divider(rate, l_parent_rate); in cdce925_clk_round_rate() 409 if (divider) in cdce925_clk_round_rate() 410 return (long)(l_parent_rate / divider); in cdce925_clk_round_rate() [all …]
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D | clk-xgene.c | 335 u32 divider; in xgene_clk_set_rate() local 345 divider_save = divider = parent_rate / rate; /* Rounded down */ in xgene_clk_set_rate() 346 divider &= (1 << pclk->param.reg_divider_width) - 1; in xgene_clk_set_rate() 347 divider <<= pclk->param.reg_divider_shift; in xgene_clk_set_rate() 354 data |= divider; in xgene_clk_set_rate() 374 u32 divider; in xgene_clk_round_rate() local 380 divider = parent_rate / rate; /* Rounded down */ in xgene_clk_round_rate() 382 divider = 1; in xgene_clk_round_rate() 385 return parent_rate / divider; in xgene_clk_round_rate()
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/drivers/clk/imx/ |
D | clk-fixup-div.c | 31 struct clk_divider divider; member 38 struct clk_divider *divider = to_clk_div(hw); in to_clk_fixup_div() local 40 return container_of(divider, struct clk_fixup_div, divider); in to_clk_fixup_div() 48 return fixup_div->ops->recalc_rate(&fixup_div->divider.hw, parent_rate); in clk_fixup_div_recalc_rate() 56 return fixup_div->ops->round_rate(&fixup_div->divider.hw, rate, prate); in clk_fixup_div_round_rate() 64 unsigned int divider, value; in clk_fixup_div_set_rate() local 68 divider = parent_rate / rate; in clk_fixup_div_set_rate() 71 value = divider - 1; in clk_fixup_div_set_rate() 116 fixup_div->divider.reg = reg; in imx_clk_fixup_divider() 117 fixup_div->divider.shift = shift; in imx_clk_fixup_divider() [all …]
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/drivers/clk/mxs/ |
D | clk-div.c | 28 struct clk_divider divider; member 36 struct clk_divider *divider = container_of(hw, struct clk_divider, hw); in to_clk_div() local 38 return container_of(divider, struct clk_div, divider); in to_clk_div() 46 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate() 54 return div->ops->round_rate(&div->divider.hw, rate, prate); in clk_div_round_rate() 63 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate() 96 div->divider.reg = reg; in mxs_clk_div() 97 div->divider.shift = shift; in mxs_clk_div() 98 div->divider.width = width; in mxs_clk_div() 99 div->divider.flags = CLK_DIVIDER_ONE_BASED; in mxs_clk_div() [all …]
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/drivers/media/i2c/cx25840/ |
D | cx25840-ir.c | 159 static inline unsigned int clock_divider_to_ns(unsigned int divider) in clock_divider_to_ns() argument 162 return DIV_ROUND_CLOSEST((divider + 1) * 1000, in clock_divider_to_ns() 172 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) in clock_divider_to_carrier_freq() argument 174 return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, (divider + 1) * 16); in clock_divider_to_carrier_freq() 184 static inline unsigned int clock_divider_to_freq(unsigned int divider, in clock_divider_to_freq() argument 188 (divider + 1) * rollovers); in clock_divider_to_freq() 229 static u32 clock_divider_to_resolution(u16 divider) in clock_divider_to_resolution() argument 236 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000, in clock_divider_to_resolution() 240 static u64 pulse_width_count_to_ns(u16 count, u16 divider) in pulse_width_count_to_ns() argument 249 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */ in pulse_width_count_to_ns() [all …]
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/drivers/media/pci/cx23885/ |
D | cx23888-ir.c | 193 static inline unsigned int clock_divider_to_ns(unsigned int divider) in clock_divider_to_ns() argument 196 return DIV_ROUND_CLOSEST((divider + 1) * 1000, in clock_divider_to_ns() 206 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) in clock_divider_to_carrier_freq() argument 208 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16); in clock_divider_to_carrier_freq() 218 static inline unsigned int clock_divider_to_freq(unsigned int divider, in clock_divider_to_freq() argument 222 (divider + 1) * rollovers); in clock_divider_to_freq() 263 static u32 clock_divider_to_resolution(u16 divider) in clock_divider_to_resolution() argument 270 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000, in clock_divider_to_resolution() 274 static u64 pulse_width_count_to_ns(u16 count, u16 divider) in pulse_width_count_to_ns() argument 283 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */ in pulse_width_count_to_ns() [all …]
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/drivers/video/fbdev/aty/ |
D | mach64_gx.c | 505 short divider = 0, tempA; in aty_var_to_pll_1703() local 522 divider = 0; in aty_var_to_pll_1703() 525 divider += 0x20; in aty_var_to_pll_1703() 543 divider &= ~0x1f; in aty_var_to_pll_1703() 544 divider |= tempA; in aty_var_to_pll_1703() 545 divider = in aty_var_to_pll_1703() 546 (divider & 0x00ff) + in aty_var_to_pll_1703() 554 program_bits = divider; in aty_var_to_pll_1703() 559 pll->ics2595.post_divider = divider; /* fuer nix */ in aty_var_to_pll_1703() 745 short divider = 0, tempA; in aty_var_to_pll_408() local [all …]
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D | mach64_ct.c | 122 u32 multiplier, divider, ras_multiplier, ras_divider, tmp; in aty_dsp_gt() local 127 divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div; in aty_dsp_gt() 133 divider = divider * (bpp >> 2); in aty_dsp_gt() 145 divider = divider * pll->xres & ~7; in aty_dsp_gt() 153 while (((multiplier | divider) & 1) == 0) { in aty_dsp_gt() 155 divider = divider >> 1; in aty_dsp_gt() 159 tmp = ((multiplier * pll->fifo_size) << vshift) / divider; in aty_dsp_gt() 172 dsp_off = ((multiplier * (pll->fifo_size - 1)) << vshift) / divider - in aty_dsp_gt() 179 dsp_on = ((multiplier << vshift) + divider) / divider; in aty_dsp_gt() 191 dsp_on = dsp_off - (multiplier << vshift) / divider; in aty_dsp_gt() [all …]
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/drivers/clk/bcm/ |
D | clk-bcm2835.c | 1052 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); in bcm2835_pll_divider_is_on() local 1053 struct bcm2835_cprman *cprman = divider->cprman; in bcm2835_pll_divider_is_on() 1054 const struct bcm2835_pll_divider_data *data = divider->data; in bcm2835_pll_divider_is_on() 1069 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); in bcm2835_pll_divider_get_rate() local 1070 struct bcm2835_cprman *cprman = divider->cprman; in bcm2835_pll_divider_get_rate() 1071 const struct bcm2835_pll_divider_data *data = divider->data; in bcm2835_pll_divider_get_rate() 1083 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); in bcm2835_pll_divider_off() local 1084 struct bcm2835_cprman *cprman = divider->cprman; in bcm2835_pll_divider_off() 1085 const struct bcm2835_pll_divider_data *data = divider->data; in bcm2835_pll_divider_off() 1099 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); in bcm2835_pll_divider_on() local [all …]
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/drivers/i2c/busses/ |
D | i2c-mxs.c | 698 uint32_t divider; in mxs_i2c_derive_timing() local 703 divider = DIV_ROUND_UP(clk, speed); in mxs_i2c_derive_timing() 705 if (divider < 25) { in mxs_i2c_derive_timing() 710 divider = 25; in mxs_i2c_derive_timing() 714 clk / divider / 1000, clk / divider % 1000); in mxs_i2c_derive_timing() 715 } else if (divider > 1897) { in mxs_i2c_derive_timing() 720 divider = 1897; in mxs_i2c_derive_timing() 724 clk / divider / 1000, clk / divider % 1000); in mxs_i2c_derive_timing() 743 low_count = DIV_ROUND_CLOSEST(divider * 13, (13 + 6)); in mxs_i2c_derive_timing() 744 high_count = DIV_ROUND_CLOSEST(divider * 6, (13 + 6)); in mxs_i2c_derive_timing() [all …]
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D | i2c-bcm2835.c | 229 u32 bus_clk_rate, divider; in bcm2835_i2c_probe() local 259 divider = DIV_ROUND_UP(clk_get_rate(i2c_dev->clk), bus_clk_rate); in bcm2835_i2c_probe() 265 if (divider & 1) in bcm2835_i2c_probe() 266 divider++; in bcm2835_i2c_probe() 267 if ((divider < BCM2835_I2C_CDIV_MIN) || in bcm2835_i2c_probe() 268 (divider > BCM2835_I2C_CDIV_MAX)) { in bcm2835_i2c_probe() 272 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DIV, divider); in bcm2835_i2c_probe()
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D | i2c-mpc.c | 79 u16 divider; member 287 u32 divider; in mpc_i2c_get_fdr_52xx() local 297 divider = mpc5xxx_get_bus_frequency(node) / clock; in mpc_i2c_get_fdr_52xx() 308 if (div->divider >= divider) in mpc_i2c_get_fdr_52xx() 312 *real_clk = mpc5xxx_get_bus_frequency(node) / div->divider; in mpc_i2c_get_fdr_52xx() 461 u32 divider; in mpc_i2c_get_fdr_8xxx() local 476 divider = fsl_get_sys_freq() / clock / prescaler; in mpc_i2c_get_fdr_8xxx() 479 fsl_get_sys_freq(), clock, divider); in mpc_i2c_get_fdr_8xxx() 487 if (div->divider >= divider) in mpc_i2c_get_fdr_8xxx() 491 *real_clk = fsl_get_sys_freq() / prescaler / div->divider; in mpc_i2c_get_fdr_8xxx()
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/drivers/staging/comedi/drivers/ |
D | dt3000.c | 354 unsigned int divider, base, prescale; in dt3k_ns_to_timer() local 364 divider = (*nanosec + base / 2) / base; in dt3k_ns_to_timer() 367 divider = (*nanosec) / base; in dt3k_ns_to_timer() 370 divider = DIV_ROUND_UP(*nanosec, base); in dt3k_ns_to_timer() 373 if (divider < 65536) { in dt3k_ns_to_timer() 374 *nanosec = divider * base; in dt3k_ns_to_timer() 375 return (prescale << 16) | (divider); in dt3k_ns_to_timer() 381 divider = 65535; in dt3k_ns_to_timer() 382 *nanosec = divider * base; in dt3k_ns_to_timer() 383 return (prescale << 16) | (divider); in dt3k_ns_to_timer() [all …]
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/drivers/media/dvb-frontends/ |
D | stv6110.c | 241 u32 nbsteps, divider, psd2, freq; in stv6110_get_frequency() local 246 divider = (priv->regs[RSTV6110_TUNING2] & 0x0f) << 8; in stv6110_get_frequency() 247 divider += priv->regs[RSTV6110_TUNING1]; in stv6110_get_frequency() 254 freq = divider * (priv->mclk / 1000); in stv6110_get_frequency() 268 u32 divider, ref, p, presc, i, result_freq, vco_freq; in stv6110_set_frequency() local 324 divider = (((frequency * 1000) + (ref >> 1)) / ref); in stv6110_set_frequency() 332 priv->regs[RSTV6110_TUNING2] |= (((divider) >> 8) & 0x0f); in stv6110_set_frequency() 335 priv->regs[RSTV6110_TUNING1] = (divider & 0xff); in stv6110_set_frequency() 353 vco_freq = divider * ((priv->mclk / 1000) / ((1 << (r_div_opt + 1)))); in stv6110_set_frequency()
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/drivers/media/rc/ |
D | ir-xmp-decoder.c | 85 int divider, i; in ir_xmp_decode() local 103 divider = (n[3] - XMP_NIBBLE_PREFIX) / 15 - 2000; in ir_xmp_decode() 104 if (divider < 50) { in ir_xmp_decode() 105 IR_dprintk(2, "divider to small %d.\n", divider); in ir_xmp_decode() 112 n[i] = (n[i] - XMP_NIBBLE_PREFIX) / divider; in ir_xmp_decode()
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/drivers/clk/berlin/ |
D | berlin2-div.c | 191 u32 divsw, div3sw, divider = 1; in berlin2_div_recalc_rate() local 203 divider = 3; in berlin2_div_recalc_rate() 206 divider = 1; in berlin2_div_recalc_rate() 213 divider = clk_div[reg]; in berlin2_div_recalc_rate() 219 return parent_rate / divider; in berlin2_div_recalc_rate()
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D | berlin2-avpll.c | 266 u32 reg, div_av2, div_av3, divider = 1; in berlin2_avpll_channel_recalc_rate() local 282 divider = reg & VCO_SYNC1_MASK; in berlin2_avpll_channel_recalc_rate() 298 divider *= div_hdmi[reg & 0x3]; in berlin2_avpll_channel_recalc_rate() 312 divider *= div_av1[reg & 0x3]; in berlin2_avpll_channel_recalc_rate() 329 divider *= div_av2; in berlin2_avpll_channel_recalc_rate() 347 do_div(freq, divider); in berlin2_avpll_channel_recalc_rate()
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/drivers/spi/ |
D | spi-orion.c | 141 unsigned divider = DIV_ROUND_UP(tclk_hz, speed); in orion_spi_baudrate_set() local 144 if (divider < 16) { in orion_spi_baudrate_set() 146 spr = divider; in orion_spi_baudrate_set() 157 sppr = fls(divider) - 4; in orion_spi_baudrate_set() 164 divider = (divider + two_pow_sppr - 1) & -two_pow_sppr; in orion_spi_baudrate_set() 173 sppr = fls(divider) - 4; in orion_spi_baudrate_set() 174 spr = divider >> sppr; in orion_spi_baudrate_set()
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/drivers/clk/sunxi/ |
D | clk-sunxi.c | 985 struct clk_divider *divider; in sunxi_divs_clk_setup() local 1054 divider = kzalloc(sizeof(*divider), GFP_KERNEL); in sunxi_divs_clk_setup() 1055 if (!divider) in sunxi_divs_clk_setup() 1060 divider->reg = reg; in sunxi_divs_clk_setup() 1061 divider->shift = data->div[i].shift; in sunxi_divs_clk_setup() 1062 divider->width = SUNXI_DIVISOR_WIDTH; in sunxi_divs_clk_setup() 1063 divider->flags = flags; in sunxi_divs_clk_setup() 1064 divider->lock = &clk_lock; in sunxi_divs_clk_setup() 1065 divider->table = data->div[i].table; in sunxi_divs_clk_setup() 1067 rate_hw = ÷r->hw; in sunxi_divs_clk_setup()
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