1 /*
2 * clk-xgene.c - AppliedMicro X-Gene Clock Interface
3 *
4 * Copyright (c) 2013, Applied Micro Circuits Corporation
5 * Author: Loc Ho <lho@apm.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 *
22 */
23 #include <linux/module.h>
24 #include <linux/spinlock.h>
25 #include <linux/io.h>
26 #include <linux/of.h>
27 #include <linux/clkdev.h>
28 #include <linux/clk-provider.h>
29 #include <linux/of_address.h>
30
31 /* Register SCU_PCPPLL bit fields */
32 #define N_DIV_RD(src) (((src) & 0x000001ff))
33
34 /* Register SCU_SOCPLL bit fields */
35 #define CLKR_RD(src) (((src) & 0x07000000)>>24)
36 #define CLKOD_RD(src) (((src) & 0x00300000)>>20)
37 #define REGSPEC_RESET_F1_MASK 0x00010000
38 #define CLKF_RD(src) (((src) & 0x000001ff))
39
40 #define XGENE_CLK_DRIVER_VER "0.1"
41
42 static DEFINE_SPINLOCK(clk_lock);
43
xgene_clk_read(void __iomem * csr)44 static inline u32 xgene_clk_read(void __iomem *csr)
45 {
46 return readl_relaxed(csr);
47 }
48
xgene_clk_write(u32 data,void __iomem * csr)49 static inline void xgene_clk_write(u32 data, void __iomem *csr)
50 {
51 return writel_relaxed(data, csr);
52 }
53
54 /* PLL Clock */
55 enum xgene_pll_type {
56 PLL_TYPE_PCP = 0,
57 PLL_TYPE_SOC = 1,
58 };
59
60 struct xgene_clk_pll {
61 struct clk_hw hw;
62 void __iomem *reg;
63 spinlock_t *lock;
64 u32 pll_offset;
65 enum xgene_pll_type type;
66 };
67
68 #define to_xgene_clk_pll(_hw) container_of(_hw, struct xgene_clk_pll, hw)
69
xgene_clk_pll_is_enabled(struct clk_hw * hw)70 static int xgene_clk_pll_is_enabled(struct clk_hw *hw)
71 {
72 struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw);
73 u32 data;
74
75 data = xgene_clk_read(pllclk->reg + pllclk->pll_offset);
76 pr_debug("%s pll %s\n", clk_hw_get_name(hw),
77 data & REGSPEC_RESET_F1_MASK ? "disabled" : "enabled");
78
79 return data & REGSPEC_RESET_F1_MASK ? 0 : 1;
80 }
81
xgene_clk_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)82 static unsigned long xgene_clk_pll_recalc_rate(struct clk_hw *hw,
83 unsigned long parent_rate)
84 {
85 struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw);
86 unsigned long fref;
87 unsigned long fvco;
88 u32 pll;
89 u32 nref;
90 u32 nout;
91 u32 nfb;
92
93 pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset);
94
95 if (pllclk->type == PLL_TYPE_PCP) {
96 /*
97 * PLL VCO = Reference clock * NF
98 * PCP PLL = PLL_VCO / 2
99 */
100 nout = 2;
101 fvco = parent_rate * (N_DIV_RD(pll) + 4);
102 } else {
103 /*
104 * Fref = Reference Clock / NREF;
105 * Fvco = Fref * NFB;
106 * Fout = Fvco / NOUT;
107 */
108 nref = CLKR_RD(pll) + 1;
109 nout = CLKOD_RD(pll) + 1;
110 nfb = CLKF_RD(pll);
111 fref = parent_rate / nref;
112 fvco = fref * nfb;
113 }
114 pr_debug("%s pll recalc rate %ld parent %ld\n", clk_hw_get_name(hw),
115 fvco / nout, parent_rate);
116
117 return fvco / nout;
118 }
119
120 static const struct clk_ops xgene_clk_pll_ops = {
121 .is_enabled = xgene_clk_pll_is_enabled,
122 .recalc_rate = xgene_clk_pll_recalc_rate,
123 };
124
xgene_register_clk_pll(struct device * dev,const char * name,const char * parent_name,unsigned long flags,void __iomem * reg,u32 pll_offset,u32 type,spinlock_t * lock)125 static struct clk *xgene_register_clk_pll(struct device *dev,
126 const char *name, const char *parent_name,
127 unsigned long flags, void __iomem *reg, u32 pll_offset,
128 u32 type, spinlock_t *lock)
129 {
130 struct xgene_clk_pll *apmclk;
131 struct clk *clk;
132 struct clk_init_data init;
133
134 /* allocate the APM clock structure */
135 apmclk = kzalloc(sizeof(*apmclk), GFP_KERNEL);
136 if (!apmclk) {
137 pr_err("%s: could not allocate APM clk\n", __func__);
138 return ERR_PTR(-ENOMEM);
139 }
140
141 init.name = name;
142 init.ops = &xgene_clk_pll_ops;
143 init.flags = flags;
144 init.parent_names = parent_name ? &parent_name : NULL;
145 init.num_parents = parent_name ? 1 : 0;
146
147 apmclk->reg = reg;
148 apmclk->lock = lock;
149 apmclk->pll_offset = pll_offset;
150 apmclk->type = type;
151 apmclk->hw.init = &init;
152
153 /* Register the clock */
154 clk = clk_register(dev, &apmclk->hw);
155 if (IS_ERR(clk)) {
156 pr_err("%s: could not register clk %s\n", __func__, name);
157 kfree(apmclk);
158 return NULL;
159 }
160 return clk;
161 }
162
xgene_pllclk_init(struct device_node * np,enum xgene_pll_type pll_type)163 static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_type)
164 {
165 const char *clk_name = np->full_name;
166 struct clk *clk;
167 void __iomem *reg;
168
169 reg = of_iomap(np, 0);
170 if (reg == NULL) {
171 pr_err("Unable to map CSR register for %s\n", np->full_name);
172 return;
173 }
174 of_property_read_string(np, "clock-output-names", &clk_name);
175 clk = xgene_register_clk_pll(NULL,
176 clk_name, of_clk_get_parent_name(np, 0),
177 CLK_IS_ROOT, reg, 0, pll_type, &clk_lock);
178 if (!IS_ERR(clk)) {
179 of_clk_add_provider(np, of_clk_src_simple_get, clk);
180 clk_register_clkdev(clk, clk_name, NULL);
181 pr_debug("Add %s clock PLL\n", clk_name);
182 }
183 }
184
xgene_socpllclk_init(struct device_node * np)185 static void xgene_socpllclk_init(struct device_node *np)
186 {
187 xgene_pllclk_init(np, PLL_TYPE_SOC);
188 }
189
xgene_pcppllclk_init(struct device_node * np)190 static void xgene_pcppllclk_init(struct device_node *np)
191 {
192 xgene_pllclk_init(np, PLL_TYPE_PCP);
193 }
194
195 /* IP Clock */
196 struct xgene_dev_parameters {
197 void __iomem *csr_reg; /* CSR for IP clock */
198 u32 reg_clk_offset; /* Offset to clock enable CSR */
199 u32 reg_clk_mask; /* Mask bit for clock enable */
200 u32 reg_csr_offset; /* Offset to CSR reset */
201 u32 reg_csr_mask; /* Mask bit for disable CSR reset */
202 void __iomem *divider_reg; /* CSR for divider */
203 u32 reg_divider_offset; /* Offset to divider register */
204 u32 reg_divider_shift; /* Bit shift to divider field */
205 u32 reg_divider_width; /* Width of the bit to divider field */
206 };
207
208 struct xgene_clk {
209 struct clk_hw hw;
210 spinlock_t *lock;
211 struct xgene_dev_parameters param;
212 };
213
214 #define to_xgene_clk(_hw) container_of(_hw, struct xgene_clk, hw)
215
xgene_clk_enable(struct clk_hw * hw)216 static int xgene_clk_enable(struct clk_hw *hw)
217 {
218 struct xgene_clk *pclk = to_xgene_clk(hw);
219 unsigned long flags = 0;
220 u32 data;
221
222 if (pclk->lock)
223 spin_lock_irqsave(pclk->lock, flags);
224
225 if (pclk->param.csr_reg != NULL) {
226 pr_debug("%s clock enabled\n", clk_hw_get_name(hw));
227 /* First enable the clock */
228 data = xgene_clk_read(pclk->param.csr_reg +
229 pclk->param.reg_clk_offset);
230 data |= pclk->param.reg_clk_mask;
231 xgene_clk_write(data, pclk->param.csr_reg +
232 pclk->param.reg_clk_offset);
233 pr_debug("%s clk offset 0x%08X mask 0x%08X value 0x%08X\n",
234 clk_hw_get_name(hw),
235 pclk->param.reg_clk_offset, pclk->param.reg_clk_mask,
236 data);
237
238 /* Second enable the CSR */
239 data = xgene_clk_read(pclk->param.csr_reg +
240 pclk->param.reg_csr_offset);
241 data &= ~pclk->param.reg_csr_mask;
242 xgene_clk_write(data, pclk->param.csr_reg +
243 pclk->param.reg_csr_offset);
244 pr_debug("%s csr offset 0x%08X mask 0x%08X value 0x%08X\n",
245 clk_hw_get_name(hw),
246 pclk->param.reg_csr_offset, pclk->param.reg_csr_mask,
247 data);
248 }
249
250 if (pclk->lock)
251 spin_unlock_irqrestore(pclk->lock, flags);
252
253 return 0;
254 }
255
xgene_clk_disable(struct clk_hw * hw)256 static void xgene_clk_disable(struct clk_hw *hw)
257 {
258 struct xgene_clk *pclk = to_xgene_clk(hw);
259 unsigned long flags = 0;
260 u32 data;
261
262 if (pclk->lock)
263 spin_lock_irqsave(pclk->lock, flags);
264
265 if (pclk->param.csr_reg != NULL) {
266 pr_debug("%s clock disabled\n", clk_hw_get_name(hw));
267 /* First put the CSR in reset */
268 data = xgene_clk_read(pclk->param.csr_reg +
269 pclk->param.reg_csr_offset);
270 data |= pclk->param.reg_csr_mask;
271 xgene_clk_write(data, pclk->param.csr_reg +
272 pclk->param.reg_csr_offset);
273
274 /* Second disable the clock */
275 data = xgene_clk_read(pclk->param.csr_reg +
276 pclk->param.reg_clk_offset);
277 data &= ~pclk->param.reg_clk_mask;
278 xgene_clk_write(data, pclk->param.csr_reg +
279 pclk->param.reg_clk_offset);
280 }
281
282 if (pclk->lock)
283 spin_unlock_irqrestore(pclk->lock, flags);
284 }
285
xgene_clk_is_enabled(struct clk_hw * hw)286 static int xgene_clk_is_enabled(struct clk_hw *hw)
287 {
288 struct xgene_clk *pclk = to_xgene_clk(hw);
289 u32 data = 0;
290
291 if (pclk->param.csr_reg != NULL) {
292 pr_debug("%s clock checking\n", clk_hw_get_name(hw));
293 data = xgene_clk_read(pclk->param.csr_reg +
294 pclk->param.reg_clk_offset);
295 pr_debug("%s clock is %s\n", clk_hw_get_name(hw),
296 data & pclk->param.reg_clk_mask ? "enabled" :
297 "disabled");
298 }
299
300 if (pclk->param.csr_reg == NULL)
301 return 1;
302 return data & pclk->param.reg_clk_mask ? 1 : 0;
303 }
304
xgene_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)305 static unsigned long xgene_clk_recalc_rate(struct clk_hw *hw,
306 unsigned long parent_rate)
307 {
308 struct xgene_clk *pclk = to_xgene_clk(hw);
309 u32 data;
310
311 if (pclk->param.divider_reg) {
312 data = xgene_clk_read(pclk->param.divider_reg +
313 pclk->param.reg_divider_offset);
314 data >>= pclk->param.reg_divider_shift;
315 data &= (1 << pclk->param.reg_divider_width) - 1;
316
317 pr_debug("%s clock recalc rate %ld parent %ld\n",
318 clk_hw_get_name(hw),
319 parent_rate / data, parent_rate);
320
321 return parent_rate / data;
322 } else {
323 pr_debug("%s clock recalc rate %ld parent %ld\n",
324 clk_hw_get_name(hw), parent_rate, parent_rate);
325 return parent_rate;
326 }
327 }
328
xgene_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)329 static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate,
330 unsigned long parent_rate)
331 {
332 struct xgene_clk *pclk = to_xgene_clk(hw);
333 unsigned long flags = 0;
334 u32 data;
335 u32 divider;
336 u32 divider_save;
337
338 if (pclk->lock)
339 spin_lock_irqsave(pclk->lock, flags);
340
341 if (pclk->param.divider_reg) {
342 /* Let's compute the divider */
343 if (rate > parent_rate)
344 rate = parent_rate;
345 divider_save = divider = parent_rate / rate; /* Rounded down */
346 divider &= (1 << pclk->param.reg_divider_width) - 1;
347 divider <<= pclk->param.reg_divider_shift;
348
349 /* Set new divider */
350 data = xgene_clk_read(pclk->param.divider_reg +
351 pclk->param.reg_divider_offset);
352 data &= ~(((1 << pclk->param.reg_divider_width) - 1)
353 << pclk->param.reg_divider_shift);
354 data |= divider;
355 xgene_clk_write(data, pclk->param.divider_reg +
356 pclk->param.reg_divider_offset);
357 pr_debug("%s clock set rate %ld\n", clk_hw_get_name(hw),
358 parent_rate / divider_save);
359 } else {
360 divider_save = 1;
361 }
362
363 if (pclk->lock)
364 spin_unlock_irqrestore(pclk->lock, flags);
365
366 return parent_rate / divider_save;
367 }
368
xgene_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)369 static long xgene_clk_round_rate(struct clk_hw *hw, unsigned long rate,
370 unsigned long *prate)
371 {
372 struct xgene_clk *pclk = to_xgene_clk(hw);
373 unsigned long parent_rate = *prate;
374 u32 divider;
375
376 if (pclk->param.divider_reg) {
377 /* Let's compute the divider */
378 if (rate > parent_rate)
379 rate = parent_rate;
380 divider = parent_rate / rate; /* Rounded down */
381 } else {
382 divider = 1;
383 }
384
385 return parent_rate / divider;
386 }
387
388 static const struct clk_ops xgene_clk_ops = {
389 .enable = xgene_clk_enable,
390 .disable = xgene_clk_disable,
391 .is_enabled = xgene_clk_is_enabled,
392 .recalc_rate = xgene_clk_recalc_rate,
393 .set_rate = xgene_clk_set_rate,
394 .round_rate = xgene_clk_round_rate,
395 };
396
xgene_register_clk(struct device * dev,const char * name,const char * parent_name,struct xgene_dev_parameters * parameters,spinlock_t * lock)397 static struct clk *xgene_register_clk(struct device *dev,
398 const char *name, const char *parent_name,
399 struct xgene_dev_parameters *parameters, spinlock_t *lock)
400 {
401 struct xgene_clk *apmclk;
402 struct clk *clk;
403 struct clk_init_data init;
404 int rc;
405
406 /* allocate the APM clock structure */
407 apmclk = kzalloc(sizeof(*apmclk), GFP_KERNEL);
408 if (!apmclk) {
409 pr_err("%s: could not allocate APM clk\n", __func__);
410 return ERR_PTR(-ENOMEM);
411 }
412
413 init.name = name;
414 init.ops = &xgene_clk_ops;
415 init.flags = 0;
416 init.parent_names = parent_name ? &parent_name : NULL;
417 init.num_parents = parent_name ? 1 : 0;
418
419 apmclk->lock = lock;
420 apmclk->hw.init = &init;
421 apmclk->param = *parameters;
422
423 /* Register the clock */
424 clk = clk_register(dev, &apmclk->hw);
425 if (IS_ERR(clk)) {
426 pr_err("%s: could not register clk %s\n", __func__, name);
427 kfree(apmclk);
428 return clk;
429 }
430
431 /* Register the clock for lookup */
432 rc = clk_register_clkdev(clk, name, NULL);
433 if (rc != 0) {
434 pr_err("%s: could not register lookup clk %s\n",
435 __func__, name);
436 }
437 return clk;
438 }
439
xgene_devclk_init(struct device_node * np)440 static void __init xgene_devclk_init(struct device_node *np)
441 {
442 const char *clk_name = np->full_name;
443 struct clk *clk;
444 struct resource res;
445 int rc;
446 struct xgene_dev_parameters parameters;
447 int i;
448
449 /* Check if the entry is disabled */
450 if (!of_device_is_available(np))
451 return;
452
453 /* Parse the DTS register for resource */
454 parameters.csr_reg = NULL;
455 parameters.divider_reg = NULL;
456 for (i = 0; i < 2; i++) {
457 void __iomem *map_res;
458 rc = of_address_to_resource(np, i, &res);
459 if (rc != 0) {
460 if (i == 0) {
461 pr_err("no DTS register for %s\n",
462 np->full_name);
463 return;
464 }
465 break;
466 }
467 map_res = of_iomap(np, i);
468 if (map_res == NULL) {
469 pr_err("Unable to map resource %d for %s\n",
470 i, np->full_name);
471 goto err;
472 }
473 if (strcmp(res.name, "div-reg") == 0)
474 parameters.divider_reg = map_res;
475 else /* if (strcmp(res->name, "csr-reg") == 0) */
476 parameters.csr_reg = map_res;
477 }
478 if (of_property_read_u32(np, "csr-offset", ¶meters.reg_csr_offset))
479 parameters.reg_csr_offset = 0;
480 if (of_property_read_u32(np, "csr-mask", ¶meters.reg_csr_mask))
481 parameters.reg_csr_mask = 0xF;
482 if (of_property_read_u32(np, "enable-offset",
483 ¶meters.reg_clk_offset))
484 parameters.reg_clk_offset = 0x8;
485 if (of_property_read_u32(np, "enable-mask", ¶meters.reg_clk_mask))
486 parameters.reg_clk_mask = 0xF;
487 if (of_property_read_u32(np, "divider-offset",
488 ¶meters.reg_divider_offset))
489 parameters.reg_divider_offset = 0;
490 if (of_property_read_u32(np, "divider-width",
491 ¶meters.reg_divider_width))
492 parameters.reg_divider_width = 0;
493 if (of_property_read_u32(np, "divider-shift",
494 ¶meters.reg_divider_shift))
495 parameters.reg_divider_shift = 0;
496 of_property_read_string(np, "clock-output-names", &clk_name);
497
498 clk = xgene_register_clk(NULL, clk_name,
499 of_clk_get_parent_name(np, 0), ¶meters, &clk_lock);
500 if (IS_ERR(clk))
501 goto err;
502 pr_debug("Add %s clock\n", clk_name);
503 rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
504 if (rc != 0)
505 pr_err("%s: could register provider clk %s\n", __func__,
506 np->full_name);
507
508 return;
509
510 err:
511 if (parameters.csr_reg)
512 iounmap(parameters.csr_reg);
513 if (parameters.divider_reg)
514 iounmap(parameters.divider_reg);
515 }
516
517 CLK_OF_DECLARE(xgene_socpll_clock, "apm,xgene-socpll-clock", xgene_socpllclk_init);
518 CLK_OF_DECLARE(xgene_pcppll_clock, "apm,xgene-pcppll-clock", xgene_pcppllclk_init);
519 CLK_OF_DECLARE(xgene_dev_clock, "apm,xgene-device-clock", xgene_devclk_init);
520