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Searched refs:gpu_addr (Results 1 – 25 of 97) sorted by relevance

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/drivers/gpu/drm/radeon/
Dr600_dma.c144 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF); in r600_dma_resume()
146 ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC)); in r600_dma_resume()
151 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8); in r600_dma_resume()
237 u64 gpu_addr; in r600_dma_ring_test() local
244 gpu_addr = rdev->wb.gpu_addr + index; in r600_dma_ring_test()
255 radeon_ring_write(ring, lower_32_bits(gpu_addr)); in r600_dma_ring_test()
256 radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff); in r600_dma_ring_test()
291 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in r600_dma_fence_ring_emit()
318 u64 addr = semaphore->gpu_addr; in r600_dma_semaphore_ring_emit()
344 u64 gpu_addr; in r600_dma_ib_test() local
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Dcik_sdma.c155 radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ in cik_sdma_ring_ib_execute()
156 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); in cik_sdma_ring_ib_execute()
204 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in cik_sdma_fence_ring_emit()
233 u64 addr = semaphore->gpu_addr; in cik_sdma_semaphore_ring_emit()
401 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); in cik_sdma_gfx_resume()
403 ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); in cik_sdma_gfx_resume()
408 WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8); in cik_sdma_gfx_resume()
409 WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40); in cik_sdma_gfx_resume()
652 u64 gpu_addr; in cik_sdma_ring_test() local
659 gpu_addr = rdev->wb.gpu_addr + index; in cik_sdma_ring_test()
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Dr600_blit.c77 set_render_target(drm_radeon_private_t *dev_priv, int format, int w, int h, u64 gpu_addr) in set_render_target() argument
97 OUT_RING(gpu_addr >> 8); in set_render_target()
104 OUT_RING(gpu_addr >> 8); in set_render_target()
160 u64 gpu_addr; in set_shaders() local
178 gpu_addr = dev_priv->gart_buffers_offset + dev_priv->blit_vb->offset; in set_shaders()
187 OUT_RING(gpu_addr >> 8); in set_shaders()
200 OUT_RING((gpu_addr + 256) >> 8); in set_shaders()
216 R600_SH_ACTION_ENA, 512, gpu_addr); in set_shaders()
220 set_vtx_resource(drm_radeon_private_t *dev_priv, u64 gpu_addr) in set_vtx_resource() argument
226 sq_vtx_constant_word2 = (((gpu_addr >> 32) & 0xff) | (16 << 8)); in set_vtx_resource()
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Duvd_v2_2.c43 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; in uvd_v2_2_fence_emit()
77 uint64_t addr = semaphore->gpu_addr; in uvd_v2_2_semaphore_emit()
113 addr = rdev->uvd.gpu_addr >> 3; in uvd_v2_2_resume()
129 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v2_2_resume()
133 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v2_2_resume()
Duvd_v4_2.c44 addr = rdev->uvd.gpu_addr >> 3; in uvd_v4_2_resume()
60 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v4_2_resume()
64 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v4_2_resume()
Duvd_v1_0.c85 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; in uvd_v1_0_fence_emit()
121 addr = (rdev->uvd.gpu_addr >> 3) + 16; in uvd_v1_0_resume()
137 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v1_0_resume()
141 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v1_0_resume()
363 WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | in uvd_v1_0_start()
373 WREG32(UVD_RBC_RB_BASE, ring->gpu_addr); in uvd_v1_0_start()
486 radeon_ring_write(ring, ib->gpu_addr); in uvd_v1_0_ib_execute()
Dradeon_semaphore.c51 (*semaphore)->gpu_addr = radeon_sa_bo_gpu_addr((*semaphore)->sa_bo); in radeon_semaphore_create()
69 ring->last_semaphore_signal_addr = semaphore->gpu_addr; in radeon_semaphore_emit_signal()
86 ring->last_semaphore_wait_addr = semaphore->gpu_addr; in radeon_semaphore_emit_wait()
Dvce_v1_0.c218 uint64_t addr = rdev->vce.gpu_addr; in vce_v1_0_resume()
300 WREG32(VCE_RB_BASE_LO, ring->gpu_addr); in vce_v1_0_start()
301 WREG32(VCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vce_v1_0_start()
307 WREG32(VCE_RB_BASE_LO2, ring->gpu_addr); in vce_v1_0_start()
308 WREG32(VCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vce_v1_0_start()
Dradeon_trace.h176 __field(uint64_t, gpu_addr)
182 __entry->gpu_addr = sem->gpu_addr;
186 __entry->waiters, __entry->gpu_addr)
Devergreen_dma.c45 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in evergreen_dma_fence_ring_emit()
89 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in evergreen_dma_ring_ib_execute()
90 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in evergreen_dma_ring_ib_execute()
Dni_dma.c145 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in cayman_dma_ring_ib_execute()
146 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in cayman_dma_ring_ib_execute()
223 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF); in cayman_dma_resume()
225 ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); in cayman_dma_resume()
230 WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8); in cayman_dma_resume()
Dradeon_object.h135 extern int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr);
137 u64 max_offset, u64 *gpu_addr);
165 return sa_bo->manager->gpu_addr + sa_bo->soffset; in radeon_sa_bo_gpu_addr()
/drivers/gpu/drm/amd/amdgpu/
Damdgpu_amdkfd.c170 void **mem_obj, uint64_t *gpu_addr, in alloc_gtt_mem() argument
178 BUG_ON(gpu_addr == NULL); in alloc_gtt_mem()
201 &(*mem)->gpu_addr); in alloc_gtt_mem()
206 *gpu_addr = (*mem)->gpu_addr; in alloc_gtt_mem()
Damdgpu_semaphore.c51 (*semaphore)->gpu_addr = amdgpu_sa_bo_gpu_addr((*semaphore)->sa_bo); in amdgpu_semaphore_create()
67 ring->last_semaphore_signal_addr = semaphore->gpu_addr; in amdgpu_semaphore_emit_signal()
82 ring->last_semaphore_wait_addr = semaphore->gpu_addr; in amdgpu_semaphore_emit_wait()
Dcik_sdma.c233 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ in cik_sdma_ring_emit_ib()
234 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); in cik_sdma_ring_emit_ib()
312 u64 addr = semaphore->gpu_addr; in cik_sdma_ring_emit_semaphore()
439 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); in cik_sdma_gfx_resume()
441 ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); in cik_sdma_gfx_resume()
445 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); in cik_sdma_gfx_resume()
446 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); in cik_sdma_gfx_resume()
576 u64 gpu_addr; in cik_sdma_ring_test_ring() local
584 gpu_addr = adev->wb.gpu_addr + (index * 4); in cik_sdma_ring_test_ring()
595 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in cik_sdma_ring_test_ring()
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Dsdma_v2_4.c268 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v2_4_ring_emit_ib()
269 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v2_4_ring_emit_ib()
351 u64 addr = semaphore->gpu_addr; in sdma_v2_4_ring_emit_semaphore()
481 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); in sdma_v2_4_gfx_resume()
483 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); in sdma_v2_4_gfx_resume()
487 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); in sdma_v2_4_gfx_resume()
488 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); in sdma_v2_4_gfx_resume()
627 u64 gpu_addr; in sdma_v2_4_ring_test_ring() local
635 gpu_addr = adev->wb.gpu_addr + (index * 4); in sdma_v2_4_ring_test_ring()
648 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in sdma_v2_4_ring_test_ring()
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Dvce_v3_0.c190 WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr); in vce_v3_0_start()
191 WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vce_v3_0_start()
197 WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr); in vce_v3_0_start()
198 WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vce_v3_0_start()
400 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8)); in vce_v3_0_mc_resume()
401 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8)); in vce_v3_0_mc_resume()
402 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR2, (adev->vce.gpu_addr >> 8)); in vce_v3_0_mc_resume()
404 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8)); in vce_v3_0_mc_resume()
Dsdma_v3_0.c378 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v3_0_ring_emit_ib()
379 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v3_0_ring_emit_ib()
462 u64 addr = semaphore->gpu_addr; in sdma_v3_0_ring_emit_semaphore()
618 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); in sdma_v3_0_gfx_resume()
620 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); in sdma_v3_0_gfx_resume()
624 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); in sdma_v3_0_gfx_resume()
625 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); in sdma_v3_0_gfx_resume()
777 u64 gpu_addr; in sdma_v3_0_ring_test_ring() local
785 gpu_addr = adev->wb.gpu_addr + (index * 4); in sdma_v3_0_ring_test_ring()
798 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in sdma_v3_0_ring_test_ring()
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Damdgpu_fence.c117 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, in amdgpu_fence_emit()
443 ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4); in amdgpu_fence_driver_start_ring()
448 ring->fence_drv.gpu_addr = adev->uvd.gpu_addr + index; in amdgpu_fence_driver_start_ring()
459 ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr); in amdgpu_fence_driver_start_ring()
477 ring->fence_drv.gpu_addr = 0; in amdgpu_fence_driver_init_ring()
Duvd_v5_0.c264 lower_32_bits(adev->uvd.gpu_addr)); in uvd_v5_0_mc_resume()
266 upper_32_bits(adev->uvd.gpu_addr)); in uvd_v5_0_mc_resume()
409 WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); in uvd_v5_0_start()
413 lower_32_bits(ring->gpu_addr)); in uvd_v5_0_start()
415 upper_32_bits(ring->gpu_addr)); in uvd_v5_0_start()
498 uint64_t addr = semaphore->gpu_addr; in uvd_v5_0_ring_emit_semaphore()
566 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in uvd_v5_0_ring_emit_ib()
568 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in uvd_v5_0_ring_emit_ib()
Duvd_v6_0.c262 lower_32_bits(adev->uvd.gpu_addr)); in uvd_v6_0_mc_resume()
264 upper_32_bits(adev->uvd.gpu_addr)); in uvd_v6_0_mc_resume()
409 WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); in uvd_v6_0_start()
413 lower_32_bits(ring->gpu_addr)); in uvd_v6_0_start()
415 upper_32_bits(ring->gpu_addr)); in uvd_v6_0_start()
498 uint64_t addr = semaphore->gpu_addr; in uvd_v6_0_ring_emit_semaphore()
566 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in uvd_v6_0_ring_emit_ib()
568 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in uvd_v6_0_ring_emit_ib()
Damdgpu_amdkfd.h35 uint64_t gpu_addr; member
57 void **mem_obj, uint64_t *gpu_addr,
/drivers/gpu/drm/mgag200/
Dmgag200_cursor.c53 u64 gpu_addr; in mga_crtc_cursor_set() local
218 gpu_addr = mdev->cursor.pixels_1_gpu_addr; in mga_crtc_cursor_set()
220 gpu_addr = mdev->cursor.pixels_2_gpu_addr; in mga_crtc_cursor_set()
221 WREG_DAC(MGA1064_CURSOR_BASE_ADR_LOW, (u8)((gpu_addr>>10) & 0xff)); in mga_crtc_cursor_set()
222 WREG_DAC(MGA1064_CURSOR_BASE_ADR_HI, (u8)((gpu_addr>>18) & 0x3f)); in mga_crtc_cursor_set()
/drivers/gpu/drm/qxl/
Dqxl_object.c224 int qxl_bo_pin(struct qxl_bo *bo, u32 domain, u64 *gpu_addr) in qxl_bo_pin() argument
231 if (gpu_addr) in qxl_bo_pin()
232 *gpu_addr = qxl_bo_gpu_offset(bo); in qxl_bo_pin()
239 if (gpu_addr != NULL) in qxl_bo_pin()
240 *gpu_addr = qxl_bo_gpu_offset(bo); in qxl_bo_pin()
/drivers/gpu/drm/ast/
Dast_mode.c517 u64 gpu_addr; in ast_crtc_do_set_base() local
539 ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr); in ast_crtc_do_set_base()
551 ast_fbdev_set_base(ast, gpu_addr); in ast_crtc_do_set_base()
556 ast_set_start_address_crt1(crtc, (u32)gpu_addr); in ast_crtc_do_set_base()
916 uint64_t gpu_addr; in ast_cursor_init() local
928 ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr); in ast_cursor_init()
939 ast->cursor_cache_gpu_addr = gpu_addr; in ast_cursor_init()
1171 uint64_t gpu_addr; in ast_cursor_set() local
1223 gpu_addr = ast->cursor_cache_gpu_addr; in ast_cursor_set()
1224 gpu_addr += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor; in ast_cursor_set()
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