1 /*
2 * Copyright 2012 Red Hat Inc.
3 * Parts based on xf86-video-ast
4 * Copyright (c) 2005 ASPEED Technology Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 *
26 */
27 /*
28 * Authors: Dave Airlie <airlied@redhat.com>
29 */
30 #include <linux/export.h>
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_plane_helper.h>
35 #include "ast_drv.h"
36
37 #include "ast_tables.h"
38
39 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev);
40 static void ast_i2c_destroy(struct ast_i2c_chan *i2c);
41 static int ast_cursor_set(struct drm_crtc *crtc,
42 struct drm_file *file_priv,
43 uint32_t handle,
44 uint32_t width,
45 uint32_t height);
46 static int ast_cursor_move(struct drm_crtc *crtc,
47 int x, int y);
48
ast_load_palette_index(struct ast_private * ast,u8 index,u8 red,u8 green,u8 blue)49 static inline void ast_load_palette_index(struct ast_private *ast,
50 u8 index, u8 red, u8 green,
51 u8 blue)
52 {
53 ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index);
54 ast_io_read8(ast, AST_IO_SEQ_PORT);
55 ast_io_write8(ast, AST_IO_DAC_DATA, red);
56 ast_io_read8(ast, AST_IO_SEQ_PORT);
57 ast_io_write8(ast, AST_IO_DAC_DATA, green);
58 ast_io_read8(ast, AST_IO_SEQ_PORT);
59 ast_io_write8(ast, AST_IO_DAC_DATA, blue);
60 ast_io_read8(ast, AST_IO_SEQ_PORT);
61 }
62
ast_crtc_load_lut(struct drm_crtc * crtc)63 static void ast_crtc_load_lut(struct drm_crtc *crtc)
64 {
65 struct ast_private *ast = crtc->dev->dev_private;
66 struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
67 int i;
68
69 if (!crtc->enabled)
70 return;
71
72 for (i = 0; i < 256; i++)
73 ast_load_palette_index(ast, i, ast_crtc->lut_r[i],
74 ast_crtc->lut_g[i], ast_crtc->lut_b[i]);
75 }
76
ast_get_vbios_mode_info(struct drm_crtc * crtc,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode,struct ast_vbios_mode_info * vbios_mode)77 static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mode *mode,
78 struct drm_display_mode *adjusted_mode,
79 struct ast_vbios_mode_info *vbios_mode)
80 {
81 struct ast_private *ast = crtc->dev->dev_private;
82 u32 refresh_rate_index = 0, mode_id, color_index, refresh_rate;
83 u32 hborder, vborder;
84 bool check_sync;
85 struct ast_vbios_enhtable *best = NULL;
86
87 switch (crtc->primary->fb->bits_per_pixel) {
88 case 8:
89 vbios_mode->std_table = &vbios_stdtable[VGAModeIndex];
90 color_index = VGAModeIndex - 1;
91 break;
92 case 16:
93 vbios_mode->std_table = &vbios_stdtable[HiCModeIndex];
94 color_index = HiCModeIndex;
95 break;
96 case 24:
97 case 32:
98 vbios_mode->std_table = &vbios_stdtable[TrueCModeIndex];
99 color_index = TrueCModeIndex;
100 break;
101 default:
102 return false;
103 }
104
105 switch (crtc->mode.crtc_hdisplay) {
106 case 640:
107 vbios_mode->enh_table = &res_640x480[refresh_rate_index];
108 break;
109 case 800:
110 vbios_mode->enh_table = &res_800x600[refresh_rate_index];
111 break;
112 case 1024:
113 vbios_mode->enh_table = &res_1024x768[refresh_rate_index];
114 break;
115 case 1280:
116 if (crtc->mode.crtc_vdisplay == 800)
117 vbios_mode->enh_table = &res_1280x800[refresh_rate_index];
118 else
119 vbios_mode->enh_table = &res_1280x1024[refresh_rate_index];
120 break;
121 case 1360:
122 vbios_mode->enh_table = &res_1360x768[refresh_rate_index];
123 break;
124 case 1440:
125 vbios_mode->enh_table = &res_1440x900[refresh_rate_index];
126 break;
127 case 1600:
128 if (crtc->mode.crtc_vdisplay == 900)
129 vbios_mode->enh_table = &res_1600x900[refresh_rate_index];
130 else
131 vbios_mode->enh_table = &res_1600x1200[refresh_rate_index];
132 break;
133 case 1680:
134 vbios_mode->enh_table = &res_1680x1050[refresh_rate_index];
135 break;
136 case 1920:
137 if (crtc->mode.crtc_vdisplay == 1080)
138 vbios_mode->enh_table = &res_1920x1080[refresh_rate_index];
139 else
140 vbios_mode->enh_table = &res_1920x1200[refresh_rate_index];
141 break;
142 default:
143 return false;
144 }
145
146 refresh_rate = drm_mode_vrefresh(mode);
147 check_sync = vbios_mode->enh_table->flags & WideScreenMode;
148 do {
149 struct ast_vbios_enhtable *loop = vbios_mode->enh_table;
150
151 while (loop->refresh_rate != 0xff) {
152 if ((check_sync) &&
153 (((mode->flags & DRM_MODE_FLAG_NVSYNC) &&
154 (loop->flags & PVSync)) ||
155 ((mode->flags & DRM_MODE_FLAG_PVSYNC) &&
156 (loop->flags & NVSync)) ||
157 ((mode->flags & DRM_MODE_FLAG_NHSYNC) &&
158 (loop->flags & PHSync)) ||
159 ((mode->flags & DRM_MODE_FLAG_PHSYNC) &&
160 (loop->flags & NHSync)))) {
161 loop++;
162 continue;
163 }
164 if (loop->refresh_rate <= refresh_rate
165 && (!best || loop->refresh_rate > best->refresh_rate))
166 best = loop;
167 loop++;
168 }
169 if (best || !check_sync)
170 break;
171 check_sync = 0;
172 } while (1);
173 if (best)
174 vbios_mode->enh_table = best;
175
176 hborder = (vbios_mode->enh_table->flags & HBorder) ? 8 : 0;
177 vborder = (vbios_mode->enh_table->flags & VBorder) ? 8 : 0;
178
179 adjusted_mode->crtc_htotal = vbios_mode->enh_table->ht;
180 adjusted_mode->crtc_hblank_start = vbios_mode->enh_table->hde + hborder;
181 adjusted_mode->crtc_hblank_end = vbios_mode->enh_table->ht - hborder;
182 adjusted_mode->crtc_hsync_start = vbios_mode->enh_table->hde + hborder +
183 vbios_mode->enh_table->hfp;
184 adjusted_mode->crtc_hsync_end = (vbios_mode->enh_table->hde + hborder +
185 vbios_mode->enh_table->hfp +
186 vbios_mode->enh_table->hsync);
187
188 adjusted_mode->crtc_vtotal = vbios_mode->enh_table->vt;
189 adjusted_mode->crtc_vblank_start = vbios_mode->enh_table->vde + vborder;
190 adjusted_mode->crtc_vblank_end = vbios_mode->enh_table->vt - vborder;
191 adjusted_mode->crtc_vsync_start = vbios_mode->enh_table->vde + vborder +
192 vbios_mode->enh_table->vfp;
193 adjusted_mode->crtc_vsync_end = (vbios_mode->enh_table->vde + vborder +
194 vbios_mode->enh_table->vfp +
195 vbios_mode->enh_table->vsync);
196
197 refresh_rate_index = vbios_mode->enh_table->refresh_rate_index;
198 mode_id = vbios_mode->enh_table->mode_id;
199
200 if (ast->chip == AST1180) {
201 /* TODO 1180 */
202 } else {
203 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0xf) << 4));
204 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff);
205 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff);
206
207 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
208 if (vbios_mode->enh_table->flags & NewModeInfo) {
209 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
210 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, crtc->primary->fb->bits_per_pixel);
211 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000);
212 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay);
213 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8);
214
215 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay);
216 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8);
217 }
218 }
219
220 return true;
221
222
223 }
ast_set_std_reg(struct drm_crtc * crtc,struct drm_display_mode * mode,struct ast_vbios_mode_info * vbios_mode)224 static void ast_set_std_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
225 struct ast_vbios_mode_info *vbios_mode)
226 {
227 struct ast_private *ast = crtc->dev->dev_private;
228 struct ast_vbios_stdtable *stdtable;
229 u32 i;
230 u8 jreg;
231
232 stdtable = vbios_mode->std_table;
233
234 jreg = stdtable->misc;
235 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
236
237 /* Set SEQ */
238 ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03);
239 for (i = 0; i < 4; i++) {
240 jreg = stdtable->seq[i];
241 if (!i)
242 jreg |= 0x20;
243 ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1) , jreg);
244 }
245
246 /* Set CRTC */
247 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
248 for (i = 0; i < 25; i++)
249 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
250
251 /* set AR */
252 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
253 for (i = 0; i < 20; i++) {
254 jreg = stdtable->ar[i];
255 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i);
256 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg);
257 }
258 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14);
259 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00);
260
261 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
262 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20);
263
264 /* Set GR */
265 for (i = 0; i < 9; i++)
266 ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]);
267 }
268
ast_set_crtc_reg(struct drm_crtc * crtc,struct drm_display_mode * mode,struct ast_vbios_mode_info * vbios_mode)269 static void ast_set_crtc_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
270 struct ast_vbios_mode_info *vbios_mode)
271 {
272 struct ast_private *ast = crtc->dev->dev_private;
273 u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0;
274 u16 temp;
275
276 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
277
278 temp = (mode->crtc_htotal >> 3) - 5;
279 if (temp & 0x100)
280 jregAC |= 0x01; /* HT D[8] */
281 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp);
282
283 temp = (mode->crtc_hdisplay >> 3) - 1;
284 if (temp & 0x100)
285 jregAC |= 0x04; /* HDE D[8] */
286 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp);
287
288 temp = (mode->crtc_hblank_start >> 3) - 1;
289 if (temp & 0x100)
290 jregAC |= 0x10; /* HBS D[8] */
291 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp);
292
293 temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f;
294 if (temp & 0x20)
295 jreg05 |= 0x80; /* HBE D[5] */
296 if (temp & 0x40)
297 jregAD |= 0x01; /* HBE D[5] */
298 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f));
299
300 temp = (mode->crtc_hsync_start >> 3) - 1;
301 if (temp & 0x100)
302 jregAC |= 0x40; /* HRS D[5] */
303 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp);
304
305 temp = ((mode->crtc_hsync_end >> 3) - 1) & 0x3f;
306 if (temp & 0x20)
307 jregAD |= 0x04; /* HRE D[5] */
308 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05));
309
310 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC);
311 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD);
312
313 /* vert timings */
314 temp = (mode->crtc_vtotal) - 2;
315 if (temp & 0x100)
316 jreg07 |= 0x01;
317 if (temp & 0x200)
318 jreg07 |= 0x20;
319 if (temp & 0x400)
320 jregAE |= 0x01;
321 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp);
322
323 temp = (mode->crtc_vsync_start) - 1;
324 if (temp & 0x100)
325 jreg07 |= 0x04;
326 if (temp & 0x200)
327 jreg07 |= 0x80;
328 if (temp & 0x400)
329 jregAE |= 0x08;
330 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp);
331
332 temp = (mode->crtc_vsync_end - 1) & 0x3f;
333 if (temp & 0x10)
334 jregAE |= 0x20;
335 if (temp & 0x20)
336 jregAE |= 0x40;
337 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf);
338
339 temp = mode->crtc_vdisplay - 1;
340 if (temp & 0x100)
341 jreg07 |= 0x02;
342 if (temp & 0x200)
343 jreg07 |= 0x40;
344 if (temp & 0x400)
345 jregAE |= 0x02;
346 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp);
347
348 temp = mode->crtc_vblank_start - 1;
349 if (temp & 0x100)
350 jreg07 |= 0x08;
351 if (temp & 0x200)
352 jreg09 |= 0x20;
353 if (temp & 0x400)
354 jregAE |= 0x04;
355 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp);
356
357 temp = mode->crtc_vblank_end - 1;
358 if (temp & 0x100)
359 jregAE |= 0x10;
360 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp);
361
362 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07);
363 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09);
364 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80));
365
366 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80);
367 }
368
ast_set_offset_reg(struct drm_crtc * crtc)369 static void ast_set_offset_reg(struct drm_crtc *crtc)
370 {
371 struct ast_private *ast = crtc->dev->dev_private;
372
373 u16 offset;
374
375 offset = crtc->primary->fb->pitches[0] >> 3;
376 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff));
377 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f);
378 }
379
ast_set_dclk_reg(struct drm_device * dev,struct drm_display_mode * mode,struct ast_vbios_mode_info * vbios_mode)380 static void ast_set_dclk_reg(struct drm_device *dev, struct drm_display_mode *mode,
381 struct ast_vbios_mode_info *vbios_mode)
382 {
383 struct ast_private *ast = dev->dev_private;
384 struct ast_vbios_dclk_info *clk_info;
385
386 clk_info = &dclk_table[vbios_mode->enh_table->dclk_index];
387
388 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1);
389 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2);
390 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f,
391 (clk_info->param3 & 0x80) | ((clk_info->param3 & 0x3) << 4));
392 }
393
ast_set_ext_reg(struct drm_crtc * crtc,struct drm_display_mode * mode,struct ast_vbios_mode_info * vbios_mode)394 static void ast_set_ext_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
395 struct ast_vbios_mode_info *vbios_mode)
396 {
397 struct ast_private *ast = crtc->dev->dev_private;
398 u8 jregA0 = 0, jregA3 = 0, jregA8 = 0;
399
400 switch (crtc->primary->fb->bits_per_pixel) {
401 case 8:
402 jregA0 = 0x70;
403 jregA3 = 0x01;
404 jregA8 = 0x00;
405 break;
406 case 15:
407 case 16:
408 jregA0 = 0x70;
409 jregA3 = 0x04;
410 jregA8 = 0x02;
411 break;
412 case 32:
413 jregA0 = 0x70;
414 jregA3 = 0x08;
415 jregA8 = 0x02;
416 break;
417 }
418
419 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0);
420 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3);
421 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8);
422
423 /* Set Threshold */
424 if (ast->chip == AST2300 || ast->chip == AST2400) {
425 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78);
426 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60);
427 } else if (ast->chip == AST2100 ||
428 ast->chip == AST1100 ||
429 ast->chip == AST2200 ||
430 ast->chip == AST2150) {
431 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f);
432 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f);
433 } else {
434 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f);
435 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f);
436 }
437 }
438
ast_set_sync_reg(struct drm_device * dev,struct drm_display_mode * mode,struct ast_vbios_mode_info * vbios_mode)439 static void ast_set_sync_reg(struct drm_device *dev, struct drm_display_mode *mode,
440 struct ast_vbios_mode_info *vbios_mode)
441 {
442 struct ast_private *ast = dev->dev_private;
443 u8 jreg;
444
445 jreg = ast_io_read8(ast, AST_IO_MISC_PORT_READ);
446 jreg &= ~0xC0;
447 if (vbios_mode->enh_table->flags & NVSync) jreg |= 0x80;
448 if (vbios_mode->enh_table->flags & NHSync) jreg |= 0x40;
449 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
450 }
451
ast_set_dac_reg(struct drm_crtc * crtc,struct drm_display_mode * mode,struct ast_vbios_mode_info * vbios_mode)452 static bool ast_set_dac_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
453 struct ast_vbios_mode_info *vbios_mode)
454 {
455 switch (crtc->primary->fb->bits_per_pixel) {
456 case 8:
457 break;
458 default:
459 return false;
460 }
461 return true;
462 }
463
ast_set_start_address_crt1(struct drm_crtc * crtc,unsigned offset)464 static void ast_set_start_address_crt1(struct drm_crtc *crtc, unsigned offset)
465 {
466 struct ast_private *ast = crtc->dev->dev_private;
467 u32 addr;
468
469 addr = offset >> 2;
470 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff));
471 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff));
472 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff));
473
474 }
475
ast_crtc_dpms(struct drm_crtc * crtc,int mode)476 static void ast_crtc_dpms(struct drm_crtc *crtc, int mode)
477 {
478 struct ast_private *ast = crtc->dev->dev_private;
479
480 if (ast->chip == AST1180)
481 return;
482
483 switch (mode) {
484 case DRM_MODE_DPMS_ON:
485 case DRM_MODE_DPMS_STANDBY:
486 case DRM_MODE_DPMS_SUSPEND:
487 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0);
488 if (ast->tx_chip_type == AST_TX_DP501)
489 ast_set_dp501_video_output(crtc->dev, 1);
490 ast_crtc_load_lut(crtc);
491 break;
492 case DRM_MODE_DPMS_OFF:
493 if (ast->tx_chip_type == AST_TX_DP501)
494 ast_set_dp501_video_output(crtc->dev, 0);
495 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20);
496 break;
497 }
498 }
499
ast_crtc_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)500 static bool ast_crtc_mode_fixup(struct drm_crtc *crtc,
501 const struct drm_display_mode *mode,
502 struct drm_display_mode *adjusted_mode)
503 {
504 return true;
505 }
506
507 /* ast is different - we will force move buffers out of VRAM */
ast_crtc_do_set_base(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y,int atomic)508 static int ast_crtc_do_set_base(struct drm_crtc *crtc,
509 struct drm_framebuffer *fb,
510 int x, int y, int atomic)
511 {
512 struct ast_private *ast = crtc->dev->dev_private;
513 struct drm_gem_object *obj;
514 struct ast_framebuffer *ast_fb;
515 struct ast_bo *bo;
516 int ret;
517 u64 gpu_addr;
518
519 /* push the previous fb to system ram */
520 if (!atomic && fb) {
521 ast_fb = to_ast_framebuffer(fb);
522 obj = ast_fb->obj;
523 bo = gem_to_ast_bo(obj);
524 ret = ast_bo_reserve(bo, false);
525 if (ret)
526 return ret;
527 ast_bo_push_sysram(bo);
528 ast_bo_unreserve(bo);
529 }
530
531 ast_fb = to_ast_framebuffer(crtc->primary->fb);
532 obj = ast_fb->obj;
533 bo = gem_to_ast_bo(obj);
534
535 ret = ast_bo_reserve(bo, false);
536 if (ret)
537 return ret;
538
539 ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
540 if (ret) {
541 ast_bo_unreserve(bo);
542 return ret;
543 }
544
545 if (&ast->fbdev->afb == ast_fb) {
546 /* if pushing console in kmap it */
547 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap);
548 if (ret)
549 DRM_ERROR("failed to kmap fbcon\n");
550 else
551 ast_fbdev_set_base(ast, gpu_addr);
552 }
553 ast_bo_unreserve(bo);
554
555 ast_set_offset_reg(crtc);
556 ast_set_start_address_crt1(crtc, (u32)gpu_addr);
557
558 return 0;
559 }
560
ast_crtc_mode_set_base(struct drm_crtc * crtc,int x,int y,struct drm_framebuffer * old_fb)561 static int ast_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
562 struct drm_framebuffer *old_fb)
563 {
564 return ast_crtc_do_set_base(crtc, old_fb, x, y, 0);
565 }
566
ast_crtc_mode_set(struct drm_crtc * crtc,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode,int x,int y,struct drm_framebuffer * old_fb)567 static int ast_crtc_mode_set(struct drm_crtc *crtc,
568 struct drm_display_mode *mode,
569 struct drm_display_mode *adjusted_mode,
570 int x, int y,
571 struct drm_framebuffer *old_fb)
572 {
573 struct drm_device *dev = crtc->dev;
574 struct ast_private *ast = crtc->dev->dev_private;
575 struct ast_vbios_mode_info vbios_mode;
576 bool ret;
577 if (ast->chip == AST1180) {
578 DRM_ERROR("AST 1180 modesetting not supported\n");
579 return -EINVAL;
580 }
581
582 ret = ast_get_vbios_mode_info(crtc, mode, adjusted_mode, &vbios_mode);
583 if (ret == false)
584 return -EINVAL;
585 ast_open_key(ast);
586
587 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x04);
588
589 ast_set_std_reg(crtc, adjusted_mode, &vbios_mode);
590 ast_set_crtc_reg(crtc, adjusted_mode, &vbios_mode);
591 ast_set_offset_reg(crtc);
592 ast_set_dclk_reg(dev, adjusted_mode, &vbios_mode);
593 ast_set_ext_reg(crtc, adjusted_mode, &vbios_mode);
594 ast_set_sync_reg(dev, adjusted_mode, &vbios_mode);
595 ast_set_dac_reg(crtc, adjusted_mode, &vbios_mode);
596
597 ast_crtc_mode_set_base(crtc, x, y, old_fb);
598
599 return 0;
600 }
601
ast_crtc_disable(struct drm_crtc * crtc)602 static void ast_crtc_disable(struct drm_crtc *crtc)
603 {
604
605 }
606
ast_crtc_prepare(struct drm_crtc * crtc)607 static void ast_crtc_prepare(struct drm_crtc *crtc)
608 {
609
610 }
611
ast_crtc_commit(struct drm_crtc * crtc)612 static void ast_crtc_commit(struct drm_crtc *crtc)
613 {
614 struct ast_private *ast = crtc->dev->dev_private;
615 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0);
616 }
617
618
619 static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = {
620 .dpms = ast_crtc_dpms,
621 .mode_fixup = ast_crtc_mode_fixup,
622 .mode_set = ast_crtc_mode_set,
623 .mode_set_base = ast_crtc_mode_set_base,
624 .disable = ast_crtc_disable,
625 .load_lut = ast_crtc_load_lut,
626 .prepare = ast_crtc_prepare,
627 .commit = ast_crtc_commit,
628
629 };
630
ast_crtc_reset(struct drm_crtc * crtc)631 static void ast_crtc_reset(struct drm_crtc *crtc)
632 {
633
634 }
635
ast_crtc_gamma_set(struct drm_crtc * crtc,u16 * red,u16 * green,u16 * blue,uint32_t start,uint32_t size)636 static void ast_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
637 u16 *blue, uint32_t start, uint32_t size)
638 {
639 struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
640 int end = (start + size > 256) ? 256 : start + size, i;
641
642 /* userspace palettes are always correct as is */
643 for (i = start; i < end; i++) {
644 ast_crtc->lut_r[i] = red[i] >> 8;
645 ast_crtc->lut_g[i] = green[i] >> 8;
646 ast_crtc->lut_b[i] = blue[i] >> 8;
647 }
648 ast_crtc_load_lut(crtc);
649 }
650
651
ast_crtc_destroy(struct drm_crtc * crtc)652 static void ast_crtc_destroy(struct drm_crtc *crtc)
653 {
654 drm_crtc_cleanup(crtc);
655 kfree(crtc);
656 }
657
658 static const struct drm_crtc_funcs ast_crtc_funcs = {
659 .cursor_set = ast_cursor_set,
660 .cursor_move = ast_cursor_move,
661 .reset = ast_crtc_reset,
662 .set_config = drm_crtc_helper_set_config,
663 .gamma_set = ast_crtc_gamma_set,
664 .destroy = ast_crtc_destroy,
665 };
666
ast_crtc_init(struct drm_device * dev)667 static int ast_crtc_init(struct drm_device *dev)
668 {
669 struct ast_crtc *crtc;
670 int i;
671
672 crtc = kzalloc(sizeof(struct ast_crtc), GFP_KERNEL);
673 if (!crtc)
674 return -ENOMEM;
675
676 drm_crtc_init(dev, &crtc->base, &ast_crtc_funcs);
677 drm_mode_crtc_set_gamma_size(&crtc->base, 256);
678 drm_crtc_helper_add(&crtc->base, &ast_crtc_helper_funcs);
679
680 for (i = 0; i < 256; i++) {
681 crtc->lut_r[i] = i;
682 crtc->lut_g[i] = i;
683 crtc->lut_b[i] = i;
684 }
685 return 0;
686 }
687
ast_encoder_destroy(struct drm_encoder * encoder)688 static void ast_encoder_destroy(struct drm_encoder *encoder)
689 {
690 drm_encoder_cleanup(encoder);
691 kfree(encoder);
692 }
693
694
ast_best_single_encoder(struct drm_connector * connector)695 static struct drm_encoder *ast_best_single_encoder(struct drm_connector *connector)
696 {
697 int enc_id = connector->encoder_ids[0];
698 /* pick the encoder ids */
699 if (enc_id)
700 return drm_encoder_find(connector->dev, enc_id);
701 return NULL;
702 }
703
704
705 static const struct drm_encoder_funcs ast_enc_funcs = {
706 .destroy = ast_encoder_destroy,
707 };
708
ast_encoder_dpms(struct drm_encoder * encoder,int mode)709 static void ast_encoder_dpms(struct drm_encoder *encoder, int mode)
710 {
711
712 }
713
ast_mode_fixup(struct drm_encoder * encoder,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)714 static bool ast_mode_fixup(struct drm_encoder *encoder,
715 const struct drm_display_mode *mode,
716 struct drm_display_mode *adjusted_mode)
717 {
718 return true;
719 }
720
ast_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)721 static void ast_encoder_mode_set(struct drm_encoder *encoder,
722 struct drm_display_mode *mode,
723 struct drm_display_mode *adjusted_mode)
724 {
725 }
726
ast_encoder_prepare(struct drm_encoder * encoder)727 static void ast_encoder_prepare(struct drm_encoder *encoder)
728 {
729
730 }
731
ast_encoder_commit(struct drm_encoder * encoder)732 static void ast_encoder_commit(struct drm_encoder *encoder)
733 {
734
735 }
736
737
738 static const struct drm_encoder_helper_funcs ast_enc_helper_funcs = {
739 .dpms = ast_encoder_dpms,
740 .mode_fixup = ast_mode_fixup,
741 .prepare = ast_encoder_prepare,
742 .commit = ast_encoder_commit,
743 .mode_set = ast_encoder_mode_set,
744 };
745
ast_encoder_init(struct drm_device * dev)746 static int ast_encoder_init(struct drm_device *dev)
747 {
748 struct ast_encoder *ast_encoder;
749
750 ast_encoder = kzalloc(sizeof(struct ast_encoder), GFP_KERNEL);
751 if (!ast_encoder)
752 return -ENOMEM;
753
754 drm_encoder_init(dev, &ast_encoder->base, &ast_enc_funcs,
755 DRM_MODE_ENCODER_DAC);
756 drm_encoder_helper_add(&ast_encoder->base, &ast_enc_helper_funcs);
757
758 ast_encoder->base.possible_crtcs = 1;
759 return 0;
760 }
761
ast_get_modes(struct drm_connector * connector)762 static int ast_get_modes(struct drm_connector *connector)
763 {
764 struct ast_connector *ast_connector = to_ast_connector(connector);
765 struct ast_private *ast = connector->dev->dev_private;
766 struct edid *edid;
767 int ret;
768 bool flags = false;
769 if (ast->tx_chip_type == AST_TX_DP501) {
770 ast->dp501_maxclk = 0xff;
771 edid = kmalloc(128, GFP_KERNEL);
772 if (!edid)
773 return -ENOMEM;
774
775 flags = ast_dp501_read_edid(connector->dev, (u8 *)edid);
776 if (flags)
777 ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev);
778 else
779 kfree(edid);
780 }
781 if (!flags)
782 edid = drm_get_edid(connector, &ast_connector->i2c->adapter);
783 if (edid) {
784 drm_mode_connector_update_edid_property(&ast_connector->base, edid);
785 ret = drm_add_edid_modes(connector, edid);
786 kfree(edid);
787 return ret;
788 } else
789 drm_mode_connector_update_edid_property(&ast_connector->base, NULL);
790 return 0;
791 }
792
ast_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)793 static int ast_mode_valid(struct drm_connector *connector,
794 struct drm_display_mode *mode)
795 {
796 struct ast_private *ast = connector->dev->dev_private;
797 int flags = MODE_NOMODE;
798 uint32_t jtemp;
799
800 if (ast->support_wide_screen) {
801 if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050))
802 return MODE_OK;
803 if ((mode->hdisplay == 1280) && (mode->vdisplay == 800))
804 return MODE_OK;
805 if ((mode->hdisplay == 1440) && (mode->vdisplay == 900))
806 return MODE_OK;
807 if ((mode->hdisplay == 1360) && (mode->vdisplay == 768))
808 return MODE_OK;
809 if ((mode->hdisplay == 1600) && (mode->vdisplay == 900))
810 return MODE_OK;
811
812 if ((ast->chip == AST2100) || (ast->chip == AST2200) || (ast->chip == AST2300) || (ast->chip == AST2400) || (ast->chip == AST1180)) {
813 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080))
814 return MODE_OK;
815
816 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) {
817 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
818 if (jtemp & 0x01)
819 return MODE_NOMODE;
820 else
821 return MODE_OK;
822 }
823 }
824 }
825 switch (mode->hdisplay) {
826 case 640:
827 if (mode->vdisplay == 480) flags = MODE_OK;
828 break;
829 case 800:
830 if (mode->vdisplay == 600) flags = MODE_OK;
831 break;
832 case 1024:
833 if (mode->vdisplay == 768) flags = MODE_OK;
834 break;
835 case 1280:
836 if (mode->vdisplay == 1024) flags = MODE_OK;
837 break;
838 case 1600:
839 if (mode->vdisplay == 1200) flags = MODE_OK;
840 break;
841 default:
842 return flags;
843 }
844
845 return flags;
846 }
847
ast_connector_destroy(struct drm_connector * connector)848 static void ast_connector_destroy(struct drm_connector *connector)
849 {
850 struct ast_connector *ast_connector = to_ast_connector(connector);
851 ast_i2c_destroy(ast_connector->i2c);
852 drm_connector_unregister(connector);
853 drm_connector_cleanup(connector);
854 kfree(connector);
855 }
856
857 static enum drm_connector_status
ast_connector_detect(struct drm_connector * connector,bool force)858 ast_connector_detect(struct drm_connector *connector, bool force)
859 {
860 return connector_status_connected;
861 }
862
863 static const struct drm_connector_helper_funcs ast_connector_helper_funcs = {
864 .mode_valid = ast_mode_valid,
865 .get_modes = ast_get_modes,
866 .best_encoder = ast_best_single_encoder,
867 };
868
869 static const struct drm_connector_funcs ast_connector_funcs = {
870 .dpms = drm_helper_connector_dpms,
871 .detect = ast_connector_detect,
872 .fill_modes = drm_helper_probe_single_connector_modes,
873 .destroy = ast_connector_destroy,
874 };
875
ast_connector_init(struct drm_device * dev)876 static int ast_connector_init(struct drm_device *dev)
877 {
878 struct ast_connector *ast_connector;
879 struct drm_connector *connector;
880 struct drm_encoder *encoder;
881
882 ast_connector = kzalloc(sizeof(struct ast_connector), GFP_KERNEL);
883 if (!ast_connector)
884 return -ENOMEM;
885
886 connector = &ast_connector->base;
887 drm_connector_init(dev, connector, &ast_connector_funcs, DRM_MODE_CONNECTOR_VGA);
888
889 drm_connector_helper_add(connector, &ast_connector_helper_funcs);
890
891 connector->interlace_allowed = 0;
892 connector->doublescan_allowed = 0;
893
894 drm_connector_register(connector);
895
896 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
897
898 encoder = list_first_entry(&dev->mode_config.encoder_list, struct drm_encoder, head);
899 drm_mode_connector_attach_encoder(connector, encoder);
900
901 ast_connector->i2c = ast_i2c_create(dev);
902 if (!ast_connector->i2c)
903 DRM_ERROR("failed to add ddc bus for connector\n");
904
905 return 0;
906 }
907
908 /* allocate cursor cache and pin at start of VRAM */
ast_cursor_init(struct drm_device * dev)909 static int ast_cursor_init(struct drm_device *dev)
910 {
911 struct ast_private *ast = dev->dev_private;
912 int size;
913 int ret;
914 struct drm_gem_object *obj;
915 struct ast_bo *bo;
916 uint64_t gpu_addr;
917
918 size = (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE) * AST_DEFAULT_HWC_NUM;
919
920 ret = ast_gem_create(dev, size, true, &obj);
921 if (ret)
922 return ret;
923 bo = gem_to_ast_bo(obj);
924 ret = ast_bo_reserve(bo, false);
925 if (unlikely(ret != 0))
926 goto fail;
927
928 ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
929 ast_bo_unreserve(bo);
930 if (ret)
931 goto fail;
932
933 /* kmap the object */
934 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &ast->cache_kmap);
935 if (ret)
936 goto fail;
937
938 ast->cursor_cache = obj;
939 ast->cursor_cache_gpu_addr = gpu_addr;
940 DRM_DEBUG_KMS("pinned cursor cache at %llx\n", ast->cursor_cache_gpu_addr);
941 return 0;
942 fail:
943 return ret;
944 }
945
ast_cursor_fini(struct drm_device * dev)946 static void ast_cursor_fini(struct drm_device *dev)
947 {
948 struct ast_private *ast = dev->dev_private;
949 ttm_bo_kunmap(&ast->cache_kmap);
950 drm_gem_object_unreference_unlocked(ast->cursor_cache);
951 }
952
ast_mode_init(struct drm_device * dev)953 int ast_mode_init(struct drm_device *dev)
954 {
955 ast_cursor_init(dev);
956 ast_crtc_init(dev);
957 ast_encoder_init(dev);
958 ast_connector_init(dev);
959 return 0;
960 }
961
ast_mode_fini(struct drm_device * dev)962 void ast_mode_fini(struct drm_device *dev)
963 {
964 ast_cursor_fini(dev);
965 }
966
get_clock(void * i2c_priv)967 static int get_clock(void *i2c_priv)
968 {
969 struct ast_i2c_chan *i2c = i2c_priv;
970 struct ast_private *ast = i2c->dev->dev_private;
971 uint32_t val, val2, count, pass;
972
973 count = 0;
974 pass = 0;
975 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
976 do {
977 val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
978 if (val == val2) {
979 pass++;
980 } else {
981 pass = 0;
982 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
983 }
984 } while ((pass < 5) && (count++ < 0x10000));
985
986 return val & 1 ? 1 : 0;
987 }
988
get_data(void * i2c_priv)989 static int get_data(void *i2c_priv)
990 {
991 struct ast_i2c_chan *i2c = i2c_priv;
992 struct ast_private *ast = i2c->dev->dev_private;
993 uint32_t val, val2, count, pass;
994
995 count = 0;
996 pass = 0;
997 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
998 do {
999 val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
1000 if (val == val2) {
1001 pass++;
1002 } else {
1003 pass = 0;
1004 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
1005 }
1006 } while ((pass < 5) && (count++ < 0x10000));
1007
1008 return val & 1 ? 1 : 0;
1009 }
1010
set_clock(void * i2c_priv,int clock)1011 static void set_clock(void *i2c_priv, int clock)
1012 {
1013 struct ast_i2c_chan *i2c = i2c_priv;
1014 struct ast_private *ast = i2c->dev->dev_private;
1015 int i;
1016 u8 ujcrb7, jtemp;
1017
1018 for (i = 0; i < 0x10000; i++) {
1019 ujcrb7 = ((clock & 0x01) ? 0 : 1);
1020 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf4, ujcrb7);
1021 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01);
1022 if (ujcrb7 == jtemp)
1023 break;
1024 }
1025 }
1026
set_data(void * i2c_priv,int data)1027 static void set_data(void *i2c_priv, int data)
1028 {
1029 struct ast_i2c_chan *i2c = i2c_priv;
1030 struct ast_private *ast = i2c->dev->dev_private;
1031 int i;
1032 u8 ujcrb7, jtemp;
1033
1034 for (i = 0; i < 0x10000; i++) {
1035 ujcrb7 = ((data & 0x01) ? 0 : 1) << 2;
1036 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf1, ujcrb7);
1037 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04);
1038 if (ujcrb7 == jtemp)
1039 break;
1040 }
1041 }
1042
ast_i2c_create(struct drm_device * dev)1043 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev)
1044 {
1045 struct ast_i2c_chan *i2c;
1046 int ret;
1047
1048 i2c = kzalloc(sizeof(struct ast_i2c_chan), GFP_KERNEL);
1049 if (!i2c)
1050 return NULL;
1051
1052 i2c->adapter.owner = THIS_MODULE;
1053 i2c->adapter.class = I2C_CLASS_DDC;
1054 i2c->adapter.dev.parent = &dev->pdev->dev;
1055 i2c->dev = dev;
1056 i2c_set_adapdata(&i2c->adapter, i2c);
1057 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
1058 "AST i2c bit bus");
1059 i2c->adapter.algo_data = &i2c->bit;
1060
1061 i2c->bit.udelay = 20;
1062 i2c->bit.timeout = 2;
1063 i2c->bit.data = i2c;
1064 i2c->bit.setsda = set_data;
1065 i2c->bit.setscl = set_clock;
1066 i2c->bit.getsda = get_data;
1067 i2c->bit.getscl = get_clock;
1068 ret = i2c_bit_add_bus(&i2c->adapter);
1069 if (ret) {
1070 DRM_ERROR("Failed to register bit i2c\n");
1071 goto out_free;
1072 }
1073
1074 return i2c;
1075 out_free:
1076 kfree(i2c);
1077 return NULL;
1078 }
1079
ast_i2c_destroy(struct ast_i2c_chan * i2c)1080 static void ast_i2c_destroy(struct ast_i2c_chan *i2c)
1081 {
1082 if (!i2c)
1083 return;
1084 i2c_del_adapter(&i2c->adapter);
1085 kfree(i2c);
1086 }
1087
ast_show_cursor(struct drm_crtc * crtc)1088 static void ast_show_cursor(struct drm_crtc *crtc)
1089 {
1090 struct ast_private *ast = crtc->dev->dev_private;
1091 u8 jreg;
1092
1093 jreg = 0x2;
1094 /* enable ARGB cursor */
1095 jreg |= 1;
1096 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, jreg);
1097 }
1098
ast_hide_cursor(struct drm_crtc * crtc)1099 static void ast_hide_cursor(struct drm_crtc *crtc)
1100 {
1101 struct ast_private *ast = crtc->dev->dev_private;
1102 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, 0x00);
1103 }
1104
copy_cursor_image(u8 * src,u8 * dst,int width,int height)1105 static u32 copy_cursor_image(u8 *src, u8 *dst, int width, int height)
1106 {
1107 union {
1108 u32 ul;
1109 u8 b[4];
1110 } srcdata32[2], data32;
1111 union {
1112 u16 us;
1113 u8 b[2];
1114 } data16;
1115 u32 csum = 0;
1116 s32 alpha_dst_delta, last_alpha_dst_delta;
1117 u8 *srcxor, *dstxor;
1118 int i, j;
1119 u32 per_pixel_copy, two_pixel_copy;
1120
1121 alpha_dst_delta = AST_MAX_HWC_WIDTH << 1;
1122 last_alpha_dst_delta = alpha_dst_delta - (width << 1);
1123
1124 srcxor = src;
1125 dstxor = (u8 *)dst + last_alpha_dst_delta + (AST_MAX_HWC_HEIGHT - height) * alpha_dst_delta;
1126 per_pixel_copy = width & 1;
1127 two_pixel_copy = width >> 1;
1128
1129 for (j = 0; j < height; j++) {
1130 for (i = 0; i < two_pixel_copy; i++) {
1131 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
1132 srcdata32[1].ul = *((u32 *)(srcxor + 4)) & 0xf0f0f0f0;
1133 data32.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
1134 data32.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
1135 data32.b[2] = srcdata32[1].b[1] | (srcdata32[1].b[0] >> 4);
1136 data32.b[3] = srcdata32[1].b[3] | (srcdata32[1].b[2] >> 4);
1137
1138 writel(data32.ul, dstxor);
1139 csum += data32.ul;
1140
1141 dstxor += 4;
1142 srcxor += 8;
1143
1144 }
1145
1146 for (i = 0; i < per_pixel_copy; i++) {
1147 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
1148 data16.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
1149 data16.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
1150 writew(data16.us, dstxor);
1151 csum += (u32)data16.us;
1152
1153 dstxor += 2;
1154 srcxor += 4;
1155 }
1156 dstxor += last_alpha_dst_delta;
1157 }
1158 return csum;
1159 }
1160
ast_cursor_set(struct drm_crtc * crtc,struct drm_file * file_priv,uint32_t handle,uint32_t width,uint32_t height)1161 static int ast_cursor_set(struct drm_crtc *crtc,
1162 struct drm_file *file_priv,
1163 uint32_t handle,
1164 uint32_t width,
1165 uint32_t height)
1166 {
1167 struct ast_private *ast = crtc->dev->dev_private;
1168 struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
1169 struct drm_gem_object *obj;
1170 struct ast_bo *bo;
1171 uint64_t gpu_addr;
1172 u32 csum;
1173 int ret;
1174 struct ttm_bo_kmap_obj uobj_map;
1175 u8 *src, *dst;
1176 bool src_isiomem, dst_isiomem;
1177 if (!handle) {
1178 ast_hide_cursor(crtc);
1179 return 0;
1180 }
1181
1182 if (width > AST_MAX_HWC_WIDTH || height > AST_MAX_HWC_HEIGHT)
1183 return -EINVAL;
1184
1185 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
1186 if (!obj) {
1187 DRM_ERROR("Cannot find cursor object %x for crtc\n", handle);
1188 return -ENOENT;
1189 }
1190 bo = gem_to_ast_bo(obj);
1191
1192 ret = ast_bo_reserve(bo, false);
1193 if (ret)
1194 goto fail;
1195
1196 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &uobj_map);
1197
1198 src = ttm_kmap_obj_virtual(&uobj_map, &src_isiomem);
1199 dst = ttm_kmap_obj_virtual(&ast->cache_kmap, &dst_isiomem);
1200
1201 if (src_isiomem == true)
1202 DRM_ERROR("src cursor bo should be in main memory\n");
1203 if (dst_isiomem == false)
1204 DRM_ERROR("dst bo should be in VRAM\n");
1205
1206 dst += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor;
1207
1208 /* do data transfer to cursor cache */
1209 csum = copy_cursor_image(src, dst, width, height);
1210
1211 /* write checksum + signature */
1212 ttm_bo_kunmap(&uobj_map);
1213 ast_bo_unreserve(bo);
1214 {
1215 u8 *dst = (u8 *)ast->cache_kmap.virtual + (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE;
1216 writel(csum, dst);
1217 writel(width, dst + AST_HWC_SIGNATURE_SizeX);
1218 writel(height, dst + AST_HWC_SIGNATURE_SizeY);
1219 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTX);
1220 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY);
1221
1222 /* set pattern offset */
1223 gpu_addr = ast->cursor_cache_gpu_addr;
1224 gpu_addr += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor;
1225 gpu_addr >>= 3;
1226 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, gpu_addr & 0xff);
1227 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, (gpu_addr >> 8) & 0xff);
1228 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, (gpu_addr >> 16) & 0xff);
1229 }
1230 ast_crtc->cursor_width = width;
1231 ast_crtc->cursor_height = height;
1232 ast_crtc->offset_x = AST_MAX_HWC_WIDTH - width;
1233 ast_crtc->offset_y = AST_MAX_HWC_WIDTH - height;
1234
1235 ast->next_cursor = (ast->next_cursor + 1) % AST_DEFAULT_HWC_NUM;
1236
1237 ast_show_cursor(crtc);
1238
1239 drm_gem_object_unreference_unlocked(obj);
1240 return 0;
1241 fail:
1242 drm_gem_object_unreference_unlocked(obj);
1243 return ret;
1244 }
1245
ast_cursor_move(struct drm_crtc * crtc,int x,int y)1246 static int ast_cursor_move(struct drm_crtc *crtc,
1247 int x, int y)
1248 {
1249 struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
1250 struct ast_private *ast = crtc->dev->dev_private;
1251 int x_offset, y_offset;
1252 u8 *sig;
1253
1254 sig = (u8 *)ast->cache_kmap.virtual + (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE;
1255 writel(x, sig + AST_HWC_SIGNATURE_X);
1256 writel(y, sig + AST_HWC_SIGNATURE_Y);
1257
1258 x_offset = ast_crtc->offset_x;
1259 y_offset = ast_crtc->offset_y;
1260 if (x < 0) {
1261 x_offset = (-x) + ast_crtc->offset_x;
1262 x = 0;
1263 }
1264
1265 if (y < 0) {
1266 y_offset = (-y) + ast_crtc->offset_y;
1267 y = 0;
1268 }
1269 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset);
1270 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset);
1271 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, (x & 0xff));
1272 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, ((x >> 8) & 0x0f));
1273 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, (y & 0xff));
1274 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, ((y >> 8) & 0x07));
1275
1276 /* dummy write to fire HWC */
1277 ast_show_cursor(crtc);
1278
1279 return 0;
1280 }
1281