| /drivers/staging/media/omap4iss/ |
| D | iss_csiphy.c | 40 reg |= (phy->lanes.data[i].pol ? in csiphy_lanes_config()
42 reg |= (phy->lanes.data[i].pos << in csiphy_lanes_config()
48 reg |= phy->lanes.clk.pol ? CSI2_COMPLEXIO_CFG_CLOCK_POL : 0; in csiphy_lanes_config()
49 reg |= phy->lanes.clk.pos << CSI2_COMPLEXIO_CFG_CLOCK_POSITION_SHIFT; in csiphy_lanes_config()
127 struct iss_csiphy_lanes_cfg *lanes; in omap4iss_csiphy_config() local
132 lanes = &subdevs->bus.csi2.lanecfg; in omap4iss_csiphy_config()
179 if (lanes->data[i].pos == 0) in omap4iss_csiphy_config()
182 if (lanes->data[i].pol > 1 || in omap4iss_csiphy_config()
183 lanes->data[i].pos > (csi2->phy->max_data_lanes + 1)) in omap4iss_csiphy_config()
186 if (used_lanes & (1 << lanes->data[i].pos)) in omap4iss_csiphy_config()
[all …]
|
| D | iss_csiphy.h | 41 struct iss_csiphy_lanes_cfg lanes; member
|
| /drivers/media/platform/omap3isp/ |
| D | ispcsiphy.c | 170 struct isp_csiphy_lanes_cfg *lanes; in omap3isp_csiphy_config() local
185 lanes = &buscfg->bus.ccp2.lanecfg; in omap3isp_csiphy_config()
187 lanes = &buscfg->bus.csi2.lanecfg; in omap3isp_csiphy_config()
191 if (lanes->data[i].pol > 1 || lanes->data[i].pos > 3) in omap3isp_csiphy_config()
194 if (used_lanes & (1 << lanes->data[i].pos)) in omap3isp_csiphy_config()
197 used_lanes |= 1 << lanes->data[i].pos; in omap3isp_csiphy_config()
200 if (lanes->clk.pol > 1 || lanes->clk.pos > 3) in omap3isp_csiphy_config()
203 if (lanes->clk.pos == 0 || used_lanes & (1 << lanes->clk.pos)) in omap3isp_csiphy_config()
249 reg |= (lanes->data[i].pol << in omap3isp_csiphy_config()
251 reg |= (lanes->data[i].pos << in omap3isp_csiphy_config()
[all …]
|
| /drivers/video/fbdev/omap2/dss/ |
| D | hdmi_common.c | 19 u32 lanes[8]; in hdmi_parse_lanes_of() local
21 if (len / sizeof(u32) != ARRAY_SIZE(lanes)) { in hdmi_parse_lanes_of()
26 r = of_property_read_u32_array(ep, "lanes", lanes, in hdmi_parse_lanes_of()
27 ARRAY_SIZE(lanes)); in hdmi_parse_lanes_of()
33 r = hdmi_phy_parse_lanes(phy, lanes); in hdmi_parse_lanes_of()
|
| D | hdmi_phy.c | 42 int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes) in hdmi_phy_parse_lanes() argument
50 dx = lanes[i]; in hdmi_phy_parse_lanes()
51 dy = lanes[i + 1]; in hdmi_phy_parse_lanes()
|
| D | dsi.c | 380 struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; member
1841 if (dsi->lanes[t].function == functions[i]) in dsi_set_lane_config()
1848 polarity = dsi->lanes[t].polarity; in dsi_set_lane_config()
1973 unsigned p = dsi->lanes[i].polarity; in dsi_cio_enable_lane_override()
2026 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED; in dsi_cio_wait_tx_clk_esc_reset()
2067 if (dsi->lanes[i].function != DSI_LANE_UNUSED) in dsi_get_lane_mask()
2129 if (dsi->lanes[i].function == DSI_LANE_UNUSED) in dsi_cio_init()
3179 if (dsi->lanes[i].function == DSI_LANE_UNUSED) in dsi_enter_ulps()
3765 struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; in dsi_configure_pins() local
3785 lanes[i].function = DSI_LANE_UNUSED; in dsi_configure_pins()
[all …]
|
| /drivers/gpu/drm/tegra/ |
| D | dsi.c | 38 unsigned int lanes; member
71 unsigned int lanes; member
490 return dsi->master->lanes + dsi->lanes; in tegra_dsi_get_lanes()
493 return dsi->lanes + dsi->slave->lanes; in tegra_dsi_get_lanes()
495 return dsi->lanes; in tegra_dsi_get_lanes()
528 DSI_CONTROL_LANES(dsi->lanes - 1) | in tegra_dsi_configure()
612 unsigned int lanes = state->lanes; in tegra_dsi_configure() local
616 delay = DIV_ROUND_UP(delay * mul, div * lanes); in tegra_dsi_configure()
620 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes); in tegra_dsi_configure()
621 bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes); in tegra_dsi_configure()
[all …]
|
| /drivers/media/platform/soc_camera/ |
| D | sh_mobile_csi2.c | 148 if (priv->client->lanes != 1) in sh_csi2_g_mbus_config()
152 switch (priv->client->lanes) { in sh_csi2_g_mbus_config()
232 if (priv->client->lanes == 1) in sh_csi2_hwinit()
239 if (!priv->client->lanes || priv->client->lanes > 4) in sh_csi2_hwinit()
243 tmp |= (1 << priv->client->lanes) - 1; in sh_csi2_hwinit()
|
| /drivers/nubus/ |
| D | nubus.c | 211 dir->mask = board->lanes; in nubus_get_root_dir()
222 dir->mask = dev->board->lanes; in nubus_get_func_dir()
234 dir->mask = board->lanes; in nubus_get_board_dir()
732 nubus_rewind(&rp, 4, board->lanes); in nubus_find_rom_dir()
733 if (nubus_get_rom(&rp, 4, board->lanes) != NUBUS_TEST_PATTERN) { in nubus_find_rom_dir()
738 board->lanes); in nubus_find_rom_dir()
747 nubus_rewind(&romdir, ROM_DIR_OFFSET, board->lanes); in nubus_find_rom_dir()
750 dir.mask = board->lanes; in nubus_find_rom_dir()
794 nubus_move(&board->directory, nubus_expand32(board->doffset), board->lanes); in nubus_find_rom_dir()
847 board->lanes = bytelanes; in nubus_add_board()
|
| /drivers/gpu/drm/gma500/ |
| D | intel_bios.c | 102 switch (edp_link_params->lanes) { in parse_edp()
104 dev_priv->edp.lanes = 1; in parse_edp()
107 dev_priv->edp.lanes = 2; in parse_edp()
111 dev_priv->edp.lanes = 4; in parse_edp()
115 dev_priv->edp.lanes, dev_priv->edp.rate, dev_priv->edp.bpp); in parse_edp()
|
| /drivers/media/i2c/ |
| D | tc358743.c | 691 unsigned lanes = tc358743_num_csi_lanes_needed(sd); in tc358743_set_csi() local
697 if (lanes < 1) in tc358743_set_csi()
699 if (lanes < 1) in tc358743_set_csi()
701 if (lanes < 2) in tc358743_set_csi()
703 if (lanes < 3) in tc358743_set_csi()
705 if (lanes < 4) in tc358743_set_csi()
719 ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) | in tc358743_set_csi()
720 ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) | in tc358743_set_csi()
721 ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) | in tc358743_set_csi()
722 ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) | in tc358743_set_csi()
[all …]
|
| D | smiapp-pll.h | 42 uint8_t lanes; member
|
| D | smiapp-pll.c | 418 lane_op_clock_ratio = pll->csi2.lanes; in smiapp_pll_calculate()
430 * (pll->csi2.lanes / lane_op_clock_ratio); in smiapp_pll_calculate()
|
| /drivers/pci/host/ |
| D | pci-xgene.c | 209 u32 *lanes, u32 *speed) in xgene_pcie_linkup() argument
220 *lanes = val32 >> 26; in xgene_pcie_linkup()
486 u32 val, lanes = 0, speed = 0; in xgene_pcie_setup() local
503 xgene_pcie_linkup(port, &lanes, &speed); in xgene_pcie_setup()
508 lanes, speed + 1); in xgene_pcie_setup()
|
| D | pci-tegra.c | 314 unsigned int lanes; member
1369 static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes, in tegra_pcie_get_xbar_config() argument
1375 switch (lanes) { in tegra_pcie_get_xbar_config()
1387 switch (lanes) { in tegra_pcie_get_xbar_config()
1404 switch (lanes) { in tegra_pcie_get_xbar_config()
1584 u32 lanes = 0, mask = 0; in tegra_pcie_parse_dt() local
1692 lanes |= value << (index << 3); in tegra_pcie_parse_dt()
1715 rp->lanes = value; in tegra_pcie_parse_dt()
1725 err = tegra_pcie_get_xbar_config(pcie, lanes, &pcie->xbar_config); in tegra_pcie_parse_dt()
1798 port->index, port->lanes); in tegra_pcie_enable()
|
| D | pcie-designware.c | 494 ret = of_property_read_u32(np, "num-lanes", &pp->lanes); in dw_pcie_host_init()
496 pp->lanes = 0; in dw_pcie_host_init()
717 switch (pp->lanes) { in dw_pcie_setup_rc()
731 dev_err(pp->dev, "num-lanes %u: invalid value\n", pp->lanes); in dw_pcie_setup_rc()
739 switch (pp->lanes) { in dw_pcie_setup_rc()
|
| D | pcie-designware.h | 46 u32 lanes; member
|
| /drivers/gpu/drm/panel/ |
| D | panel-simple.c | 1237 unsigned int lanes; member
1265 .lanes = 4,
1293 .lanes = 4,
1321 .lanes = 4,
1350 .lanes = 4,
1390 dsi->lanes = desc->lanes; in panel_simple_dsi_probe()
|
| /drivers/pinctrl/ |
| D | pinctrl-tegra-xusb.c | 69 const struct tegra_xusb_padctl_lane *lanes; member
309 lane = &padctl->soc->lanes[group]; in tegra_xusb_padctl_pinmux_set()
343 lane = &padctl->soc->lanes[group]; in tegra_xusb_padctl_pinconf_group_get()
382 lane = &padctl->soc->lanes[group]; in tegra_xusb_padctl_pinconf_group_set()
865 .lanes = tegra124_lanes,
|
| /drivers/gpu/drm/msm/dsi/ |
| D | dsi_host.c | 132 unsigned int lanes; member
520 u8 lanes = msm_host->lanes; in dsi_calc_clk_rate() local
530 if (lanes > 0) { in dsi_calc_clk_rate()
531 msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes); in dsi_calc_clk_rate()
688 DBG("lane number=%d", msm_host->lanes); in dsi_ctrl_config()
689 if (msm_host->lanes == 2) { in dsi_ctrl_config()
1295 msm_host->lanes = dsi->lanes; in dsi_host_attach()
|
| /drivers/edac/ |
| D | ppc4xx_edac.c | 442 unsigned int lane, lanes; in ppc4xx_edac_generate_lane_message() local
455 for (lanes = 0, lane = first_lane; lane < lane_count; lane++) { in ppc4xx_edac_generate_lane_message()
459 (lanes++ ? ", " : ""), lane); in ppc4xx_edac_generate_lane_message()
470 n = snprintf(buffer, size, "%s; ", lanes ? "" : "None"); in ppc4xx_edac_generate_lane_message()
|
| /drivers/net/ethernet/ti/ |
| D | netcp_xgbepcsr.c | 315 void __iomem *sw_regs, u32 lanes, in netcp_xgbe_check_link_status() argument
323 for (i = 0; i < lanes; i++) { in netcp_xgbe_check_link_status()
|
| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_dpm.h | 83 u8 amdgpu_encode_pci_lane_width(u32 lanes);
|
| /drivers/scsi/ufs/ |
| D | ufs-qcom.c | 717 int lanes = max_t(u32, p->lane_rx, p->lane_tx); in ufs_qcom_get_speed_mode() local
724 if (!lanes) in ufs_qcom_get_speed_mode()
725 lanes = 1; in ufs_qcom_get_speed_mode()
734 p->hs_rate == PA_HS_MODE_B ? "B" : "A", gear, lanes); in ufs_qcom_get_speed_mode()
738 "PWM", gear, lanes); in ufs_qcom_get_speed_mode()
|
| /drivers/gpu/drm/exynos/ |
| D | exynos_drm_dsi.c | 279 u32 lanes; member
669 | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1) in exynos_dsi_enable_clock()
750 reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK | in exynos_dsi_enable_lane()
841 lanes_mask = BIT(dsi->lanes) - 1; in exynos_dsi_init_link()
1307 exynos_dsi_enable_lane(dsi, BIT(dsi->lanes) - 1); in exynos_dsi_init()
1365 dsi->lanes = device->lanes; in exynos_dsi_host_attach()
|