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Searched refs:lvds (Results 1 – 25 of 36) sorted by relevance

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/drivers/gpu/drm/rcar-du/
Drcar_du_lvdsenc.c36 static void rcar_lvds_write(struct rcar_du_lvdsenc *lvds, u32 reg, u32 data) in rcar_lvds_write() argument
38 iowrite32(data, lvds->mmio + reg); in rcar_lvds_write()
41 static int rcar_du_lvdsenc_start(struct rcar_du_lvdsenc *lvds, in rcar_du_lvdsenc_start() argument
51 if (lvds->enabled) in rcar_du_lvdsenc_start()
54 ret = clk_prepare_enable(lvds->clock); in rcar_du_lvdsenc_start()
68 rcar_lvds_write(lvds, LVDPLLCR, pllcr); in rcar_du_lvdsenc_start()
77 rcar_lvds_write(lvds, LVDCTRCR, LVDCTRCR_CTR3SEL_ZERO | in rcar_du_lvdsenc_start()
81 if (rcar_du_needs(lvds->dev, RCAR_DU_QUIRK_LVDS_LANES)) in rcar_du_lvdsenc_start()
88 rcar_lvds_write(lvds, LVDCHCR, lvdhcr); in rcar_du_lvdsenc_start()
96 rcar_lvds_write(lvds, LVDCR0, lvdcr0); in rcar_du_lvdsenc_start()
[all …]
Drcar_du_encoder.c49 if (renc->lvds) in rcar_du_encoder_disable()
50 rcar_du_lvdsenc_enable(renc->lvds, encoder->crtc, false); in rcar_du_encoder_disable()
57 if (renc->lvds) in rcar_du_encoder_enable()
58 rcar_du_lvdsenc_enable(renc->lvds, encoder->crtc, true); in rcar_du_encoder_enable()
95 if (renc->lvds) in rcar_du_encoder_atomic_check()
142 renc->lvds = rcdu->lvds[0]; in rcar_du_encoder_init()
146 renc->lvds = rcdu->lvds[1]; in rcar_du_encoder_init()
Drcar_du_hdmienc.c43 if (hdmienc->renc->lvds) in rcar_du_hdmienc_disable()
44 rcar_du_lvdsenc_enable(hdmienc->renc->lvds, encoder->crtc, in rcar_du_hdmienc_disable()
55 if (hdmienc->renc->lvds) in rcar_du_hdmienc_enable()
56 rcar_du_lvdsenc_enable(hdmienc->renc->lvds, encoder->crtc, in rcar_du_hdmienc_enable()
77 if (hdmienc->renc->lvds) in rcar_du_hdmienc_atomic_check()
Drcar_du_lvdsenc.h31 int rcar_du_lvdsenc_enable(struct rcar_du_lvdsenc *lvds,
38 static inline int rcar_du_lvdsenc_enable(struct rcar_du_lvdsenc *lvds, in rcar_du_lvdsenc_enable() argument
Drcar_du_encoder.h36 struct rcar_du_lvdsenc *lvds; member
/drivers/gpu/drm/radeon/
Dradeon_combios.c1104 struct radeon_encoder_lvds *lvds = NULL; in radeon_legacy_get_lvds_info_from_regs() local
1109 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); in radeon_legacy_get_lvds_info_from_regs()
1111 if (!lvds) in radeon_legacy_get_lvds_info_from_regs()
1118 lvds->panel_pwr_delay = 200; in radeon_legacy_get_lvds_info_from_regs()
1119 lvds->panel_vcc_delay = 2000; in radeon_legacy_get_lvds_info_from_regs()
1121 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_get_lvds_info_from_regs()
1122 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf; in radeon_legacy_get_lvds_info_from_regs()
1123 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf; in radeon_legacy_get_lvds_info_from_regs()
1126 lvds->native_mode.vdisplay = in radeon_legacy_get_lvds_info_from_regs()
1130 lvds->native_mode.vdisplay = in radeon_legacy_get_lvds_info_from_regs()
[all …]
Dradeon_legacy_encoders.c62 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; in radeon_legacy_lvds_update() local
63 panel_pwr_delay = lvds->panel_pwr_delay; in radeon_legacy_lvds_update()
64 if (lvds->bl_dev) in radeon_legacy_lvds_update()
65 backlight_level = lvds->backlight_level; in radeon_legacy_lvds_update()
67 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; in radeon_legacy_lvds_update() local
68 panel_pwr_delay = lvds->panel_pwr_delay; in radeon_legacy_lvds_update()
69 if (lvds->bl_dev) in radeon_legacy_lvds_update()
70 backlight_level = lvds->backlight_level; in radeon_legacy_lvds_update()
143 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; in radeon_legacy_lvds_dpms() local
144 lvds->dpms_mode = mode; in radeon_legacy_lvds_dpms()
[all …]
Dradeon_atombios.c1636 struct radeon_encoder_atom_dig *lvds = NULL; in radeon_atombios_get_lvds_info() local
1643 lvds = in radeon_atombios_get_lvds_info()
1646 if (!lvds) in radeon_atombios_get_lvds_info()
1649 lvds->native_mode.clock = in radeon_atombios_get_lvds_info()
1651 lvds->native_mode.hdisplay = in radeon_atombios_get_lvds_info()
1653 lvds->native_mode.vdisplay = in radeon_atombios_get_lvds_info()
1655 lvds->native_mode.htotal = lvds->native_mode.hdisplay + in radeon_atombios_get_lvds_info()
1657 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + in radeon_atombios_get_lvds_info()
1659 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + in radeon_atombios_get_lvds_info()
1661 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + in radeon_atombios_get_lvds_info()
[all …]
Dradeon_legacy_crtc.c801 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; in radeon_set_pll() local
802 if (lvds) { in radeon_set_pll()
803 if (lvds->use_bios_dividers) { in radeon_set_pll()
804 pll_ref_div = lvds->panel_ref_divider; in radeon_set_pll()
805 pll_fb_post_div = (lvds->panel_fb_divider | in radeon_set_pll()
806 (lvds->panel_post_divider << 16)); in radeon_set_pll()
/drivers/gpu/drm/amd/amdgpu/
Datombios_encoders.c1920 struct amdgpu_encoder_atom_dig *lvds = NULL; in amdgpu_atombios_encoder_get_lcd_info() local
1927 lvds = in amdgpu_atombios_encoder_get_lcd_info()
1930 if (!lvds) in amdgpu_atombios_encoder_get_lcd_info()
1933 lvds->native_mode.clock = in amdgpu_atombios_encoder_get_lcd_info()
1935 lvds->native_mode.hdisplay = in amdgpu_atombios_encoder_get_lcd_info()
1937 lvds->native_mode.vdisplay = in amdgpu_atombios_encoder_get_lcd_info()
1939 lvds->native_mode.htotal = lvds->native_mode.hdisplay + in amdgpu_atombios_encoder_get_lcd_info()
1941 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + in amdgpu_atombios_encoder_get_lcd_info()
1943 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + in amdgpu_atombios_encoder_get_lcd_info()
1945 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + in amdgpu_atombios_encoder_get_lcd_info()
[all …]
/drivers/staging/xgifb/
Dvb_init.c874 struct XGI21_LVDSCapStruct *lvds; in xgifb_read_vbios() local
912 lvds = &xgifb_info->lvds_data; in xgifb_read_vbios()
915 lvds->LVDS_Capability = vbios[i] | (vbios[i + 1] << 8); in xgifb_read_vbios()
916 lvds->LVDSHT = vbios[i + 2] | (vbios[i + 3] << 8); in xgifb_read_vbios()
917 lvds->LVDSVT = vbios[i + 4] | (vbios[i + 5] << 8); in xgifb_read_vbios()
918 lvds->LVDSHDE = vbios[i + 6] | (vbios[i + 7] << 8); in xgifb_read_vbios()
919 lvds->LVDSVDE = vbios[i + 8] | (vbios[i + 9] << 8); in xgifb_read_vbios()
920 lvds->LVDSHFP = vbios[i + 10] | (vbios[i + 11] << 8); in xgifb_read_vbios()
921 lvds->LVDSVFP = vbios[i + 12] | (vbios[i + 13] << 8); in xgifb_read_vbios()
922 lvds->LVDSHSYNC = vbios[i + 14] | (vbios[i + 15] << 8); in xgifb_read_vbios()
[all …]
/drivers/gpu/drm/gma500/
Dpsb_intel_display.c235 u32 lvds = REG_READ(LVDS); in psb_intel_crtc_mode_set() local
237 lvds &= ~LVDS_PIPEB_SELECT; in psb_intel_crtc_mode_set()
239 lvds |= LVDS_PIPEB_SELECT; in psb_intel_crtc_mode_set()
241 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; in psb_intel_crtc_mode_set()
246 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); in psb_intel_crtc_mode_set()
248 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; in psb_intel_crtc_mode_set()
255 REG_WRITE(LVDS, lvds); in psb_intel_crtc_mode_set()
Dcdv_intel_lvds.c619 u32 lvds; in cdv_intel_lvds_init() local
744 lvds = REG_READ(LVDS); in cdv_intel_lvds_init()
745 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; in cdv_intel_lvds_init()
748 if (crtc && (lvds & LVDS_PORT_EN)) { in cdv_intel_lvds_init()
Dcdv_intel_display.c751 u32 lvds = REG_READ(LVDS); in cdv_intel_crtc_mode_set() local
753 lvds |= in cdv_intel_crtc_mode_set()
761 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; in cdv_intel_crtc_mode_set()
763 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); in cdv_intel_crtc_mode_set()
770 REG_WRITE(LVDS, lvds); in cdv_intel_crtc_mode_set()
Dpsb_intel_lvds.c694 u32 lvds; in psb_intel_lvds_init() local
809 lvds = REG_READ(LVDS); in psb_intel_lvds_init()
810 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; in psb_intel_lvds_init()
813 if (crtc && (lvds & LVDS_PORT_EN)) { in psb_intel_lvds_init()
/drivers/gpu/drm/nouveau/
Dnv50_display.c1940 struct nv50_disp_sor_lvds_script_v0 lvds; in nv50_sor_mode_set() member
1941 } lvds = { in nv50_sor_mode_set() local
1979 lvds.lvds.script |= 0x0100; in nv50_sor_mode_set()
1981 lvds.lvds.script |= 0x0200; in nv50_sor_mode_set()
1985 lvds.lvds.script |= 0x0100; in nv50_sor_mode_set()
1988 lvds.lvds.script |= 0x0100; in nv50_sor_mode_set()
1991 if (lvds.lvds.script & 0x0100) { in nv50_sor_mode_set()
1993 lvds.lvds.script |= 0x0200; in nv50_sor_mode_set()
1996 lvds.lvds.script |= 0x0200; in nv50_sor_mode_set()
2000 lvds.lvds.script |= 0x0200; in nv50_sor_mode_set()
[all …]
/drivers/gpu/drm/i915/
Dintel_lvds.c951 u32 lvds; in intel_lvds_init() local
978 lvds = I915_READ(lvds_reg); in intel_lvds_init()
981 if ((lvds & LVDS_DETECTED) == 0) in intel_lvds_init()
991 if ((lvds & LVDS_PORT_EN) == 0) { in intel_lvds_init()
1149 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; in intel_lvds_init()
1152 if (crtc && (lvds & LVDS_PORT_EN)) { in intel_lvds_init()
/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dgk104.c38 .outp.internal.lvds = nv50_sor_output_new,
Dgm107.c38 .outp.internal.lvds = nv50_sor_output_new,
Dgk110.c38 .outp.internal.lvds = nv50_sor_output_new,
Dg84.c38 .outp.internal.lvds = nv50_sor_output_new,
Dgt200.c38 .outp.internal.lvds = nv50_sor_output_new,
Dgm204.c38 .outp.internal.lvds = nv50_sor_output_new,
Dg94.c38 .outp.internal.lvds = nv50_sor_output_new,
Dpriv.h20 int (*lvds)(struct nvkm_disp *, int index, struct dcb_output *, member

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