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Searched refs:mwidth (Results 1 – 9 of 9) sorted by relevance

/drivers/clk/
Dclk-fractional-divider.c75 GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0), in clk_fd_round_rate()
93 GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0), in clk_fd_set_rate()
123 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, in clk_register_fractional_divider() argument
142 fd->mwidth = mwidth; in clk_register_fractional_divider()
143 fd->mmask = GENMASK(mwidth - 1, 0) << mshift; in clk_register_fractional_divider()
/drivers/clk/sunxi/
Dclk-sun9i-core.c76 .mwidth = 1,
139 .mwidth = 2,
294 .mwidth = 5,
Dclk-factors.c61 if (config->mwidth != SUNXI_FACTORS_NOT_APPLICABLE) in clk_factors_recalc_rate()
62 m = FACTOR_GET(config->mshift, config->mwidth, reg); in clk_factors_recalc_rate()
140 reg = FACTOR_SET(config->mshift, config->mwidth, reg, m); in clk_factors_set_rate()
Dclk-sunxi.c617 .mwidth = 2,
628 .mwidth = 2,
638 .mwidth = 2,
666 .mwidth = 5,
674 .mwidth = 5,
Dclk-factors.h16 u8 mwidth; member
Dclk-sun8i-mbus.c57 .mwidth = 3,
Dclk-mod0.c67 .mwidth = 4,
/drivers/clk/rockchip/
Dclk.c145 div->mwidth = 16; in rockchip_clk_register_frac_branch()
146 div->mmask = GENMASK(div->mwidth - 1, 0) << div->mshift; in rockchip_clk_register_frac_branch()
/drivers/video/fbdev/aty/
Datyfb_base.c3303 u16 mwidth, mheight, lcd_hsync_start, lcd_vsync_start; in aty_init_lcd() local
3306 mwidth = *((u16 *)(modeptr+0)); in aty_init_lcd()
3309 if (mwidth == width && mheight == height) { in aty_init_lcd()